gonzalo delgado huitrón - nxp.com · tm freescale, the freescale logo, altivec, c-5, codetest,...

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t

he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony

are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,

ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ

Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property

of their respective owners. © 2011 Freescale Semiconductor, Inc.

Confidential and Proprietary

Mayo 2012

Gonzalo Delgado Huitrón

TM 2

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,

mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,

Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,

Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.

Robust and Reliable: industry leading EFT/ESD performance for

harsh environment and safety compliance with IEC-60730

Cost Effective: chose between bare bone PL class or the full

featured PT/PA class; reduce BOM cost with integrated EEPROM,

precision oscillator, high current IO and low Cost OSBDM; smart

pinout enables cheap single-side PCBs

Easy-to-Use: speed time to market and reduce R&D expenses with

C-friendly increased RAM/Flash ratio, simple yet powerful S08 core;

streamlined documentation; CodeWarrior support and Processor-

Expert initialization tool

Scalable & Compatible: Easy migration from existing S08

product with common core, IP and tools; consistent pinout across a

2K-60KB portfolio with a large choice of package options

Pillars for 5V S08P Family

... Building the Industry’s Most Trusted MCU Solutions

TM 3






S08P F

ea

ture

s &

P

erf

orm

an

ce

• Bare Bone Family

• 10Mhz

• 4KB RAM; 256B EEPROM

• Abundant GPIO

• 16ch 8bit ADC

• 6ch + 2ch FTM

• 2 x UART

• 2pins with true open drain

• 4.5V~5.5V / -40c ~ 85c

• Full-featured

• 20Mhz

• 4KB RAM; 256B EEPROM

• 3 x UART; 2 x SPI; IIC

• 6ch + 2ch + 2ch FTM; 2 x MTIM

• RTC; CRC

• 16ch 12bit ADC with 4 entry Buffer registers

• 1 ACMP

• 8pins with 20mA Sink

• 2pins with true open drain

• 2.7V~5.5V / -40c ~ 105c

• 16-TSI for touch-sensing on PT

PL

PT

Features on superset Typical Applications

Low-end

e-meter

Small

Appliances

Large

Appliances

Lighting

Control

Off-Line UPS Keypads

Power

Tools

Battery

Charger

Smart Circuit

Breaker

Class

Electric Motor

HVAC

PA

http://images.google.com/imgres?imgurl=http://www.homeauto.com/_SiteElements/images/ConnectivityPartners/Lutron_MaestroDimmer.jpg&imgrefurl=http://www.homeauto.com/Products/HAIConnectivityPartners/Lutron.asp?Sort=Company&Type=ALL&usg=__ZXfTsRpJ-AVdkb476VgcgpxKDqM=&h=376&w=248&sz=32&hl=en&start=7&tbnid=yCngzF7COTVOEM:&tbnh=122&tbnw=80&prev=/images?q=lutron+dimmer&gbv=2&ndsp=18&hl=en&safe=off

TM 4






64LQFP (0.5mm pitch); 64QFP (0.8mm

pitch);

44LQFP (0.8mm pitch); 32LQFP (0.8mm

pitch);

48LQFP (0.5mm pitch); 48QFN

GPIO Slew Rate as S08

Passive Filter on GPIO

Digital Filter for selectable pins

2.7V ~ 5.5V / -40~105°C operation

Peripheral Bus (20MHz)

Analog Interfaces 16ch 8bit-12bit ADC

with 8 FIFO

Serial Interfaces

3 x SCI (LIN capable)

I/O Ports Up to 57

GPIO mux’d

on all pins

Timers & Triggers

6ch + 2ch + 2ch

16-bit Flex Timer

2 x MTIM

Power Management

Power On

Reset

Low Voltage

Detector

Single 2.7-5.5V Power Supply

System

Flash

60/32KB

RAM

4KB

Bi-

directional

Reset Pin

Clock Management High Speed

Ext Osc (4-

20MHz)

Low Speed

Ext Osc

32.768KHz)

Internal

R/C OSC

(~32KHz)

FLL

Clock

Multiplier

DBG/

BDM

WDOG w/ ind clock

256B

EEPRO

M

CRC

1 x 16bit SPI

1 x IIC

16 pin KBI

16-bit Real Time Counter

1 x 8bit SPI

IRQ

2 pins True

Open-Drain

8 pins

20mA

sink/source

1 x ACMP

16-ch TSI

S08

10-20MHz

All Px Features

Available on:

PT/A

Only

TM 5






44LQFP, 32LQFP GPIO Slew Rate as S08



2.7V ~ 5.5V / -40~105°C operation

20TSSOP,

16TSSOP


Analog Interfaces Serial Interfaces


I/O Ports

Up to 37

GPIO

Timers & Triggers

6ch + 2ch

16-bit Flex Timer

1 x 8bit MTIM

Power Management

Power On

Reset

Low Voltage

Detector


System

S08

10-20MHz

Flash

16/8KB

RAM

2KB

Bi-

directional

Reset Pin

Clock Management

High Speed

Ext Osc (4-

20MHz)

Low Speed

Ext Osc

32.768KHz)

Internal

R/C OSC

(~32KHz)

FLL

Clock

Multiplier

DBG/

BDM

WDOG w/ ind clock

256B

EEPRO

M

CRC

1 x IIC

8 pin KBI

16-bit Real Time Counter

1 x 8bit SPI

IRQ

2 pins True

Open-Drain

4 pins 20mA

sink/source

1 x ACMP

16-ch TSI

12ch 8bit-12bit ADC

with 8 FIFO

All Px Features

Available on:

PT/A

Only

TM 6






GPIO Slew Rate as S08



2.7V ~ 5.5V / -40~105°C operation

20TSSOP

16TSSOP,

8 SOIC, 8DFN


Analog Interfaces Serial Interfaces


I/O Ports

Up to 18

GPIO

Timers & Triggers

2+2 ch

16-bit Flex Timer

Power Management

Power On

Reset

Low Voltage

Detector


System

S08

10-20MHz

Flash

4/2KB

RAM

512B

Bi-directional

Reset Pin

Clock Management High Speed

Ext Osc (4-

20MHz)

Low Speed

Ext Osc

32.768KHz)

Internal

R/C OSC

(~32KHz)

FLL

Clock

Multiplier

DBG/

BDM

WDOG w/ ind clock

128B

EEPRO

M

CRC

4 pin KBI

16bit Real Time Counter IRQ

2 pins 20mA

sink/source

1 x ACMP

8ch 8bit-12bit ADC

with 8 FIFO

All Px Features

Available on:

PA

Only

TM 7






• 7

Feature PT60/PA60 PT32/PA32 PT16/PA16 PT8/PA8 PA4 PA2

Flash 60KB 32KB 16KB 8KB 4KB 2KB

RAM 4KB 4KB 2KB 2KB 512B 512B

EEPROM 256B 256B 256B 256B 128B 128B

Max Speed 20MHz 20MHz 20MHz 20MHz 20MHz 10MHz

CRC Yes Yes Yes Yes Yes Yes

WDOG w/ ind

clk

Yes Yes Yes Yes Yes Yes

ADC /w 8 FIFO 16ch x 12bit 16ch x 12bit 12ch x 12bit 8ch x 12bit 8ch x 12bit 4ch x 12bit

Hardware Timer 6ch+2ch+2ch FTM 6ch+2ch+2ch FTM; 6ch+2ch FTM 6ch+2ch FTM 2ch+2ch FTM 2ch+2ch FTM

Software Timer 2 x 8bit MTIM 2 x 8bit MTIM 1 x 8bit MTIM 1 x 8bit MTIM - -

RTC 1x16bit 1x16bit 1x16bit 1x16bit 1x16bit 1x16bit

SPI 1x8bit, 1x16bit 1x8bit, 1x16bit 1x8bit 1x8bit - -

IIC 1 1 1 - - -

SCI 3 3 2 2 1 -

Comparator 1 1 1 1 1 1

Temperature

Range

-40c to 105c -40c to 105c -40c to 105c -40c to 105c -40c to 105c -40c to 105c

Operation

Voltage

2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v

GPIO Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

TSI (S08PT

only)

16ch 16ch 12ch 8ch - -

Package 64/48/44/32LQFP;

64QFP

48QFN

64/48/44/32LQFP

64QFP

48QFN

44/32LQFP

20/16 TSSOP

44/32LQFP

20/16 TSSOP

20/16 TSSOP

8SOIC, 8DFN

8 SOIC

8DFN

TM 8






• 8

Feature PL60 PL32 PL16 PL8 PL4 PL2

Flash 60KB 32KB 16KB 8KB 4KB 2KB

RAM 4KB 4KB 2KB 2KB 512B 512B

EEPROM 256B 256B 256B 256B 128B 128B

Max Speed 10MHz 10MHz 10MHz 10MHz 10MHz 10MHz

CRC - - - - - -

WDOG w/ ind clk Yes Yes Yes Yes Yes Yes

ADC /w 8 FIFO 12ch x 8bit 12ch x 8bit 8ch x 8bit 8ch x 8bit 4ch x 8bit 4ch x 8bit

Hardware Timer 6ch+2ch+2ch TPM 6ch+2ch+2ch TPM; 6ch+2ch TPM 6ch+2ch TPM 2ch TPM 2ch TPM

Software Timer 2 x 8bit MTIM 2 x 8bit MTIM 1 x 8bit MTIM 1 x 8bit MTIM - -

RTC 1x16bit 1x16bit 1x16bit 1x16bit 1x16bit 1x16bit

SPI - - - - - -

IIC - - - - - -

SCI 2 2 1 1 1 -

Comparator - - - - - -

Temperature Range -40c to 85c -40c to 85c -40c to 85c -40c to 85c -40c to 85c -40c to 85c

Operation Voltage 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v

GPIO Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Passive Filter;

Digital Filter

Package 64/48/44/32LQFP;

64QFP

48QFN

64/48/44/32LQFP

64QFP

48QFN

44/32LQFP

20/16 TSSOP

44/32LQFP

20/16 TSSOP

20/16 TSSOP

8SOIC, 8DFN

8 SOIC

8DFN

TM 9






8 pin

SOIC

DFN

16 pin

TSSOP

32 pin

LQFP

44 pin

LQFP

48 pin

LQFP

QFN

64 pin

LQFP

QFP

20 pin

TSSOP

Pin

Compatible

Ap

plic

atio

n P

erf

orm

an

ce

/ In

teg

ratio

n

S08PT60

S08PA60

S08PL60

S08PT32

S08PA32

S08PL32

S08PT60

S08PA60

S08PL60

S08PT32

S08PA32

S08PL32

S08PT60

S08PA60

S08PL60

S08PT32

S08PA32

S08PL32

S08PT60

S08PA60

S08PL60

S08PT32

S08PA32

S08PL32

S08PT16

S08PA16

S08PL16

S08PT16

S08PA16

S08PL16

S08PT16

S08PA16

S08PL16

S08PT8

S08PA8

S08PL8

S08PT8

S08PA8

S08PL8

S08PT8

S08PA8

S08PL8

S08PA4

S08PL4

S08PA4

S08PL4

S08PA4

S08PL4

S08PA2

S08PL2

Full Featured

with TSI

Full Featured

without TSI

Feature-Lite

S08PT16

S08PA16

S08PL16

S08PT8

S08PA8

S08PL8

TM 10





other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. 10

Ap

plic

atio

n P

erf

orm

an

ce

/ In

teg

ratio

n

RS08KA8 RS08 Core; No Interrupt

1KB to 8KB; Ultra Low Cost

2010 2011 Available Now

S08SV/FL16 S08 Core; 8KB to 16KB

IPC; 30GPIO

RS08KB12 RS08 Core (enhanced)

2KB to 12KB

S08QD4 S08 Core; 2KB to 4KB

S08SE8 S08 Core; 4KB to 8KB;

10ch ADC; Ganged Output

S08SH8 S08 Core; 4KB to 8KB;

ACMP; SCI; SPI; IIC

S08AC16 S08 Core; 8KB to 16KB;

3TPM; 2SCI; 2SPI; IIC

S08SH32 S08 Core; 16KB to 32KB;

16pin to 28pin


32pin to 64pin

S08Px60/32 60KB to 32KB; 4K RAM; 256B

EEPROM; 3UART; 2SPI; IIC

16ch 12bit ADC with 4 Buffer;

3 FTM; RTC; 64pin to 32pin

S08Px16/8 16KB to 8KB; 2K RAM; 256B

EEPROM; UART; SPI

FTM; 32pin to 16pin

S08Px 4/2 4KB to 2KB; 256B EEPROM

20pin to 8pin

Ease of Use

Lower Cost

Robustness & Reliability

S08MP16 S08 Core; 12KB to 16KB;

2FTM; PGA; HSCMP; DAC

New

Existing 0.25u

Next Node

Legend

Code & Pin

Compatibility

Code & Pin

Compatibility

S08L Core

2.7V~5.5V

S08 Core

2.7V~5.5V

RS08 Core

2.7V~5.5V


44pin to 80pin

2012

Entry Level 32bit

TM 11






• Memory Combination:

− Increased Flash/RAM ratio (4KB RAM in Px60): Easy for C-Coding

− On-chip EEPROM with 500K~1M write/erase cycle: Simplify the system design for data logging and recording

• Robust GPIO & High Drive Capability:

− Up to 58 GPIO with filtering in 64pin: simplify external circuit design

− Up to 8 pins with 20mA sink drive capability: save external components for high current drive like TRIAC and LED

− 2 pins with True Open-Drain: provide design flexibility for different voltage level

• 16ch 12bit SAR ADC:

− Linear successive approximation algorithm with up to 12-bit resolution

− Up to 16-ch single-ended external analog inputs

− 12-bit, 10-bit, and 8-bit modes, 8-deep result FIFO

− Single or continuous conversion (automatic return to idle after single conversion)

• 16ch Touch-Sensing Interface on PT

− Dedicated hardware module to sense touch-input, minimum software intervention

− Functional in all power modes - run, wait & low-power stop. Wake-up capable from stop

− Designed for harsh environment operation with high sensitivity

− Highly configurable through HW & SW

• Feature-Rich integration:

− 6ch + 2ch + 2ch Flex Timer; 2 x MTIM

− Real Time Counter: helpful for any task scheduling functions

− 3 x SCI; 2 x SPI; IIC

− Enhanced Watch-dog and prog-CRC to meet IEC60730

− High accuracy internal clock to eliminate external clock source

AD Engine

ADR0

ADR1

ADR6

ADR7

Interrupt when four AD

conversion results got

…

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,

ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,

Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of

Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,

CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,

Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and

Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service

names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.

.

Application Examples

TM 13






MC9S08PA60

2 × SCI

S08L CPU

1 × IIC

ADC

MTIM

FLASH

RAM

EEPROM

FTM

EEPROM

IIC

RS232

SCI

LED

GPIO

TEMP

SENSOR

ADC

FTM

SWITCH

& KEY

FAN

CONTROL

Relay

BUZZER

FTM

GPIO for LED lighting

Multi AD channels

monitoring analog

signal

RS2323 communications

IIC for accessing external l

IIC components

Rich GPIO for all kinds

of control

IR

RECEIVE

R

FTM

GPIO /

TSI

GPIO

FTM generating PWM

for driving Buzzer and

fan control

FTM capture function

to implement IR

receiver

44-pin LQFP

compromises size, cost,

and features.

TM 14






Power /

Motor

control

board

SCI

LED

GPIO

TEMP

SENSOR

ADC

FTM

UI Touch

panel

FAN

CONTROL

Relay

BUZZER

FTM

GPIO for LED digit display

Multi AD channels

monitoring analog

signal

Serial communications

Rich GPIO for all kinds

of control

TSI GPIO

FTM generating PWM

for driving Buzzer and

fan control

44-pin LQFP


and features.

MC9S08PT60

2 × SCI S08L CPU

1 × IIC

ADC

MTIM

FLASH

RAM

EEPROM FTM

TSI

TM 15






MC9S08PL60

3 × SCI

S08L CPU

1 × SPI

1 × IIC

ADC

Meas.

Power

Supply

FTM/MTIM

FLASH

RAM

EEPROM

SPI

FTM

GPIO

VDD

VSS

ADC

PLC

RS485

5V 12V

SCI

SCI

5V

IR

TPM/SCI

Switches

GPIO

Relay

GPIO

LED

GPIO

ESAM FTM

Smart

Card FTM

Battery ADC

RTC EEPROM

LCM

IIC

FTM channel emulates

ISO-7816

64-pin LQFP


and features.

S08L CPU provides

lower power

consumption

38-kHz Inferred

Communication

Emulation Rich GPIOs for kinds

of control and monitor

Multi SCIs provides

more flexible design of

RS232, RS485, and PLC

Multi AD channels

support analog signal

monitor

IIC provides

communications with

on-board components

SPI provides

communications with on-

board serial peripherals

TM 16






1 × SCI

S08L CPU

FTM

MTIM

FLASH

RAM

MC9S08PL16

BUZZER FTM

ZERO

CROSS FTM

ADC VOLTAGE

MONITOR

ADC

SCI

GPIO

RS232

SWITC

HES GPIO

High-performance S08L

providing minimized run

current

FTM PWM output

driving Buzzer

FTM Channel Capture

for Zero Cross Detect

INVERTE

R

FTM

RS232 interface for host

communication

ADC Sampling for

power meter

Kinds of switching Square Wave

Generation LCM

IIC/GPIO emulation for

human interface

IIC/GPIO

IIC

32-pin LQFP


and features.

TM 17






H-Bridge driver

MC9S08PA8

Host

M

Hall Sensor

ACMP

S08L CPU

FTM 8KB FLASH

256B RAM

Regulator

2-CH FTM

12-bit ADC

Power VDD

18V ~ 24V

Power package

providing excellent

power dissipation

High-performance S08L

providing minimized run

current

Flexible external

interface providing

communication from

host

On-chip FLASH

providing software

flexibility for fast

development and

manufacture

Rich on-chip digital and

analog module providing high-

performance control with least

external components

PWM control

Analog control

PMC

16-pin TSSOP


and features.

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t

he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony

are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,

ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ

Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property

of their respective owners. © 2011 Freescale Semiconductor, Inc.

Confidential and Proprietary

Architecture

TM 19






• 19

XOSC

• automotive proven mature.18um process for super low power and high relibility

• V6 S08 Core with reduced power consumption up to 59% against old S08 core

• stop3 mode <= 3uA

• 20 MHz system/bus clock @2.7V to 5.5V across temperature range of -40 C to +105 C

• Memory

− Up to 60KB FLASH，256B EEPROM

− Up to 4KB RAM

• Serial Ports: 3 SCIs, 2 SPIs (8-bit SPI, 16-bit SPI w/ 64-bit FIFO ) and IIC

• 3 8-bit Modulo timers, 1 Real Time Counter w/ independent clock source options

• 3 FlexTimers: 2 TPM only, 1 enhanced

• Watchdog , 16-bit/32-bit CRC compatible with IEC60730 safety standard

• 16-ch ADC with selectable resolution: 12-bit/10-bit/8-bit

• 16-ch Touch Sensor Input capable of wakeup MCU from stop3 mode

• Analog Comparator with configurable hysteresis and 6b DAC w/ selectable vref

• Up to 57 GPIO with glitch filter – Versatile pin usage and enhance EMC performance

•DBG/BDC enables 3 h/w breakpoints

GPIO

16-ch

ADC

ACMP w/

6b DAC

S08L

Core

20 MHz

IIC

KBI

PMC

TSI

DBG

ICS

RTC

BDC

2x MTIM

3x FTM

3x SCI

8-bit SPI

16-bit SPI

CRC

Flash EEPROM RAM IRQ

IPC

Temp Sensor

►Packages: LQFP32/44/48/64, QFP64,QFN-48

New Peripherals

TM 20






• Eliminated 2x clock domain so system and bus clock frequency are

same

• Added CALL and RTC to support extended memory space >64KB

• Support MMU

TM 21






• 5V pad and internal layout are optimized for transient protection

• Adjacent power and ground

• 56 Bi-directional GPIOs

− PTA/PTB/PTC/PTD/PTE/PTF7-0 (except PTA4) , PTG3-0,PTH7-6/2-0

• 1 Output only: PTA4

• Pullups only available for input pins

• 2 True open drain pins: PTA3/PTA2

• 8 configurable high current drive pins (up to 20mA):

− PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0 and PTH1

• Normal single drive current up to 5mA, total < 100mA

• Pin remaps for SCI0, SPI0, IIC, FTM2

TM 22






TM 23






• NVM technology similar to S12

• Supports simultaneous flash and EEPROM operations

• EEPROM with Error Correction Codes to resolve single-bit fault and detect double-bit faults

• Flash memory has these features:

− Automated program and erase algorithm with verify

− Fast sector erase (sector size = 512B) and longword (32-bit) program operation

− Ability to read flash memory while programming a byte in EEPROM memory

− Flexible protection scheme to prevent accidental program or erase of flash memory

− Ability to set flash read margin levels

TM 24






• EEPROM memory has these features:

− Single-bit fault correction and double-bit fault detection within a word

during read operations

− Automated program and erase algorithm with verification and generation

of ECC parity bits

− Fast sector erase (sector size = 2B) and byte program operation

− Protection scheme to prevent accidental program or erase of EEPROM

memory

− Ability to program up to four bytes in a burst sequence

− Ability to set EEPROM read margin levels

TM 25






Features S08AC S08FL S08PT Unit Flash security √ √ √

Flash protection √ √ √

EEPROM X X 256 Bytes

Flash size 128K 16K 64K Bytes maximum

Flash sector/page size 512 512 512 Bytes

ECC parity check X X Single fault bit resolve &

Double fault bit detection

on EEPROM

Flash clock

frequency (FCLK)

150k to 200K 150k to 200K 0.8M to 1M Hz

Flash program bytes 1 1 8 Bytes maximum

EEPROM

program bytes

X X 4 Bytes maximum

Access time/byte read 1 1

1 Bus cycles

Program time 9 (byte program) 4 (burst program)

9 (byte program) 4 (burst program)

~68 (2 words)

~122 (4 words)

FCLK cycles

Page Erase time 4000 4000 ~20015 FCLK cycles

Mass erase time 20,000 20000 ~100066 FCLK cycles

TM 26






64 KB of flash memory composed of one 64 KB flash block divided into 128 sectors of 512

bytes

256 bytes of EEPROM memory composed of one 256 byte EEPROM block divided

into 128 sectors of 2 bytes (Single bit fault correction and double bit fault correction)

TM 27






• FLASH Program/erase endurance:

− S08PT60: typical 100 k cycles

− Old S08: typical 100 k cycles

• EEPROM Program/erase endurance:

− S08PT60: typical 500K cycles

− Old S08: typical 100K cycles

TM 28






• Simplified version of watchdog on Kinetis

• Compatible with IEC60730 safety standard

• Configurable independent clock source input from bus clock

− — Internal 32 kHz RC oscillator

− — Internal 1 kHz RC oscillator

− — External clock source

• Programmable time-out period with 16-bit modulo value and

optional fixed 256 clock prescaler

• Robust write sequence for counter refresh

− — Refresh sequence of writing 0xA602 and then 0xB480 within 16 bus

clock cycles

TM 29






• Windowed refresh option

− — Programmable 16-bit window value

− — Provides robust check that program flow is faster than expected

− — Refresh outside window leads to reset

• Programmable timeout post-processing

− — Interrupt request to CPU with interrupt vector allowing ISR

− — Force a reset after 128 bus clock cycles

• Robust write sequence for unlocking write-once control/configuration bits

− — Unlock sequence of writing 0xC520 and then 0xD928 within 16 bus clock cycles for allowing updates to write-once control/configuration bits

− — User need to update these after unlocking, within 128 bus clock cycles. Failure to update resets the system

TM 30






• Configuration bits and registers are write-once-after-reset, to

ensure watchdog configuration cannot be mistakenly altered

• Flexible test mode enabling fast testing watchdog in the safety

environment (either high 8-bit counter or lower 8-bit counter for

comparison)

• Backup reset to prevent hardware lockup condition driven by bus

clock

TM 31






TM 32






• Reused from Kinetis K40/60 with minor rework

• 16/32-bit CRC code for error detection

• Programmable 16/32-bit initial seed value

• Programmable 16/32-bit polynomial

• Reverse input and output data by bit in a byte (no byte reverse)

• Final complement output of result

• Not functional in stop3 mode

•

NOTE:

Input data can only be written to 8-bit CRC_D3

TM 33






• Reused from MCF51JU128

• FTM0 and FTM1 are TPM only

• FTM2 enhanced timer, targeting motor control and power conversion applications:

− Combined mode to generate asymmetric PWM

− Complementary mode

− Deadtime insertion hardware

− PWM synchronization control

− Fault control inputs

− Output masking

− Polarity control

− Enhanced triggering functionality (channel match trigger and init trigger)

− Dual edge capture

TM 34






• Combined mode

Channel <n> controls PWM first edge, while channel <n+1> controls PWM second edge

• Complementary mode

TM 35






• Deadtime insertion

Available only in complementary mode

Deadtime insertion on either rising edge or falling edge

Counter clock derived from 1/4/16 system clocks

Count from 1 to 63

Dead time from 1 to 1008 system clocks ( 0.05 to 50.4us @20MHz )

TM 36






• PWM Synchronization

Provide opportunity to

• force FTM counter to its initial value (CNTINH:L) and the channel outputs are forced to

initial value (known as FTM counter synchronization) and

• update 3 kinds of registers (MOD, CnV, OUTMASK[CHnOM]) with their write buffers

and sync two or more FTMs

Trigger event: hardware trigger or software trigger

Update point: boundary cycle

• Minimum/low boundary (FTM counter == CNTINH:L )

• Maximum/upper boundary (FTM counter == MOD) ( NOT available )

TM 37






• Fault Control

− Channel outputs are forced to a safe value when a fault is detected

− 4 fault control input pins with fault filters

Any pulse that is shorter than the minimum value selected by FFVAL[3:0] bits

(×system clock) is regarded as a glitch

− can be disabled for all channels

− can be enabled for even channels only with Manual fault clearing

− can be enabled for all channels with Manual fault clearing ( output re-

enabled only when Fault flag cleared by s/w)

− can be enabled for all channels with Automatic fault clearing (output re-

enabled when fault input returns to 0)

TM 38






3 LIN/SCI

2 SPI

16pin KBI

1 IIC

ATD 16ch 12b

FlexTimer

6+2+2ch 16b

32/48/64LQFP

48QFN

MTIM 2ch 8b

RTC 1ch 8b

256B EEPROM

DBG

60KB Flash

4KB RAM

S08 CPU 20MHz Bus

S08RN60 Block Diagram

WD+RTC Analog Comp.

Prog. CRC

DAC

Up to 16ch TSI

• Capacitive Touch Sense Module

− Capacitive touch sensing detection with high sensitivity and

enhanced robustness.

− Up to 16 electrodes, using a single pin per electrode, with

individual result registers

− No need for external components

− Capacitive touch sensing detection across all low power

modes – with capability to wake MCU from stop-modes

− Automatic detection of Electrode Capacitance Change with

programmable upper and lower threshold

− Automatic periodic scan with configurable duty cycle

− Low Power Mode current consumption adder of 1-3uA

− Capacitance measurement resolution down to 0.02pf

− Configurable software or hardware scan trigger

− Compensate temperature and supply voltage variations

− Fully support Freescale touch sensing software library of

button, keyboards, sliders, and rotaries

MCU 1 2 3 4 5 6 7 8 9

* 0 #

TM 39






Hardware Touch-Sensing Interface (TSI) Low Power Mode Operation

• TSI can be enabled in all MCU low power modes with minimum current consumption (adder of 1-3uA).

• Touch Sensing Input Module has programmable high and low-threshold.

• The TSI has a internal periodic scan module that is active in all MCU power mode. It has separate scan

intervals for Low Power and Run mode. So in low power modes the applications can set longer scan

intervals for minimizing power consumption. In Run mode the application can set shorter scan intervals for

faster touch response time.

• The TSI operating in MCU low power mode ensure minimal power consumption for battery operated

devices. Enabling the MCU to wake up upon a touch event.

• When Touch occurs the instantaneous electrode capacitance is detected to be out of the threshold defined

range causing an TSI interrupt to be issue waking up the CPU.

TM 40






CPU Loading Analysis Comparing with Kinetis DMA-ed Version

TSI on S08Px needs MCU to read back

touch-sensing data via interrupt service

routine or polling, while on Kinetis it’s

done through DMA

This will consume a small amount of CPU

bandwidth due to ISR and SW interactions

In most of user cases (Fbus > 5MHz), this

extra CPU loading is negligible.

Input 16 channel

Scan interval 10 ms

Instruction cycle 180 per channel

Fbus (MHz) CPU loading

20 1.44%

10 2.88% 5 5.76%

1 28.80%

TM 41






Touch Sensing Library Integration

System

Configuration

and

Management

System Setup

Decoders

Key Detector

Touch Sensing Module (TSI)

Application

Keypad Rotary Slider TSS Library

TSI Module

Freescale provides the complete Touch Solution by seamless integration of the

Touch Sensing Module (TSI) in the Freescale Touch Sensing Library.

While the TSI Module provides robust, precise electrode capacitance

measurement, the library allows easy implementation of sliders, rotaries and

keypads. Keeps flexibility to adjust very specific application requirements.

TM 42






Hardware Touch-Sensing Interface (TSI)

• C: Capacity of Electrode (changing it’s value upon touch) as a result Tcharge and Tdischarge will change

• V: configurable value (0,388V .. 1,440V); use higher values for higher immunity; lower values for faster response

• Icharge = Idischarge = I : configurable current source (0,5uA .. 64uA); low values give lower power consumption; higher values

give faster charging of the Capacitor

• A pair of configurable constant current sources are used to charge and discharge each electrode to a configurable volt change

( V).

• The TSI module measures the electrode pin capacitance by detecting both durations of charging and discharging the

electrodes (Tcharge & Tdischarge).

• The charge and discharge durations are measured by a 16-bit counter referred by reference oscillator (up to 10 MHz) or

external reference clock (up to 20 MHz).

• The current sources and 16-bit counter provides a wide range of combinations allowing application-specific optimisation

• The following figure shows the basic workflow of TSI module.

TM 43






• SAR ADC configurable for 12-bit, 10-bit and 8-bit

• Basic functionality similar to S08AC/FL families：

• Single/continuous conversion, Configurable sample time and conversion speed/power, Operation in wait or stop3 modes for lower noise operation, Asynchronous clock source for lower noise operation

• 16 external channels, 5 internal channels (bandgap,temp sensor,vref,vss)

• Added automatic compare with interrupt for less-than, or greater-than or equal-to programmable value

• Added channel FIFO and result FIFO, each up to 8 entries to reduce CPU loading in ADC interrupt service routines

− FIFO can be disabled and FIFO full condition/depth can be configurable from 2 to 8-level

− When channel FIFO is full:

• For software trigger mode, the first conversion is started immediately and the next conversion is started when the previous conversion completes, loops until the last channels in FIFO depth are converted, then COCO bit is set

• For hardware trigger mode, the first conversion is started upon 1st hardware trigger and the next conversion is started when both the previous conversion completes and a new hardware trigger comes, loops until the last channels in FIFO depth are converted, then COCO bit is set

TM 44






• FIFO scan mode to simplify dummy work of input channel FIFO

− Always use the first channel in FIFO as dummy channel

− The ADC conversion is started as soon as the first channel is written, and

the next conversion is started when the previous is completed, until the

result FIFO is full. Then the COCO bit is set.

− In continuous mode (ADCO = 1), the ADC will start the next conversion

with the same channel when COCO is set.

1

2

8

Write ADC_SC1_ADCH N

1

Input Channel FIFO Channel Conversion

FIFO Full

2

N

H/W trigger Write ADC_SC1_ADCH

Write ADC_SC1_ADCH H/W trigger

H/W trigger

COCO = 1

TM 45






• ADC H/W trigger

− MTIM0 overflow/RTC overflow/FTM2 match trigger with 8-bit

programmable delay/FT2 init trigger with 8-bit programmable delay

RTC

MTIM0

ovf

ovf

FTM2

Init trig

match trig

DELAY

(8-bit)

00

01

11

10

1/2N Bus clock

ADC H/W trigger

ovf

ADHWT

TM 46






• On-chip 6-bit resolution DAC with selectable reference voltage from

VDD or internal bandgap

• Configurable hysteresis: 20mV/30mV

• Selectable interrupt on rising edge, falling edge, or both rising or

falling edges of comparator output

• Selectable inversion on comparator output

• Up to four selectable comparator inputs:

− ACMP0/ACMP1/DAC output

− ACMP2 reserved

• Output can be placed on external pin ACMPO

• Operational in stop3 mode and can be used to wakeup MCU

• ACMP output interconnectable to FTM1 input capture channel0

• ACMP output for SCI0 RxD filter

TM 47






• Reused from MCF51AG128

• 16-bit up-counter,16-bit modulo match limit

• Software controllable periodic interrupt on match

• Three software selectable clock sources

− XOSC (32.678KHz nominal)

− LPO (~1 kHz)

− Bus clock

• Prescaler can be binary-based or decimal-based

− 1,2,4,8,16,32,64,128,256,512,1024,2048

− 100,1000

• Can work in stop3 if enabled

• Serve as cyclic wakeup from low power mode

• RTC overflow signal can trigger to ADC and TSI

• RTC overflow can toggle output on pin RTCO

TM 48






• 48

TM 49






• Reused from AG128

• Compatible with The I2C-Bus Specification, standard mode 100Kbps

• Multimaster operation

• Software programmable for one of 64 different serial clock frequencies

• Software-selectable acknowledge bit

• Interrupt-driven byte-by-byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to

slave

• Calling address identification interrupt

• START and STOP signal generation and detection

• Repeated START signal generation and detection

• Acknowledge bit generation and detection

TM 50






• Bus busy detection

• General call recognition

• 10-bit address extension

• Support for System Management Bus (SMBus) Specification, version 2

• Programmable glitch input filter

• Low power mode wakeup on slave address match

• Range slave address support

TM 51






• Reused from EM256 with minor work:

2 STOP bits format added

• Traditional features

− Break detect supporting LIN

− Full-duplex, standard non-return-to-zero (NRZ) format

− Double-buffered transmitter and receiver with separate enables

− Programmable baud rates (13-bit modulo divider)

− Interrupt-driven or polled operation:

− Transmit data register empty and transmission complete

− Receive data register full

− Receive overrun, parity error, framing error, and noise error

TM 52






− Idle receiver detect

− Active edge on receive pin

− Hardware parity generation and checking

− Programmable 8-bit or 9-bit character length

− Programmable 1-bit or 2-bit stop bits

− Receiver wakeup by idle-line or address-mark

− Optional 13-bit break character generation / 11-bit break character

detection

− Selectable transmitter output polarity

TM 53






• New features:

− 64-bit FIFO mode for high speed/large amounts of data transfers

− Receive data buffer hardware match feature

• Traditional features

− Master mode or slave mode operation

− Full-duplex or single-wire bidirectional mode

− Programmable transmit bit rate

− Double-buffered transmit and receive data register

− Serial clock phase and polarity options

− Slave select output

− Mode fault error flag with CPU interrupt capability

− Control of SPI operation during wait mode

− Selectable MSB-first or LSB-first shifting

− Programmable 8- or 16-bit data transmission length

TM 54






• TWR-S08PT60 (Expected Q4 2011)

− MCU card only

− Includes Quick Start Guide and labs

− Integrated USB open-source debugger

− Demo board can be powered by the USB circuit

− Integrated touch sensing reference design

• TWR-S08PT60-KIT (Expected Q4 2011)

− Elevators, supporting peripheral module, MC9S08PT60 MCU card

− Tower Kit for S08RN60 (automotive) to follow early 2012

• CodeWarrior Development Studio for Microcontrollers v10.x − Complimentary Special Edition with compiler sizes up to 60K

− Single tool suite that supports software development for future migration

opportunities for both 8-bit or 32-bit and includes Processor Expert Software, a rapid

application development tool

• IAR Embedded Workbench support for S08

Online training, webcast, technical documentation and application notes available at

www.freescale.com/S08P / www.freescale.com/S08R

TM 55






TM 56






56

TM 57






TM 58






Freescale Product Longevity Program

► The embedded market needs long-term product support

► Freescale has a longstanding track record of providing long-term production support for our products

► Freescale offers a formal product longevity program for the market segments we serve

• For the automotive and medical segments, Freescale will make a broad range of program devices available for a minimum of 15 years

• For all other market segments in which Freescale participates, Freescale will make a broad range of devices available for a minimum of 10 years

• Life cycles begin at the time of launch

► A list of participating Freescale products is available at: www.freescale.com/productlongevity

http://www.freescale.com/productlongevity

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