DESIGN OF VARIABLE RESOLUTION FLASH ADC USING TIQ FOR PORTABLE DEVICE APPLICATIONS.

BY S.N.MISHRA (NIT SILCHAR)Scholar No.11-24-108, ECE Dept.Under the guidance of DR. J.MEHEDI, Asst. prof. W.ARIF

OUTLINEINTRODUCTION & MOTIVATIONDESIGN OF FLASH ADCTIQ PRINCIPLETIQ COMPARATORVARIABLE RESOLUTION DESIGNFUNCTIONAL SIMULATIONFUTURE WORK

INTRODUCTIONWhat is ADCWhy ADC is needed ?Application of ADCTypes of ADCFlash ADC

PROS & CONS FLASH ADCPROSVery Fast (Fastest) Very simple operational theory Speed is only limited by gate and

comparator propagation delayCONS Expensive Prone to produce glitches in the output Each additional bit of resolution

requires twice the comparators.

ADC COMPARISON

FLASH ADC STRUCTURE

DRAWBACKS IN GENERAL FLASH ADCSTRUCTURE

The analog comparators are designed with high gain. Hence the circuit complexity becomes high.

Large transistor area for higher accuracy.

DC bias requirement.High power consumption.Resistor or capacitor array

requirement .

TIQ PRINCIPLE

TIQ COMPARATOR

where Vtn and Vtp are the threshold voltages for NMOS and PMOS devices, respectively and Kn = (W/L)n . Un Cox, Kp = (W/L)p . Up Cox.

Since the transistor channel length, L, is more effective than the channel width, W, in controlling the performance , L is kept constant and only W is changed during the design process.we know that Vth is shifted depending the transistor width ratio (Wp/Wn). That is, increasing Wp makes Vm larger, and increasing Wn results in Vm being smaller on the VTC. This changing of the widths of the PMOS and NMOS devices with a fixed transistor length is the idea of the TIQ comparator

ADVANTAGE & DISADVANTAGE OF TIQ COMPARATOR

Therefore no static power consumption is required for quantizing the analog input signal, making the idea very attractive for battery-powered applications.

Speed is very high Circuit complexity less Area is less External bias not required Resistor ladder for Vref not required

The main limitation of the TIQ based ADC approach is that it is process parameter dependent.

In TIQ based Inverters both PMOS and NMOS are on simultaneously, which will give more short circuit current

It requires 2n-1 number of different area-sized quantize designs. The matching properties of the wafer are critical Single ended structure

TIQ ADC STRUCTURE

Design a minimum size inverter and verify the threshold voltage value for midpoint quantizer. Note that the channel length is kept at the minimum value during the entire design process.

Estimate a safe Analog range = Vdd − (VTN + |VTP|), where VTN and VTP are the threshold voltages for large NMOS and PMOS devices, namely the VTHO value from the model parameter data set.

Calculate the LSB value as follows: LSB = Analog range/2n

Calculate the ideal threshold points for each quantizer.

By increasing Wp we can get the higher Vth while Wn , L constant and Vth can be decreased in reverse way.

ENCODER

MUX ENCODER

VARIABLE RESOLUTION Variable resolution ADC operate at high speeds

and will consume less power when it operates at a lower resolution. This feature is highly desirable in many wireless mobile applications.

For example, the strength of a radio frequency (RF) signal varies greatly depending on geographic location. Optimally, the ADC resolution can be reduced upon the reception of strong signal, or the resolution can be increased upon the reception of weak signal.

The substantial reduction of power consumption at lower resolution will prolong the battery-powered operation.

2-BIT MUX ENCODER

3-BIT MUX ENCODER

CONTROL TIQ COMPARATOR

VARIABLE ADC

SCHEMATIC OF 4-BIT ADC

DC RESPONSE TIQ COMPARATOR

DC RESPONSE OF GAIN BOOSTER

TRANSIENT RESPONSE OF 4-BIT ADC

SCHEMATIC OF 3-BIT ADC

TRANSIENT RESPONSE OF 3-BIT ADC

FUTURE WORKDesign of 5-bit,6-bit ADCDesign of control logicIntegrate entire structure DNL, INL, Power measurementModify to improve PSRRLay out of circuit

REFERENCES

A.Tangel, K Choi, “'The CMOS Inverter as a Comparator in ADC Designs”, spinger Analog Integrated Circuits and Signal Processing, Vol.39, pp.147-155,2004

J. Yoo, “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications”, Ph.D Thesis, The Pennsylvania State University, May 2003.

Yoo, K.Choi and A.Tangel. “A 1-GSPS CMOS Flash Analog-to-Digital Converter for System-on-chip Applications”, IEEE CS Annual Workshop on VLSI, pp. 135-139, 2001.

A Mahesh Kumar, Sreehari Veeramachaneni, Venkat Tummala, M.B.Srinivas, “Design of a Low Power Variable-Resolution Flash ADC", In the Proceedings of the 22nd IEEE/ACM International Conference on VLSI Design and Embedded Systems (VLSI DESIGN - 2009),New Delhi , India, 5th -9th January 2009

Luca Corradin, Enrico Oriettii, Paolo Mattavelli and Stefano Saggini,” Digital Hysteretic voltage-mode conyrol for DC-DC converters based on asynchronous sampling”,IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 1, JANUARY 2009.

Darryl J. Tschirhart,Praveen k jain,”Performance of ADC for use in mixed-signal control of synchronous rectifiers in current type resonant converters”, IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.19,NO.2,JANUARY 2007.

Chetan vudadha,Goutham makkena, Sreehari Veeramachaneni, Venkat Tummala, M.B.Srinivas,”Low –power selfreconfigurable multiplexer based decoder for adaptive resolution flash ADC”, 25th IEEE International Conference on VLSI Design ,2012

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