2013 International Conference on Computer Communication and Informatics (ICCCI -2013), Jan. 09 – 11, 2013, Coimbatore, INDIA

A 1-V 1-GS/s 6-bit Low-Power Flash ADC in

90-nm CMOS with 15.75 mW Power Consumption

Kirankumar Lad1 and M S Bhat

2

Department of Electronics and Communication

National Institute Of Technology Karnataka

Surathkal-575025, India

Email: kirankumarlad@gmail.com1, msbhat@ieee.org

2

Abstract—A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm

CMOS technology is presented. Proposed Flash ADC consists of

reference generator, comparator array, 1-out-of N code

generator, Fat tree encoder and output D-latches. This Flash

ADC achieves 5.76 ENOB at Nyquist input frequency without

calibration. The measured peak INL and DNL are 0.08LSB and

0.1LSB, respectively. The proposed ADC consumes 15.75 mW

from 1V supply and yielding an energy efficiency of 0.291

pJ/conv while operating at 1 GS/s.

Keywords- Flash ADC, Preamplifier based latch comparator, Low

power, Fat tree encoder

I. INTRODUCTION

Analog to digital converters are an essential part of devices

that interact with real world. Flash ADC is one of the most

preferred architectures for high speed analog to digital data

conversion applications. Flash ADC is also used as a building

block for many architectures like folding and interpolating,

pipelined, sub-ranging ADCs etc. Although the exponential

increase in area and power consumption with resolution limits

its use in hand held applications, Flash ADCs are used in

applications requiring high speed of operation at a relatively

low resolution (up to 7 bits).

In recently published research papers, inverter based

comparators are frequently used in the design of low power

flash ADCs. In [1], a 6-bit low power flash ADC using

inverter based comparators is presented which consumes less

than 300μW of power at a sampling rate of 50MS/s. In [2], a

differential clocked comparator architecture is used as a

building block for high speed flash ADC applications.

Although, the sampling speed in this design is reported to be

1GS/s, the comparator block alone consumes 2mW of power.

The present work intends to fill the gap by proposing a 6 bit

flash ADC for high speed applications (up to 5 GS/s) and

consuming slightly higher power compared to the inverter

based ADC. The proposed ADC employs a modified version

of the comparator block presented in [2] to achieve low power

and high speed of operation.

The rest of the paper is organized as follows. Section

II briefly describes the flash ADC architecture and design.

Simulation results are discussed in section III. Section IV

presents a comparison of this work with recently published

flash ADCs and section V concludes the paper.

II. FLASH ADC DESIGN

The proposed ADC block diagram is shown in Figure 1.

Individual blocks are briefly explained below

Figure 1. Flash ADC block diagram

A. Reference Voltage Generator

A resistor ladder comprising 2N

equal resistors is used to

generate 2N

equally spaced reference voltages for the

comparators. Total resistance Rtot and total input capacitance

of all comparators Cintot is calculated using equations 1 and 2

as shown below [3] :

(1)

where N is ADC resolution and fin is maximum input

frequency and,

(2)

where C is approximate input capacitance of each comparator.

In this work, the input dynamic range is fixed as 0.6 V peak-

to-peak and the reference voltage ranges from 0.2 V to 0.8 V

with a step size of 9.375 mV (LSB).

978-1-4673-2907-1/13/$31.00 ©2013 IEEE

Figure 2. Proposed Comparator

B. Voltage Comparator

The proposed voltage comparator circuit diagram is shown in

Fig. 2. This comparator consists of three stages: a preamplifier

stage, a latch and a post amplifier stage [4]. The detail

operation of each stage is described in following subsections:

1) Preamplifier : The stage-1 of proposed comparator

shown in Fig. 2 is working as a preamplifier. It consists of

nmos input differential pair (M1 and M2) and diode connected

pmos pair (M3 and M4). In order to overcome dynamic offset

in regenerative latch, this preamplifier is needed. In this Flash

ADC frontend sample and hold circuit is not used. Because of

this, each preamplifier in the proposed comparator has to

continuously track the input signal. The large difference in

delays across different preamplifiers result in error (or bubble)

code. Furthermore, due to different changing rate of input

signal that each preamplifier sees, its delay is amplitude

dependent. This input dependent delay gives rise to 3rd

harmonic distortion. In order to suppress this distortion, one

has to make the preamplifiers fast enough, or equivalently

they should have large bandwidth. The output of preamplifier

is given to the input of latch through transistor M5 and M6 as

shown in Fig.2.

2) Latch: The latch stage (stage-2 of proposed

comparator) consists of cross coupled pair of NMOS and

PMOS transistors that are connected to the ground through the

clock enable transistor M10. When CLK is low (and CLKB is

high), the latch is in its reset state and its output voltages are at

the midpoint of the rails. Regeneration of output in evaluation

phase is faster in this case because the latch output is at the

midpoint of VDD and GND. During the reset phase, the

preamplifier translates the voltage difference between the

inputs of the comparator into an unbalanced state in the latch

stage. Then, in the evaluation phase (when CLK goes high),

the latch stage is activated. Because of the positive feedback,

this unbalanced state is amplified towards the rail voltages.

Output of the latch stage is fed to the third stage of

comparator, which converts the differential output into a

single ended output.

3) Postamplifier: The postamplifier stage (stage-3 of the

comparator) consists of a self-biased single-ended differential

amplifier and two inverters. During the reset phase of latch,

output of the postamplifier goes low. In the evaluation phase,

it converts differential output of latch to single-ended output.

The inverter at the output of the self-biased differential

amplifier introduces additional gain and isolates any load

capacitance from self-biased differential amplifier. Output of

the postamplifier stage goes to 1-outof-N code generator.

4) 1- out of N code generator, Fat tree encoder and D-

latch: The output of the comparators form a thermometer

code. It is converted to 1-outof-N code using an array of NOT

and AND gates as shown in Fig. 1. This NOT-AND array is

realized using NOT and NOR gates. This 1-outof-N code is

fed to a fat tree encoder, which converts it into a binary code.

The fat tree encoder performs better than ROM encoder in

terms of speed and power in case of a 6-bit flash ADC and it

also consumes less silicon area [5]. The OR gates of fat tree

encoder are realized using NAND and NOR gates. The six

output binary bits from the fat tree encoder are latched using a

positive edge D-latch, which gives synchronized output and

acts as an output register.

III. SIMULATION RESULTS

The proposed ADC is implemented in a 90 nm CMOS

technology and simulated using Cadence Spectre simulator.

The supply voltage and reference voltage used are 1 V and 0.6

V, respectively. The sampling rate of this ADC is 1 GHz. The

DFT spectrum at input frequency of 496.09 MHz and

sampling frequency of 1 GHz is shown in Fig. 5 and at the

same input frequency, the SNDR and SFDR are found to be

36.45 dB and 45 dB respectively. The plot of input frequency

versus SNDR and SFDR at sampling frequency of 1 GHz is

shown in Fig. 6. In the full Nyquist input frequency range, this

ADC achieves an ENOB of more than 5.5 bits at 1 GS/s. This

ADC has an effective resolution bandwidth (ERBW) of 710

2013 International Conference on Computer Communication and Informatics (ICCCI -2013), Jan. 09 – 11, 2013, Coimbatore, INDIA

MHz. The plot of measured DNL and INL are shown in Fig. 3

and Fig. 4 respectively. The measured peak DNL and INL are

found to be 0.08LSB and 0.1LSB respectively. At 1 GS/s, the

total power consumed by this ADC is 15.75 mW from a 1 V

power supply. Figure of Merit (FoM) of this ADC is 291

fJ/conv. Where the FoM is defined as

( )( ⁄ ) (3)

The performance specification of this ADC are listed in Table-

I.

Figure 3. DNL plot of the ADC

Figure 4. INL plot of the ADC

TABLE I: Performance Summary of the ADC

Parameter Value

Technology 90 nm CMOS

Supply Voltage 1 V

Resolution 6 bit

Sampling Frequency 1 GS/s

Input Range 600 mV peak to peak

SNDR 36.45 dB @ 496 MHz, 37 dB @ 121 MHz

ENOB 5.76 @ 496 MHz, 5.82 @ 121 MHz

Maximum DNL, INL 0.08 LSB, 0.1 LSB

Total Power 15.75 mW

FoM 0.291 pJ/conv @ 496 MHz

Figure 5. 256 point FFT of 496 MHz reconstructed signal

Figure 6. SNDR and SFDR of the ADC for different input

frequencies

IV. COMPARISON WITH SOME RECENT FLASH ADCS

Comparison of this work with recently reported high

sampling speed ADCs is given in Table-II. From this table , it

can be observed that the present work has lowest power

among other ADCs except Komar’s work[1] which uses

inverter based comparators. The ADC works at a sampling

speed of 1 GS/s, a FoM of below 1 pJ/conv and has a good

ENOB compared to other ADCs operating at at Nyquist

frequency. Further, this ADC consumes lesser power, it can be

used in high speed low power ADC applications.

V. CONCLUSION

In this paper, the design and the simulation results of 1-V 1-

GS/s 6-bit low power Flash ADC are represented. This

architecture can be extended to high speed applications

because the comparator used in this ADC can work up to 5

GS/s. As the ADC has high input bandwidth, low power

consumption and high linearity, this ADC is most suitable for

high speed communication applications up to 1 GS/s.

TABLE II: Comparison with low voltage state of the art designs

Author/Year Core Architecture VDD

(V) N

(bit) Speed

(GS/s) Power

(mW) ENOB@Nyquist

(bit) Tech.

(nm) FoM

(pJ/conv)

DNL/INL

(LSB)

[6] – 2005 Flash 1.5 6 1.2 160 5.7 130 2.2 -

[7] - 2006 Flash 1.8 5 3.2 227 3.627@1G 90 - 0.93/0.89

[8] – 2006 Flash 1.8 6 1.056 98 5.0 180 - 0.47/0.56

[9] – 2008 Flash 1.2 6 2.5 30 4.0 90 3.1 0.48/0.54

[10] – 2008 Flash 1 8 1.25 207 6.9 90 1.4 1.3/1.1

[11] – 2008 Flash 1.2 6 1.2 40.5 5.2 90 0.9 0.9/0.8

[12] – 2008 Flash 1.8 6 1 550 5.1@7.1 MHz 180 - 1/1.1

[13] – 2009 Flash 1.2 6 1 112 5.1@100MHz 130 - 1.1/1.1

[14] – 2009 Two-Channel Two-Step 1.2 6 1 49 5.3 130 1.24 0.28/0.30

[15] – 2010 Flash 1 5 3 36 4.3 65 0.6 0.36/0.41

[16] – 2011 Flash 1.2 7 1.5 204 6.05 90 2.05 0.7/0.64

[1]-2012 Inverter Flash 0.5 6 0.05 0.3 4.88@5.1MHz 180 - 0.025/0.375

This Work Flash 1 6 1 15.75 5.76 90 0.291 0.08/0.1

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