mobile pentium 4 hyper threading 90nm process technology datasheet

8/3/2019 Mobile Pentium 4 Hyper Threading 90nm Process Technology Datasheet

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Mobile Intel Pentium 4Processor SupportingHyper-Threading Technology on90-nm Process TechnologyDatasheetJanuary 2005

Document Number: 302424-003


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i n t e l

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BYESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED ININTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMSANY EXPRESS OR IMPLIED WARRANTY. RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIESRELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHERINTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAININGAPPLICATIONS.Intel may make changes to specifications and product descriptions at any time, without notice.Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these forfuture definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.The Mobile Intel Pentium 4 processor may contain design defects or errors known as errata which may cause the product to deviate frompublished specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.1Hyper-Threading Technology requires a computer system with a Mobile Intel Pentium 4 processor, a chipset and BIOS that utilize this technology,and an operating system that includes optimizations for this technology. Performance will vary depending on the specific hardware and software youuse. See for information.Copies of documents which have an ordering number and are referenced inthis document, or other Intel l iterature, may be obtained by calling 1-800-548-4725 or by visiting Intel's website at Intel, Pentium, Intel NetBurst, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in theUnited States and other countries.'Other names and brands may be claimed as the property of others.Copyright 2005 Intel Corporation.

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intel~Contents

Introduction 71.1 Terminology 8

1.1.1 Processor Packaging Terminology 81.2 References 9

3

Electrical Specifications 112.1 Power and Ground Pins 112.2 Decoupling Guidelines 11

2.2.1 Vcc Decoupling 112.2.2 Front Side Bus GTL+ Decoupling ll2.2.3 Front Side Bus Clock (BCLK[l :0]) and Processor Clocking 11

2.3 VOltage Identification 122.3.1 Phase Lock Loop (PLL) Power and Filter 14

2.4 Reserved, Unused, and TESTHI Pins 152.5 Front Side Bus Signal Groups 152.6 Asynchronous GTL+ Signals 172.7 Test Access Port (TAP) Connection 172.8 Front Side Bus Frequency Select Signals (BSEL[l :0]) 182.9 Absolute Maximum and Minimum Ratings 182.10 Processor DC Specifications 19

2.10.1 Fixed Mobile Solution (FMS) 192.11 VCC Overshoot Specification 25

2.11.1 Die VOltage Validation 26Package Mechanical Specifications 273.1 Package Mechanical Specifications 27

3.1.1 Package Mechanical Drawing 283.1.2 Processor Component Keep-Out Zones 313.1.3 Package Loading Specifications 313.1.4 Package Handling Guidelines 313.1.5 Package Insertion Specifications 323.1.6 Processor Mass Specification 323.1.7 Processor Materials 323.1.8 Processor Markings 323.1.9 Processor Pin-Out Coordinates 33

Pin Listing and Signal Descriptions 354.1 Processor Pin Assignments 354.2 Alphabetical Signals Reference 50Thermal Specifications and Design Considerations 595.1 Processor Thermal Specifications 59

5.1.1 Thermal Specifications 595.1.2 Thermal Metrology 60

5.2 Processor Thermal Features 615.2.1 Intel Thermal Monitor 615.2.2 Thermal Monitor 2 61

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4

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i n t e l 5.2.3 On-Demand Mode 635.2.4 PROCHOT# Signal Pin 635.2.5 THERMTRIP# Signal Pin 645.2.6 Tcontrol and Fan Speed Reduction 645.2.7 Thermal Diode 64

6

7

Features 676.1 Power-On Configuration Options 676.2 Clock Control and Low Power States 67

6.2.1 Normal State-State 1 676.2.2 AutoHALT Power-Down State-State 2 686.2.3 Stop-Grant State-State 3 686.2.4 HALT/Grant Snoop State-State 4 696.2.5 Sleep State-State 5 696.2.6 Deep Sleep State-State 6 706.2.7 Deeper Sleep State-State 7 70

6.3 Enhanced Intel SpeedStep Technology 70Debug Tools Specifications 737.1 Logic Analyzer Interface (LAI) 73

7.1.1 Mechanical Considerations 737.1.2 Electrical Considerations 73



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intel~Figures

2-12-22-33-13-23-33-43-54-14-25-15-26-1

Tables1-12-12-22-32-42-52-62-72-82-9

2-102-112-122-132-142-152-162-173-13-23-34-14-24-35-15-25-36-1

Phase Lock Loop (PLL) Filter Requirements 14Vcc Static and Transient Tolerance1, 2, 3 22VCC Overshoot Example Waveform 26Processor Package Assembly Sketch 27Processor Package Drawing Sheet 1 of 2 29Processor Package Drawing Sheet 2 of 2 30Processor Top-Side Markings 32Processor Pin-Out Coordinates, Top View 33Pinout Diagram (Top View-Left Side) .48Pinout Diagram (Top View-Right Side) 49Case Temperature (TC) Measurement Location 60Intel Thermal Monitor 2 Frequency and VOltage Ordering 62Stop Clock State Machine 68

References 9Core Frequency to Front Side Bus Multiplier Configuration 12VOltage Identification Definition 13Front Side Bus Pin Groups 16Signal Description Table 17Signal Reference VOltages 17BSEL[1 :0] Frequency Table for BCLK[1 :0] 18Absolute Maximum and Minimum Ratings 19VOltage and Current Specifications 20VCC Core Deep Sleep State VOltage Regulator Static and Transient Tolerance(Deep Sleep VI D Offset = 1.7%) 22GTL+ Signal Group DC Specifications 23Asynchronous GTL+ Signal Group DC Specifications 23PWRGOOD and TAP Signal Group DC Specifications 24VCCVI D DC Specifications 24VIDPWRGD DC Specifications 24BSEL [1 :0] and VID[5:0] DC Specifications 25BOOTSELECT DC Specifications 25VCC Overshoot Specifications 25Processor Loading Specifications 31Package Handling Guidelines 31Processor Materials 32Alphabetical Pin Assignments 35Numerical Pin Assignment 42Signal Description 50Processor Thermal Specifications 60Thermal Diode Parameters 64Thermal Diode Interface 65Power-On Configuration Option Pins 67



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i n t e l Revision HistoryRevision Description DateNumber

001 Initial release June 2004 Added Mobile Intel Pentium 4 Processor 548 specifications (3.33 GHz)002 September 2004 Updated references table003 Added Mobile Intel Pentium 4 Processor 552 specifications (3.46 GHz) January 2005

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I-t_I Introduction' e l l :1 Introduction

The Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nmprocess technology is a follow on to the Mobile Intel Pentium 4 processor on 130-nm processtechnology in the 478-pin package with enhancements to the Intel NetBurst microarchitecture.The processor utilizes Flip-Chip Pin Grid Array (FC-mPGA4) package technology, and plugs intoa zero insertion force (ZIF) socket. The Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology, like its predecessor, the Mobile IntelPentium 4 processor in the 478-pin package, is based on the same Intel 32-bit microarchitectureand maintains the tradition of compatibility with IA-32 software. In this document the Mobile IntelPentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology willbe referred to asthe "the processor."The Mobile Intel Pentium 4 processor on 90-nm process technology supports Hyper-ThreadingTechnology. Hyper-Threading Technology allows a single, physical processor to function as twological processors. While some execution resources such ascaches, execution units, and busesareshared, each logical processor has its own architecture state with its own set of general-purposeregisters, control registers to provide increased system responsiveness in multitaskingenvironments, and headroom for next generation multi threaded applications. Intel recommendsenabling Hyper-Threading Technology with Microsoft Windows* XP Professional orWindows*XP Home, and disabling Hyper-Threading Technology via the BIOS for all previousversions of Windows operating systems. For more information on Hyper-Threading Technology,seewww.intel.com/info/hyperthreading. Refer to Section 6.1 for Hyper-Threading Technologyconfiguration detai Is.In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 newinstructions, which further extend the capabilities of Intel processor technology. These newinstructions are called Streaming SIMD Extensions 3 (SSE3).These new instructions enhance theperformance of optimized applications for the digital home such as video, image processing andmedia compression technology. 3D graphics and other entertainment applications such asgamingwill take advantage of these new instructions as platforms with the Mobile Intel Pentium 4processor supporting Hyper-Threading Technology on 90-nm process technology and SSE3become available in the market place.The processor's Intel NetBurst micro architecture front side bus (FSB) utilizes a split-transaction,deferred reply protocol like the previous Mobile Intel Pentium 4 processor. The Intel NetBurstmicroarchitecture front side bus usesSource-Synchronous Transfer (SST) of address and data toimprove performance by transferring data four times per bus clock (4X data transfer rate, as inAGP 4X). Along with the 4X data bus, the address bus can deliver addressestwo times per busclock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X databus and 2X address bus provide a data bus bandwidth of up to 4.3 GB/s .The processor will feature Enhanced Intel SpeedStep'" technology, which will enable real-timedynamic switching between multiple voltage and operating frequency points. This results inoptimal performance without compromising low power. The processor features the Auto Halt, StopGrant, Deep Sleep, and Deeper Sleep low power states.The processor includes an address bus powerdown capability which removes power from theaddressand data pins when the FSB is not in use.This feature is always enabled on the processor.

http://www.intel.com/info/hyperthreading.http://www.intel.com/info/hyperthreading.


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Introduction I -nt_I' e l l :1.1 Terminology

A # symbol after a signal name refers to an active low signal, indicating a signal is in the activestate when driven to a low level. For example, when RESET# is low, a reset has been requested.Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals wherethe name does not imply an active state but describes part of a binary sequence (such as address ordata), the # symbol implies that the signal is inverted. For example, 0[3:0] = HLHL refers to a hexA . and 0[3:0]# = LHLH also refers to a hex A (H= High logic level, L= Low logic level).Front side bus (FSB) refers to the interface between the processor and system core logic (thechipset components). The FSB is a multiprocessing interface to processors, memory, and 1/0.

1.1.1 Processor Packaging TerminologyCommonly used terms are explained here for clarification: Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm

process technology - Processor in the Micro-FCPGA package with a 1-MB L2 cache. Processor - For this document, the term processor is the generic form of the Mobile IntelPentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology.

Keep-out zone - The area on or near the processor that system design can not utilize. Intel 852GM/852GME/852PM chipsets - Intel's Portability chip sets which support DDRmemory technology for the Mobile Intel Pentium 4 processor supporting Hyper-ThreadingTechnology on 90-nm process technology. Processor core - Processor core die with integrated L2 cache. FC-mPGA4 package - The Mobile Intel Pentium 4 processor supporting Hyper- ThreadingTechnology on 90-nm process technology is available in a Flip-Chip Micro Pin Grid Array 4package, consisting of a processor core mounted on a pinned substrate with an integrated heatspreader (IHS). This packaging technology employs a 1.27 mm [0.05 in] pitch for the substratepins.

mPGA479 socket - The Mobile Intel Pentium 4 processor supporting Hyper- ThreadingTechnology on 90-nm process technology mates with the system board through a surfacemount, 479-pin, zero insertion force (ZIF) socket.

Integrated heat spreader (lHS) -Aomponent of the processor package used to enhancethe thermal performance of the package. Component thermal solutions interface with theprocessor at the IHS surface. Storage Conditions - refers to a non-operational state. The processor may be installed in aplatform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.Under these conditions, processor pins should not be connected to any supply voltages, haveany II0s biased, or receive any clocks.Upon exposure to "free air" (i.e., unsealed packaging or a device removed from packagingmaterial) the processor must handled in accordance with moisture sensitivity labeling (MSL)as indicated on the packaging material.

Functional operation - refers to normal operating conditions in which all processorspecifications, including DC, AC, FSB, signal quality, mechanical and thermal, are satisfied.



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I-t_I Introduction' e l l :1.2 References

Material and concepts available in the following documents may be beneficial when reading thisdocument:

Table 1-1. ReferencesDocument Reference Number

Intel 852GME and Intel 852PM Chipset Platforms Design Guide 253026Intel Architecture Software Developer's Manual

Volume 1: Basic Architecture 253665Volume 2A: Instruction Set Reference, A-M 253666Volume 2B: Instruction Set Reference, N=Z 253667Volume 3: System Programming Guide 253668

ITP700 Debug Port Design Guide 249679



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Introduction i n t e l

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I-t_I Electrical Specifications' e l l :2 ElectricalSpecificauons2.1 Power and Ground Pins

For clean on-chip power distribution, the processor has 85 V cc (power) and 179 V 55 (ground) pins.All power pins must be connected to V cc - while all V 55 pins must be connected to a system groundplane.The processor Vcc pins must be supplied the voltage determined by the VI D (Voltageidentification) pins.

2.2 Oecoupling GuidelinesDue to its large number of transistors and high internal clock speeds, the processor is capable ofgenerating large current swings between low and full power states. This may cause voltages onpower planes to sag below their minimum values if bulk decoupling is not adequate. Care must betaken in the board design to ensure that the voltage provided to the processor remains within thespecifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetimeof the component. For further information and design guidelines, refer to the Intel 852GME andtmet" 852PM Chipset Platforms Design Guide.

2 . 2 . 1 Vcc OecouplingRegulator solutions need to provide bulk capacitance with a low effective series resistance (ESR)and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for thelarge current swings when the part is powering on, or entering/exiting low power states, must beprovided by the voltage regulator solution (VR). For more details on this topic, refer to the /ntel852GME and /ntel 852PM Chipset Platforms Design Guide.

2 . 2 . 2 Front Side Bus GTL+ OecouplingThe processor integrates signal termination on the die aswell as incorporating high frequencydecoupling capacitance on the processor package. Decoupling must also be provided by the systembaseboard for proper GTL+ bus operation. For more information, refer to the /ntel 852GME andtmet" 852PM Chipset Platforms Design Guide.

2 . 2 . 3 Front Side Bus Clock (BCLK[l :0]) and Processor ClockingBCLK[1 :0] directly controls the front side bus interface speed aswell as the core frequency of theprocessor. As in previous generation processors, the processor core frequency is a multiple of theBCLK[1 :0] frequency. No user intervention is necessary, and the processor will automatically runat the speed indicated on the package. The processor usesa differential clocking implementation.

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Electrical Specifications in telTable 2-1. Core Frequency to Front Side Bus Multiplier Configuration

Multiplication of System Core FrequencyCore Frequency to Front (133 MHz BCLK/533Side Bus Frequency MHz FSB)

1/14 1.86 GHz1/15 2.00 GHz1/16 2.13 GHz1/17 2.26 GHz1/18 2.40 GHz1/19 2.53 GHz1/20 2.66 GHz1/21 2.80 GHz1/22 2.93 GHz1/23 3.06 GHz1/24 3.20 GHz1/25 3.33 GHz1/26 3.46 GHz1/27 3.60 GHz

NOTE: Individual processors operate only at or below the rated frequency.

2 . 3 Voltage IdentificationThe voltage set by the VI 0 signals is the reference VR output voltage to be delivered to theprocessor Vcc pins. A minimum voltage is provided in Table 2-8 and changes with frequency. Thisallows processors running at a higher frequency to have a relaxed minimum voltage specification.The specifications have been set such that one voltage regulator can work with all supportedfrequencies.Individual processor VIO values may be calibrated during manufacturing such that two devices atthe same speed may have different VIO settings.The processor usessix voltage identification pins, VI 0[5:0], to support automatic selection ofpower supply voltages. Table 2-2 specifies the voltage level corresponding to the state of V I0[5:0].A 1 in this table refers to a high voltage level and a 0 refers to low voltage level. If the processorsocket is empty (VI0[5:0] = x11111), or the voltage regulation circuit cannot supply the voltagethat is requested, it must disable itself.

Power source characteristics must be guaranteed to be stable whenever the supply to the voltageregulator is stable.The processor's Voltage Identification circuit requires an independent 1.2-V supply and some otherpower sequencing considerations.



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intel~ Electrical SpecificationsTable 2-2. VOltage Identification Definition

VID5 VID4 VID3 VID2 VID1 VIDO VID VID5 VID4 VID3 VID2 VID1 VIDO VID0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.21251 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.22500 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.23751 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.25000 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.26251 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.27500 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.28751 0 0 1 1 0 0.9250 1 1 0 1 1 0 1.30000 0 0 1 1 0 0.9375 0 1 0 1 1 0 1.31251 0 0 1 0 1 0.9500 1 1 0 1 0 1 1.32500 0 0 1 0 1 0.9625 0 1 0 1 0 1 1.33751 0 0 1 0 0 0.9750 1 1 0 1 0 0 1.35000 0 0 1 0 0 0.9875 0 1 0 1 0 0 1.36251 0 0 0 1 1 1.0000 1 1 0 0 1 1 1.37500 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.38751 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.40000 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.41251 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.42500 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.43751 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.45000 0 0 0 0 0 1.0875 0 1 0 0 0 0 1.46251 1 1 1 1 1 VR output off 1 0 1 1 1 1 1.47500 1 1 1 1 1 VR output off 0 0 1 1 1 1 1.48751 1 1 1 1 0 1.1000 1 0 1 1 1 0 1.50000 1 1 1 1 0 1.1125 0 0 1 1 1 0 1.51251 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.52500 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.53751 1 1 1 0 0 1.1500 1 0 1 1 0 0 1.55000 1 1 1 0 0 1.1625 0 0 1 1 0 0 1.5625

1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.57500 1 1 0 1 1 1.1875 0 0 1 0 1 1 1.58751 1 1 0 1 0 1.2000 1 0 1 0 1 0 1.6000



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Electrical Specifications

2.3.1 Phase Lock Loop (PLL) Power and Filteri n t e l

V CCA and V CCIOPLL are power sources required by the PLL clock generators on the processorsilicon. Since these PLLs are analog in nature, they require low noise power supplies for minimumjitter. Jitter is detrimental to the system: it degrades external 1/0 timings aswell as internal coretimings (i.e., maximum frequency). To prevent this degradation, these supplies must be low passfi Itered from V cc -The AC low-pass requirements, with input at Vcc are as follows: < 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Fi!i1ure2-1. For recommendations on implementing thefilter refer to the Intel@852GME and Intel 852PM Chipset Platforms Design Guide.

Figure 21. Phase Lock Loop (PLL) Filter Requirements

-28 as

forbiddenzone

0.2 aso a s

-0.5 es


-34 as

DC. . . 1 Hz 1 MHz 66 MHzpeak fcorepassband high frequencyband

NOTES:1. Diagram not to scale.2. No specification exists for frequencies beyond fcore (core frequency).3. fpeak, if existent, should be less than 0.05 MHz.


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I-t_I Electrical Specifications' e l l :2.4 Reserved, Unused, and TESTHI Pins

All RESERVED pins must remain unconnected. Connection of these pins to V cc - Vss. or to anyother signal (including each other) can result in component malfunction or incompatibility withfuture processors. See Chapter 4 for a pin Iisting of the processor and the location of allRESERVED pins.For reliable operation, always connect unused inputs or bidirectional signals to an appropriatesignal level. In a system level design, on-die termination has been included on the processor toallow signals to be terminated within the processor silicon. Most unused GTL+ inputs should beleft as no connects, as GTL+ termination is provided on the processor silicon. However, seeTable 2-4 for details on GTL+ signals that do not include on-die termination. Unused active highinputs should be connected through a resistor to ground (V ss). Unused outputs can be leftunconnected, however this may interfere with some test access port (TAP) functions, complicatedebug probing, and prevent boundary scan testing. A resistor must be used when tyingbidirectional signals to power or ground. When tying any signal to power or ground, a resistor willalso allow for system testability. For unused GTL+ input or I/O signals, use pull-up resistors of thesame value as the on-die termination resistors (Rn).TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-dietermination. Inputs and used outputs must be terminated on the system board. Unused outputs maybe terminated on the system board or left unconnected. Note that leaving unused outputsunterminated may interfere with some TAP functions, complicate debug probing, and preventboundary scan testing. Signal termination for these signal types is discussed in the /nte/@ 852GMEand /nte/@ 852PM Chipset Platforms Design Guide.The TESTHI pins must be tied to the processor Vee using a matched resistor, where a matchedresistor has a resistance value within +/-20% of the impedance of the board transmission l inetraces. For example, if the trace impedance is 60 Q then a value between 48 Q and 72 Q isrequired.The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. Amatched resistor should be used for each group: TESTH I[1 :0] TESTHI[7:2] TESTH 18- cannot be grouped with other TESTH I signals TESTH 19- cannot be grouped with other TESTH I signals TESTHl10 - cannot be grouped with other TESTHI signals TESTHl11 - cannot be grouped with other TESTHI signals

2 . 5 Front Side Bus Signal GroupsThe front side bus signals have been combined into groups by buffer type. GTL + input signals havedifferential input buffers, which use GTLREF as a reference level. In this document, the term"GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving.Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group whendriving.



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Electrical Specifications in telWith the implementation of a source synchronous data bus comes the need to specify two sets oftiming parameters. One set is for common clock signals which are dependent upon the rising edgeof BClKO (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signalswhich are relative to their respective strobe lines (data and address) as well as the rising edge ofBC lKO . Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active atany time during the clock cycle. Table 2-3 identifies which signals are common clock, sourcesynchronous, and asynchronous.

Table 2-3. Front Side Bus Pin GroupsSignal Group Type Signals'

GTL+ Common Clock Synchronous to BPRI#, DEFER#, RESET#, RSI2:0]#, RSP#, TRDY#Input BCLKl1 :0]GTL+ Common Clock Synchronous to API1:0]#, ADS#, BINIT#, BNR#, BPMI5:0]#, BRO#, DBSY#,1 /0 BCLKl1 :0] DPI3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

Signals Associated StrobeREQI4:0]#, AI16:3]#3 ADSTBO#

GTL+ Source Synchronous to assoc. AI35:17]#3 ADSTB1#Synchronous 1 /0 strobe 0115:0]#, DBIO# DSTBPO#, DSTBNO#DI31:16]#,DBI1# DSTBP1#,DSTBN1#0147:32]#, DBI2# DSTBP2#, DSTBN2#0163:48]#, DBI3# DSTBP3#, DSTBN3#

GTL + Strobes Synchronous to ADSTBl1 :0]#, DSTBPI3:0]#, DSTBNI3:0]#BCLKl1 :0]Asynchronous GTL+ A20M#, DPSLP#, IGNNE#, INIT#, LlNTOIINTR. LlNT1/NMI,Input SMI#, SLP#, STPCLK#Asynchronous GTL+ FERR#/PBE#, IERR#, THERMTRIP#OutputAsynchronous GTL+ PROCHOT#Input/OutputTAP Input Synchronous to TCK TCK, TDI, TMS, TRST#TAP Output Synchronous to TCK TOOFront Side Bus Clock Clock BCLKl1 :0], ITP_CLKI1 :0]2

VceoVCCA, VCCIOPLL,VIDI5:0], VSS, VSSA, GTLREFI3:0],COMPl1 :0], RESERVED, TESTHl111 :0], THERMDA,

Power/Other THERMDC, VCC_SENSE, VSS_SENSE, VCCVID,VCCVIDLB, BSELl1 :0], SKTOCC#, DBR#2, VIDPWRGD,BOOTS ELECT, OPTIMIZED/COMPAT#' PWRGOOD

NOTES:1. Refer to Sect ion 4.2 for signal descript ions.2. In processor systems where there is no debug port implemented on the system board, these signals are usedto support a debug port interposer. In systems with the debug por t implemented on the system board, thesesignals are no connects.

3. The value of these pins during the active-to-inactive edge of RESET# defines the processor configurationoptions. See Sect ion 6.1 for detai ls.



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intel~ Electrical SpecificationsTable 2-4. Signal Description Table

Signals with Rn Signals with noRnA[35:3]#, AOS#, AOSTB[ l :0]#, AP[l :0]#, BINIT#, A20M#, BCLK[ l :0], BPM[5:0]#, BRO#, BSEL[l :0] ,BNR#, BOOTSELECT2, BPRI#, 0[63:0]#, OBI [3:0]#, COMP[l :0] , OPSLP#, FERR#/PBE#, IERR#,IGNNE#, INIT#, LlNTO/INTR, LlNT1/NMI,OBSY#, OEFER#, OP[3:0]#, OROY#, OSTBN[3:0]#, PWRGOOO, RESET#, SKTOCC#, SLP#, SMI#,OSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,OPTIMIZEO/COMPAT#2, PROCHOT#, REQ[4:0]#, STPCLK#, TOO, TESTHI[ ll :0] , THERMOA,THERMOC, THERMTRIP#, VI0[5:0], VIOPWRGO,RS[2:0]#, RSP#, TROY# GTLREF[3:0] , TCK, TOI, TRST#, TMS

Open Drain Signals1BSEL[l :0], VI0[5:0], THERMTRIP#, FERR#/PBE#,IERR#, BPM[5:0]#, BRO#, TOONOTES:1. Signals that do not have Rn, nor are act ively driven to their high-voltage level.2. The OPTIMIZEO/COMPAT# and BOOTS ELECT pins have a 500-5000 Q pullup to VCCVIO rather than Rn.

Table 2-5. Signal Reference VOltages

2 . 6

2 . 7

GTLREF Vcc/2 VCCVID/2BPM[5:0]#, LlNTOIINTR, LlNT1/NMI, RESET#, BINIT#,BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BRO#, A20M#, OPSLP#, IGNNE#, VIOPWRGO,A[35:0]#, AOS#, AOSTB[l :0]#, AP[l :0]#, BPRI#, 0[63:0]#, INIT#, PWRG0001, SLP#, BOOTSELECT,OBI[3:0]#, OBSY#, OEFER#, OP[3:0]#, OROY#, SMI#, STPCLK#, TCK1, OPTIMIZEOIOSTBN[3:0]#, OSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TOI1, TMS1, TRST#1 COMPAT#RSP#, TROY#NOTE: These signals also have hysteresis added to the reference voltage. See Table 2-12 for moreinformation.

Asynchronous GTL+ SignalsLegacy input signals such as A20M#, OPSLP#, [GNNE#, [N[T#, SM[#, SLP#, and STPCLK#uti I ize CMOS input buffers. All of these signals follow the same DC requirements as GTL +signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by theprocessor. These signals do not have setup or hold time specifications in relation to BCLK[l :0].

Test Access Port (TAP) ConnectionDue to the voltaqe levels supported by other components in the Test Access Port (TAP) logic, it isrecommended that the processor be first in the TAP chain and followed by any other componentswithin the system. A translation buffer should be used to connect to the rest of the chain unless oneof the other components is capable of accepting an input of the appropriate voltaqe level. Simi larconsiderations must be made for TCK, TMS, TRST#, TO!. and TOO. Two copies of each signalmay be required, with each driving a different voltaqe level.

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Electrical Specifications i n t e l 2 . 8 Front Side Bus Frequency Select Signals

(BSEL[1 :0])The BSEL[l :0] signals are used to select the frequency of the processor input clock (BCLK[l :0]).Table 2-6 defines the possible combinations of the signals and the frequency associated with eachcombination. The required frequency is determined by the processor, chipset, and clocksynthesizer. All agents must operate at the same frequency.The processor currently operates at a 533-MHz front side bus frequency (selected by a133-MHz BCLK[l :0] frequency). Individual processors will only operate at their specified frontside bus frequency.For more information about these pins refer to Section 4.2 and the appropriate platform designguidelines.

Table 2-6. BSEL[1 :0] Frequency Table for BCLK[1 :0]BSEL1 BSELO Function

L L RESERVEDL H 133 MHzH L RESERVEDH H RESERVED

2 . 9 Absolute Maximum and Minimum RatingsTable 2-7 specifies absolute maximum and minimum ratings. Within functional operation limits,functionali ty and long-term reliability can be expected.At conditions outside functional operation condition limits, but within absolute maximum andminimum ratings, neither functionality nor long-term reliability can be expected. If a device isreturned to conditions within functional operation limits after having been subjected to conditionsoutside these limits, but within the absolute maximum and minimum ratings, the device may befunctional, but with its lifetime degraded depending on exposure to conditions exceeding thefunctional operation condition limits.At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for anylength of time then, when returned to conditions within the functional operating condition limits, itwill either not function, or its reliability will be severely degraded.Although the processor contains protective circuitry to resist damage from stat ic electric discharge,precautions should always be taken to avoid high static voltaqes or electric fields.

18 Mobile Intel Pentium 4 Processor Support ing Hyper-Threading Technology on 90-nm Process Technology Datasheet


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intel~ Electrical SpecificationsTable 27. Absolute Maximum and Minimum Ratings

2.10

2.10.1

Symbol Parameter Min Max Unit Notes

Vee Any processor supply - 0.3 1.55 V 1,2voltage with respect to VSS

Te Processor case See Section 5 See Section 5 C 3,4temperatureTSTORAGE Processor storage -10 +45 C 3,4,5temperatureNOTES:1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications mustbe satisfied.

2. Overshoot and undershoot voltage guidelines for input, output and 1/ 0 signals are outlined in Section 3.Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3. Storage temperature isapplicable to storage conditions only. Inthis scenario, the processor must not receivea clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, please refer to the processor case temperaturespecifications.

4. This rating applies to the processor and does not include any tray or packaging.5. Contact Intel for storage requirements in excess of one year.

Processor DC SpecificationsThe processor DC specifications in this section are defined at the processor core silicon andnot at the package pins unless noted otherwise. See Section 4 for the pin signal definitions andsignal pin assignments, Most of the signals on the processor front side bus are in the GTL + signalgroup, The DC specifications for these signals are listed in Table 2-10,Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltageCMOS buffer types, However, these interfaces now follow DC specifications similar to GTL+, TheDC specifications for these signal groups are I isted in Table 2-11 and Table 2-12,Table 2-8 through Table 2-16 I ist the DC specifications for the processor and are val id only whi Iemeeting specifications for case temperature, clock frequency, and input voltages, Care should betaken to read all notes associated with each parameter.

Fixed Mobile Solution (FMS)The FMS guidel ines are estimates of the maximum values the mobile processor wi II have overcertain time periods, The values are only estimates and actual specifications for future processorsmay differ, The processor mayor may not have specifications equal to the FMS value in theforeseeable future, System designers should meet the FMS values to ensure their systems will becompatible with future releases of the mobile processor,



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Electrical Specifications i n t e l Table 2-8. VOltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes2

HFM VID VID range for HFM (Highest Frequency 1.250 1.400 V 1Mode)LFM VID VID for LFM N/A 1.150 N/A V(Lowest Frequency Mode)VID VID step size during a transition N/A N/A 12.5 mV 12TransitionVcc Vcc for FMSO.5 processors See Table and VID - Icc(max) * 1.45 mQ V 3, 4, 5Figure 2-2

Processor Core FrequencyNumber

Icc for processor with VID= 1.15 V: 44

1.86 GHzIcc for processor with

Icc multiple VID: A 7, 10518 2.80 GHz 80532 3.06 GHz 80538 3.20 GHz 80548 3.33 GHz 80552 3.46 GHz 80

FMSO.5 80

VCCDPRSLP Static and Transient Deeper Sleep Voltage 0.95 1.0 1.05 V 2, 3Processor Core FrequencyNumber

Icc Stop-Grant1.86 GHz 31

ISGNT 518 2.80 GHz 40 A 6,9, 13IsLP 532 3.06 GHz 40538 3.20 GHz 40548 3.33 GHz 40552 3.46 GHz 40

ITCC IccTCC active Icc A 8Icc_vccA Icc for PLL pins 60 mA 11'cc,VCCIOPLL Iccfor 1/ 0 PLL pin 60 mA 11Icc_GTLREF Icc for GTLREF pins (all pins) 200 ).lA'cc,vCCVlol Icc for VCCVIDIVCCVIDLB 150 mA 11VCCVIOLB

NOTES:1. Individual processor VID values may be calibrated during manufacturing such that two devices at the samespeed may have different VID settings.

2. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empiricaldata. These specifications will be updated with characterized data from silicon measurements at a later date.



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intel~ Electrical Specifications3. These voltages are targets only. A variable voltage source should exist on systems in the event that adifferent voltage is required. See Section 2.3 and Table 2-2 for more information.

4. The voltage specification requirements are measured across Vee SENSE and Vss SENSE pins at the socket witha 1OOMHzbandwidth oscilloscope, 1.5 pFmaximum probe capacli:ance, and 1 I V f Q minimum impedance. Themaximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from thesystem is not coupled into the oscilloscope probe.

5. Refer to Table, Table 2-9, and Figure 2-2 for the minimum, typical, and maximum Veeallowed for a givencurrent. The processor should not be subjected to any Veeand leecombination wherein Veeexceeds Vee M AXfor a given current. Moreover, Veeshould never exceed the VIO voltage. Failure to adhere to this -specification can shorten the processor lifetime.

6. The current specified is also for AutoHALT State.7. FMS is the Fixed Mobile Solution guideline. These guidelines are for estimation purposes only. SeeSection 2.10.1 for further details on FMS guidelines

8. The maximum instantaneous current the processor will draw while the thermal control circuit is active asindicated by the assertion of PROCHOT# is the same as the maximum lee for the processor.

9. leeStop-Grant and leeSleep are specified at Vee M A X .10.lee M AX is specified at Vee M A X . -11.These parameters are based on design characterization and are not tested.12.This specification represents the Vee reduction due to each VIO transition. See Section 2.3. AC timing

requirements will be included in future revisions of this document.13.The specifications for the Battery Optimized Mode (1.86 GHz at 1.15 VIO) are not 100% tested. Thesespecifications are determined by characterization of the processor currents at higher voltage and frequencyand extrapolating the values for the Battery Optimized mode voltage and frequency.

Vcc Static and Transient ToleranceVoltage Deviation from VID Setting (V),,2,3

Icc (A)Maximum Typical Minimum

0 0.000 -0.025 -0.0505 -0.007 -0.033 -0.05910 -0.015 -0.041 -0.06815 -0.022 -0.049 -0.07720 -0.029 -0.058 -0.08625 -0.036 -0.066 -0.09530 -0.044 -0.074 -0.10435 -0.051 -0.082 -0.11340 -0.058 -0.090 -0.12245 -0.065 -0.098 -0.13150 -0.073 -0.106 -0.14055 -0.080 -0.114 -0.14960 -0.087 -0.123 -0.15865 -0.094 -0.131 -0.16770 -0.102 -0.139 -0.17675 -0.109 -0.147 -0.18580 -0.116 -0.155 -0.194

NOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as shown inSection 2.11.

2. This table is intended to aid in reading discrete points on Figure 2-2.3. The loadlines specify voltage limits at the die measured at the Vee SENSE and Vss SENSE pins.4. Voltage regulation feedback for voltage regulator circuits must be taken from processor Veeand Vsspins.

Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology Oatasheet 21


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Electrical Specifications i n t e l Table 2-9. Vee Core Deep Sleep State VOltage Regulator Static and Transient Tolerance

(Deep Sleep VID Offset = 1.7%)Voltage Deviation from (VID Setting 1.7% of VID Setting) (V),,2,3,4

Icc (A) Maximum Typical Minimum0 0.000 -0.025 -0.0505 -0.007 -0.033 -0.05910 -0.015 -0.041 -0.06815 -0.022 -0.049 -0.07720 -0.029 -0.058 -0.08625 -0.036 -0.066 -0.09530 -0.044 -0.074 -0.10435 -0.051 -0.082 -0.11340 -0.058 -0.090 -0.122

NOTES:1. The loadline specifications include both static and transient limits.2. This table is intended to aid in reading discrete points on Figure 2-2.3. The loadlines specify voltage limits at the die measured at the Vee SENSE and Vss SENSE pins. Voltageregulation feedback for voltage regulator circuits must be taken from processor V-eeand Vss pins.4. The voltage used in Deep Sleep mode must first be offset by 1.7% from the VID setting before reading thevoltage deviation on respective loadline.

Figure 2-2. Vcc Static and Transient Tolerance 1,2,3

Icc [A ]10 15 20 25 30 35 40 45 50 55 60 65 70 75

VID0.025 Va: .I\/IaxirrumVID0.050

VID0.075

Va:.Minimum

~U VID-O.100~VID0.125 Va: .TypicalVID0.150

VID0.175

VID-0.200_L_----------------------------------

NOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as shown inSection 2.11.

2. This loadline specification shows the deviation from the VID set point.



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intel~ Electrical Specifications3. The loadlines specify voltage limits at the die measured at the Vee SENSEnd Vss SENSEins. Voltageregulation feedback for voltage regulator circuits must be taken from processor V-eeand Vss pins.

Table 2-10. GTL+ Signal Group DC SpecificationsSymbol Parameter Min Max Unit Notes'VIL Input Low Voltage 0.0 GTLREF - (0.10 * Vee) V 2, 6VIH Input High Voltage GTLREF + (0.10 * Vee V 3, 4, 6Vee)VOH Output High Voltage 0.90*Vee Vee V 4, 6IOL Output Low Current N/A Veel A[(0.50*Rn_MIN)+(RoN_MIN)]III Input Leakage Current N/A 200 iJA 7ILO Output Leakage Current N/A 200 iJA 8RON Buffer On Resistance 8 12 Q 5

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. VILis defined as the voltage range at a receiving agent that will be interpreted as a logical low value.3. VIHis defined as the voltage range at a receiving agent that will be interpreted as a logical high value.4. VIHand VOHmay experience excursions above Vee' However, input signal drivers must comply with the signalquality specifications.

5. Refer to processor 1 /0 Buffer Models for IIV characteristics.6. The Veereferred to in these specifications is the instantaneous Vee'7. Leakage to Vss with pin held at Vee'8. Leakage to Veewith pin held at 300 mV.

Table 2-11. Asynchronous GTL+ Signal Group DC SpecificationsSymbol Parameter Min Max Unit Notes'VIL Input Low Voltage 0.0 Vee/2 - (0.10 * Vee) 3, 11VIH Input High Voltage Vee/2 + (0.10 * Vee) Vee

4,5,7,11

VOH Output High Voltage 0.90*Vee Vee V 2, 5, 7IOL Output Low Current Vee/[(0.50*Rn MIN)+(RONMIN)] A 8- -III Input Leakage Current N/A 200 iJA 9ILO Output Leakage Current N/A 200 iJA 10RON Buffer On Resistance 8 12 Q 6

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. All outputs are open drain.3. V1Lis defined as the voltage range at a receiving agent that will be interpreted as a logical low value.4. V1His defined as the voltage range at a receiving agent that will be interpreted as a logical high value.5. Refer to the processor 1 /0 Buffer Models for IIV characteristics.6. The Veereferred to in these specifications refers to instantaneous Vee'7. The maximum output current is based on maximum current handling capability of the buffer and is notspecified into the test load.

8. Leakage to Vss with pin held at Vee'9. Leakage to Veewith pin held at 300 mV.10.LlNTOIINTR and LlNTl/NMI use GTLREF as a reference voltage. For these two signals VIH= GTLREF +(0.10 * Vee) and VIL= GTLREF - (0.10 * Vcc).



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Electrical Specifications i n t e l Table 2-12. PWRGOOD and TAP Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1,2

VHYS Input Hysteresis 200 350 mV 7VT+ Input low to high 0.5 * (Vee + VHYS_MIN) 0.5 * (Vee + VHYS_MAX) V 5threshold voltageVT- Input high to low 0.5 * (Vee- VHYS_MAX) 0.5 * (Vee - VHYS_MIN) V 5threshold voltageVOH Output High Voltage N/A Vee V 3, 5IOL Output Low Current 45 mA 6III Input Leakage Current 200 iJAILO Output Leakage Current 200 iJARON Buffer On Resistance 7 12 Q 4

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. All outputs are open drain.3. Refer to the processor 1/ 0 Buffer Models for IIV characteristics.4. The Veereferred to in these specifications refers to instantaneous Vee'5. The maximum output current is based on maximum current handling capability of the buffer and is notspecified into the test load.

6. VHySrepresents the amount of hysteresis, nominally centered about 0.5 * Vee for all TAP inputs.7. Leakage to Vss with pin held at Vee'8. Leakage to Veewith Pin held at 300 mV.

Table 2-13. VCCVID DC SpecificationsSymbol Parameter Min Typ Max Unit NotesVCCVID Voltage 1.14 1.2 1.26 VVCCVIDLB Voltage 1.14 1.2 1.26 V

Table 2-14. VIDPWRGD DC SpecificationsSymbol Parameter Min Typ Max Unit NotesVIL Input Low Voltage 0.3 VVIH Input High Voltage 0.9



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intel~ Electrical SpecificationsTable 2-15. BSEL [1:0] and VID[5:0] DC Specifications

Symbol Parameter Max Unit Notes'RON(BSEL) Buffer On Resistance 60 Q 2

RON Buffer On Resistance 60 Q 2(VIO)

10L Max Pin Current 8 mA

ILO Output Leakage Current 200 jJA 3VTOL Voltage Tolerance 3.3 + 5% V

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. These parameters are not tested and are based on design simulations.3. Leakage to Vss with pin held at 2.5 V.

Table 2-16. BOOTSELECT DC SpecificationsSymbol Parameter Min Typ Max Unit NotesV1L Input Low Voltage 0.2 * VCCVIO V 1V1H Input High Voltage 0.8 * VCCVIO 60 V 1

NOTE: These parameters are not tested and are based on design simulations.

2.11 Vee Overshoot SpecificationThe processor can tolerate short transient overshoot events where Vee exceeds the VI D voltaqewhen transitioning from a high to low current load condition. This overshoot cannot exceed VI D +Vos M A X (Vos M A X is the maximum allowable overshoot voltage). The time duration of theovershoot eve-nt must not exceed Tos M A X (Tos M A X is the maximum allowable time duration aboveVI D). These specifications apply to t ile processor die voltaqe asmeasured across the VCC_SENSEand VSS_SENSE pins.

Table 2-17. Vee Overshoot SpecificationsSymbol Parameter Min Typ Max Unit Figure Notes

Vas_MAx Magnitude of Vee 0.050 V 2-3overshoot above VIO

Tas_MAx Time duration of Vee 25 f.ls 2-3overshoot above VIO

Mobile Intel Pentium 4 Processor Support ing Hyper-Threading Technology on 90-nm Process Technology Oatasheet 25


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Electrical Specifications i n t e l Figure 23. Vee Overshoot Example Waveform

2.11.1

Example Overshoot WaveformVID + 0.050 ".> ~ Vosf\\ -:


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I-t_I Package Mechanical Specifications' e l l :3 Package Mechanical

Specifications3.1 PackageMechanicalSpecifications

The Mobile processor is packaged in a Flip-Chip Pin Grid Array (FC-mPGA4) package thatinterfaces with the motherboard via a mPGA479 socket. The package consists of a processor coremounted on a substrate pin carrier. An integrated heat spreader (I HS) is attached to the packagesubstrate and core and serves as the mating surface for processor component thermal solutions,such as a heatsink. Figure 3-1 shows a sketch of the processor package components and how theyare assembled together. Refer to the mPGA479, mPGA478A, mPGA478B, mPGA478C, andmPGA476 Socket Design Guidelines for complete details on the mPGA479 socket.The package components shown in Figure 3-1 include the following:1. Integrated Heat Spreader (IHS)2. Thermal Interface Material (TIM)3. Processor core (die)4. Package substrate5. Capacitors

Figure 3-1. Processor Package Assembly Sketch

CORE (DIE)

~

IHS~i illMM I_t ~ - SUBSTRATEr r r Ul mCAPACITORS~

~SOCKET

'---- MOTHERBOARD

-------- - - - - - - - - - - -

NOTE: Socket and motherboard are included for reference and are not part of processor package.



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Package Mechanical Specifications i n t e l 3.1.1 Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings includedimensions necessary to design a thermal solution for the processor. These dimensions include:1. Package reference with tolerances (total height, length, width, etc.)2. IHS parallelism and tilt3. Pin dimensions4. Top-side and back-side component keep-out dimensions5. Reference datums

All drawing dimensions are in mm [in].



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intel~ Package Mechanical SpecificationsFigure 3-2. Processor Package Drawing Sheet 1 of 2

"11111111111111111111';"

F~~u~- JI T Q ~"-~ gr =

. . . . I')..,'"

. . . . . . -e c

-~iI ~~::;r;::;~I ~~'&'&-~__

: ; ; : : "" C>>- ~ ~ '&"" .. ,.. , ~.,::t: """~U~

=



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Package Mechanical Specifications i n t e l Figure 3-3. Processor Package Drawing Sheet 2 of 2

1 1 ' 1 & . 10

I~UUUHHWHWUU~Jt I

D-ot-

o

---------+---------I

o

=


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I-t_I Package Mechanical Specifications' e l l :3.1.2 Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-out zonerequirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupl ing capacitors are typically mounted to either the topside or pin-side of thepackage substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.The location and quantity of package capacitors may change due to manufacturing efficiencies butwill remain within the component keep-in.

3.1.3 Package Loading SpecificationsTable 3-1 provides dynamic and static load specifications for the processor package. Thesemechanical maximum load limits should not be exceeded during heatsink assembly, shippingconditions, or standard use condition. Also, any mechanical system or component testing shouldnot exceed the maximum limits. The processor package substrate should not be used as amechanical reference or load-bearing surface for thermal and mechanical solution. The minimumloading specification must be maintained by any thermal and mechanical solutions.

Table 31. Processor Loading SpecificationsParameter Minimum Maximum NotesStatic 44 N [10 lbf] 445 N [100 lbf] 1,2,3Dynamic 890 N [200 lbf] 1,3,4Transient 667 N [150 lbf] 1,3,5

NOTES:1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS.2. This isthe maximum force that can be applied by a heatsink retention clip. The clip must also provide theminimum specified load on the processor package.

3. These specifications are based on limited testing for design characterization. Loading limits are for thepackage only and does not include the limits of the processor socket.4. Dynamic loading is defined as an 11ms duration average load superimposed on the static load requirement.

5. Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement,representative of loads experienced by the package during heatsink installation.

3.1.4 Package Handling GuidelinesTable 3-2 includes a list of guidelines on package handling in terms of recommended maximumloading on the processor [HS relative to a fixed substrate. These package handling loads may beexperienced during heatsink removal.

Table 32. Package Handling GuidelinesParameter Maximum Recommended NotesShear 356 N [80 lbf] 1, 4Tensile 156 N [35 lbf] 2, 4Torque 8 N-m [70 lbf-in] 3, 4

NOTES:1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.2. A tensile load is defined as a pulling load applied to the IHSin a direction normal to the IHS surface.



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Package Mechanical Specifications i n t e l 3. A torque load isdefined as a twisting load applied to the IHS in an axis of rotation normal to the IHS topsurface.

4. These guidelines are based on limited testing for design characterization.

3 . 1 . 5 Package Insertion SpecificationsThe processor can be inserted into and removed from a mPGA479 socket 15 times. The socketshould meet the mPGA479 requirements detailed in the mPGA479, mPGA478A, mPGA478B,mPGA478C, and mPGA476 Socket Design Guidelines.

3 . 1 . 6 Processor Mass SpecificationThe typical mass of the processor is 19 g [0.67 oz]. This mass [weight] includes all the componentsthat are included in the package.

3 . 1 . 7 Processor MaterialsTable 3-3 I ists some of the package components and associated materials.

Table 33. Processor MaterialsComponent Material

Integrated Heat Spreader (IHS) Nickel Plated CopperSubstrate Fiber Reinforced Resin

Substrate Pins Gold Plated Copper

3 . 1 . 8 Processor MarkingsFigure 3-4 shows the topside markings on the processor. These diagrams are to aid in theidentification of the processor.

Figure 34. Processor Top-Side Markings

FPO2-0 Matrix Mark l i l l AAAAAAAANNNN

Product CodeA TPO - Serial #

QOF / Country of Assy Intel ConfidentialQVVV ES XXXXXi@@'03 ZZZZZZZZFFFFFFFF



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I-t_I Package Mechanical Specifications' e l l :3.1.9 Processor Pin-Out Coordinates

Figure 3-5 shows the top view of the processor pin coordinates. The coordinates are referred tothroughout the document to identi fy processor pins.

Figure 35" Processor Pin-Out Coordinates, Top ViewClocks Async/TAP


26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1. .

AF ooooo i i oooe AFAE 0000.0.: :.00000 AEAD ooo.o.oi ioo.ooo ADAC 0.00.00: :0.00.0.ACAS Q.g.~Q.Q.,_,j i.0 Q. c:fO ASAA .00.000: :09.00. AAy 0.00.0 0.00.0w 00000. .00.00v .00.00 00.00.u 0.00.0 0.00.0T 00.00. .00.00

Data R .00.00Processor 00.00.Addressp 0.00.0 0.00.0N 00.00.Top VI"ew .00.00M 0.00.0 0.00.0.00.00 00.00.K 00.00. .00.000.00.0 - c S - i r o - o . c s - -H .00.00 00.00.G 00.00. .00.000.00.00: :00.00.0E .00.00.: :.00.00. ED oo.oo ! i oo.oo DC 0.00.0.: :.0.00.0 CS .00.00.: :.00.00 SA .0.00 !0000.0....

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

= Vee 0= G TLR EF = Vss 0= Signal/Other

CommonClock


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Package Mechanical Specifications i n t e l



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I-t_I Pin Listing and Signal Descriptions' e l l :4 Pin Listing and Signal

Descriptions4.1 Processor Pin Assignments

This chapter provides the processor pinout and signal description. Table 4-1 provides the pinoutarranged alphabetically by signal name and Table 4-2 provides the pinout arranged numerically bypin number. The pinout footprint is shown in Figure 4-1 and Figure 4-2.

Table 4-1. Alphabetical Pin AssignmentsPin Name Pin Signal Buffer Direction Pin Name Pin Signal Buffer DirectionNumber Type Number TypeA03# K2 Source Synch Input/Output A31# U4 Source Synch Input/OutputA04# K4 Source Synch Input/Output A32# V3 Source Synch Input/OutputAOS# L6 Source Synch Input/Output A33# W2 Source Synch Input/OutputA06# Kl Source Synch Input/Output A34# Yl Source Synch Input/OutputA07# L3 Source Synch Input/Output A3S# ABl Source Synch Input/OutputA08# M6 Source Synch Input/Output A20M# C6 Asynch GTL+ InputA09# L2 Source Synch Input/Output ADS# Gl Common Clock Input/OutputAl0# M3 Source Synch Input/Output ADSTBO# LS Source Synch Input/OutputAll# M4 Source Synch Input/Output ADSTB1# RS Source Synch Input/OutputA12# Nl Source Synch Input/Output APO# ACl Common Clock Input/OutputA13# Ml Source Synch Input/Output AP1# VS Common Clock Input/OutputA14# N2 Source Synch Input/Output BCLKO AF22 Bus Clock InputA1S# N4 Source Synch Input/Output BCLKl AF23 Bus Clock InputA16# NS Source Synch Input/Output BINIT# AA3 Common Clock Input/OutputA17# Tl Source Synch Input/Output BNR# G2 Common Clock Input/OutputA18# R2 Source Synch Input/Output BOOTS ELECT ADl Power/Other InputA19# P3 Source Synch Input/Output BPMO# AC6 Common Clock Input/OutputA20# P4 Source Synch Input/Output BPM1# ABS Common Clock Input/OutputA21# R3 Source Synch Input/Output BPM2# AC4 Common Clock Input/OutputA22# T2 Source Synch Input/Output BPM3# Y6 Common Clock Input/OutputA23# Ul Source Synch Input/Output BPM4# AAS Common Clock Input/OutputA24# P6 Source Synch Input/Output BPMS# AB4 Common Clock Input/OutputA2S# U3 Source Synch Input/Output BPRI# 02 Common Clock InputA26# T4 Source Synch Input/Output BRO# H6 Common Clock Input/OutputA27# V2 Source Synch Input/Output BSELO AD6 Power/Other OutputA28# R6 Source Synch Input/Output BSEL1 ADS Power/Other OutputA29# Wl Source Synch Input/Output COMPO L24 Power/Other InputA30# TS Source Synch Input/Output COMPl Pl Power/Other Input



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Pin Listing and Signal Descriptions i n t e l Pin Name Pin Signal Buffer Type Direction Pin Name Pin Signal Buffer Type DirectionNumber Number00# B21 Source Synch Input/Output 039# N25 Source Synch Input/Output001# B22 Source Synch Input/Output 040# R21 Source Synch Input/Output002# A23 Source Synch Input/Output 041# P24 Source Synch Input/Output003# A25 Source Synch Input/Output 042# R25 Source Synch Input/Output004# C21 Source Synch Input/Output 043# R24 Source Synch Input/Output005# 022 Source Synch Input/Output 044# T26 Source Synch Input/Output006# B24 Source Synch Input/Output 045# T25 Source Synch Input/Output007# C23 Source Synch Input/Output 046# T22 Source Synch Input/Output008# C24 Source Synch Input/Output 047# T23 Source Synch Input/Output009# B25 Source Synch Input/Output 048# U26 Source Synch Input/Output010# G22 Source Synch Input/Output 049# U24 Source Synch Input/Output011# H21 Source Synch Input/Output 050# U23 Source Synch Input/Output012# C26 Source Synch Input/Output 051# V25 Source Synch Input/Output013# 023 Source Synch Input/Output 052# U21 Source Synch Input/Output014# J21 Source Synch Input/Output 053# V22 Source Synch Input/Output015# 025 Source Synch Input/Output 054# V24 Source Synch Input/Output016# H22 Source Synch Input/Output 055# W26 Source Synch Input/Output017# E24 Source Synch Input/Output 056# Y26 Source Synch Input/Output018# G23 Source Synch Input/Output 057# W25 Source Synch Input/Output019# F23 Source Synch Input/Output 058# Y23 Source Synch Input/Output020# F24 Source Synch Input/Output 059# Y24 Source Synch Input/Output021# E25 Source Synch Input/Output 060# Y21 Source Synch Input/Output022# F26 Source Synch Input/Output 061# AA25 Source Synch Input/Output023# 026 Source Synch Input/Output 062# AA22 Source Synch Input/Output024# L21 Source Synch Input/Output 063# AA24 Source Synch Input/Output025# G26 Source Synch Input/Output OBIO# E21 Source Synch Input/Output026# H24 Source Synch Input/Output OBll# G25 Source Synch Input/Output027# M21 Source Synch Input/Output OBI2# P26 Source Synch Input/Output028# L22 Source Synch Input/Output OBI3# V21 Source Synch Input/Output029# J24 Source Synch Input/Output OBR# AE25 Power/Other Output030# K23 Source Synch Input/Output OBSY# H5 Common Clock Input/Output031# H25 Source Synch Input/Output OEFER# E2 Common Clock Input032# M23 Source Synch Input/Output OPO# J26 Common Clock Input/Output033# N22 Source Synch Input/Output OP1# K25 Common Clock Input/Output034# P21 Source Synch Input/Output OP2# K26 Common Clock Input/Output035# M24 Source Synch Input/Output OP3# L25 Common Clock Input/Output036# N23 Source Synch Input/Output OPSLP# A025 Asynch GTL+ Input037# M26 Source Synch Input/Output OROY# H2 Common Clock Input/Output038# N26 Source Synch Input/Output OSTBNO# E22 Source Synch Input/Output

OSTBN1# K22 Source Synch Input/Output

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intel~ Pin Listing and Signal DescriptionsPin Name Pin Signal Buffer Direction Pin Name Pin Signal Buffer DirectionNumber Type Number Type

DSTBN2# R22 Source Synch Input/Output RS2# F4 Common Clock InputDSTBN3# W22 Source Synch Input/Output RSP# AB2 Common Clock InputDSTBPO# F21 Source Synch Input/Output SKTOCC# AF26 Power/Other OutputDSTBP1# J23 Source Synch Input/Output SLP# AB26 Asynch GTL+ InputDSTBP2# P23 Source Synch Input/Output SMI# B5 Asynch GTL+ InputDSTBP3# W23 Source Synch Input/Output STPCLK# Y4 Asynch GTL+ InputFERR#/ B6 Asynch AGL+ Output TCK 04 TAP InputPBE#GTLREF AA21 Power/Other Input TDI Cl TAP InputGTLREF AA6 Power/Other Input TOO 05 TAP OutputGTLREF F20 Power/Other Input TESTHIO AD24 Power/Other InputGTLREF F6 Power/Other Input TESTHll AA2 Power/Other InputHIT# F3 Common Clock Input/Output TESTHll0 Y3 Power/Other InputHITM# E3 Common Clock Input/Output TESTHlll A6 Power/Other InputIERR# AC3 Asynch GTL+ Output TESTHI2 AC21 Power/Other InputIGNNE# B2 Asynch GTL+ Input TESTHI3 AC20 Power/Other InputINIT# W5 Asynch GTL+ Input TESTHI4 AC24 Power/Other InputITP_CLKO AC26 TAP Input TESTHI5 AC23 Power/Other InputITP_CLKl AD26 TAP Input TESTHI6 AA20 Power/Other InputLlNTO 01 Asynch GTL+ Input TESTHI7 AB22 Power/Other InputLlNTl E5 Asynch GTL+ Input TESTHI8 U6 Power/Other InputLOCK# G4 Common Clock Input/Output TESTHI9 W4 Power/Other InputMCERR# V6 Common Clock Input/Output THERMDA B3 Power/OtherOPTIMIZED/ AE26 Power/Other Input THERMDC C4 Power/OtherCOMPAT#PROCHOT# C3 Asynch GTL+ Input/Output THERMTRIP# A2 Asynch GTL+ OutputPWRGOOD AB23 Power/Other Input TMS F7 TAP InputREQO# Jl Source Synch Input/Output TRDY# J6 Common Clock InputREQ1# K5 Source Synch Input/Output TRST# E6 TAP InputREQ2# J4 Source Synch Input/Output VCC Al0 Power/OtherREQ3# J3 Source Synch Input/Output VCC A12 Power/OtherREQ4# H3 Source Synch Input/Output VCC A14 Power/OtherRESERVED A22 VCC A16 Power/OtherRESERVED A7 VCC A18 Power/OtherRESERVED AE21 VCC A20 Power/OtherRESERVED AF24 VCC A8 Power/OtherRESERVED AF25 VCC AA10 Power/OtherRESET# AB25 Common Clock Input VCC AA12 Power/OtherRSO# Fl Common Clock Input VCC AA14 Power/OtherRS1# G5 Common Clock Input VCC AA16 Power/Other



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Pin Listing and Signal Descriptions i n t e l Pin Name Pin Signal Buffer Direction Pin Name Pin Signal Buffer DirectionNumber Type Number Typevee AA18 Power/Other vee AF9 Power/Othervee AA8 Power/Other vee B11 Power/Othervee AB11 Power/Other vee B13 Power/Othervee AB13 Power/Other vee B15 Power/Othervee AB15 Power/Other vee B17 Power/Othervee AB17 Power/Other vee B19 Power/Othervee AB19 Power/Other vee B7 Power/Othervee AB7 Power/Other vee B9 Power/Othervee AB9 Power/Other vee e10 Power/Othervee Ae10 Power/Other vee e12 Power/Othervee Ae12 Power/Other vee e14 Power/Othervee Ae14 Power/Other vee e16 Power/Othervee Ae16 Power/Other vee e18 Power/Othervee Ae18 Power/Other vee e20 Power/Othervee Ae8 Power/Other vee e8 Power/Othervee A011 Power/Other vee 011 Power/Othervee A013 Power/Other vee 013 Power/Othervee A015 Power/Other vee 015 Power/Othervee A017 Power/Other vee 017 Power/Othervee A019 Power/Other vee 019 Power/Othervee A07 Power/Other vee 07 Power/Othervee A09 Power/Other vee 09 Power/Othervee AE10 Power/Other vee E10 Power/Othervee AE12 Power/Other vee E12 Power/Othervee AE14 Power/Other vee E14 Power/Othervee AE16 Power/Other vee E16 Power/Othervee AE18 Power/Other vee E18 Power/Othervee AE20 Power/Other vee E20 Power/Othervee AE6 Power/Other vee E8 Power/Othervee AE8 Power/Other vee F11 Power/Othervee AF11 Power/Other vee F13 Power/Othervee AF13 Power/Other vee F15 Power/Othervee AF15 Power/Other vee F17 Power/Othervee AF17 Power/Other vee F19 Power/Othervee AF19 Power/Other vee F9 Power/Othervee AF2 Power/Other VeeA AE23 Power/Othervee AF21 Power/Other VeelOPLL A020 Power/Othervee AF5 Power/Other VeeSENSE AS Power/Other Outputvee AF7 Power/Other vccvio AF4 Power/Other Input



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intel~ Pin Listing and Signal DescriptionsPin Name Pin Signal Buffer Direction Pin Name Pin Signal Buffer DirectionNumber Type Number Type

VCCVIDLB AF3 Power/Other Input VSS AB8 Power/OtherVIDO AE5 Power/Other Output VSS ACll Power/OtherVIOl AE4 Power/Other Output VSS AC13 Power/OtherVID2 AE3 Power/Other Output VSS AC15 Power/OtherVID3 AE2 Power/Other Output VSS AC17 Power/OtherVID4 AEl Power/Other Output VSS AC19 Power/OtherVID5 AD3 Power/Other Output VSS AC2 Power/OtherVIDPWRGD AD2 Power/Other Input VSS AC22 Power/OtherVSS All Power/Other VSS AC25 Power/OtherVSS A13 Power/Other VSS AC5 Power/OtherVSS A15 Power/Other VSS AC7 Power/OtherVSS A17 Power/Other VSS AC9 Power/OtherVSS A19 Power/Other VSS AD10 Power/OtherVSS A2l Power/Other VSS AD12 Power/OtherVSS A24 Power/Other VSS AD14 Power/OtherVSS A26 Power/Other VSS AD16 Power/OtherVSS A3 Power/Other VSS AD18 Power/OtherVSS A9 Power/Other VSS AD2l Power/OtherVSS AAl Power/Other VSS AD23 Power/OtherVSS AAll Power/Other VSS AD4 Power/OtherVSS AA13 Power/Other VSS AD8 Power/OtherVSS AA15 Power/Other VSS AEll Power/OtherVSS AA17 Power/Other VSS AE13 Power/OtherVSS AA19 Power/Other VSS AE15 Power/OtherVSS AA23 Power/Other VSS AE17 Power/OtherVSS AA26 Power/Other VSS AE19 Power/OtherVSS AA4 Power/Other VSS AE22 Power/OtherVSS AA7 Power/Other VSS AE24 Power/OtherVSS AA9 Power/Other VSS AE7 Power/OtherVSS AB10 Power/Other VSS AE9 Power/OtherVSS AB12 Power/Other VSS AFl Power/OtherVSS AB14 Power/Other VSS AF10 Power/OtherVSS AB16 Power/Other VSS AF12 Power/OtherVSS AB18 Power/Other VSS AF14 Power/OtherVSS AB20 Power/Other VSS AF16 Power/OtherVSS AB2l Power/Other VSS AF18 Power/OtherVSS AB24 Power/Other VSS AF20 Power/OtherVSS AB3 Power/Other VSS AF6 Power/OtherVSS AB6 Power/Other VSS AF8 Power/Other



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Pin Listing and Signal Descriptions i n t e l Pin Name Pin Signal Buffer Type Direction Pin Name Pin Signal Buffer Type DirectionNumber NumberVSS Bl0 Power/Other VSS E26 Power/OtherVSS B12 Power/Other VSS E4 Power/OtherVSS B14 Power/Other VSS E7 Power/OtherVSS B16 Power/Other VSS E9 Power/OtherVSS B18 Power/Other VSS FlO Power/OtherVSS B20 Power/Other VSS F12 Power/OtherVSS B23 Power/Other VSS F14 Power/OtherVSS B26 Power/Other VSS F16 Power/OtherVSS B4 Power/Other VSS F18 Power/OtherVSS B8 Power/Other VSS F2 Power/OtherVSS Cll Power/Other VSS F22 Power/OtherVSS C13 Power/Other VSS F25 Power/OtherVSS C15 Power/Other VSS F5 Power/OtherVSS C17 Power/Other VSS F8 Power/OtherVSS C19 Power/Other VSS G21 Power/OtherVSS C2 Power/Other VSS G24 Power/OtherVSS C22 Power/Other VSS G3 Power/OtherVSS C25 Power/Other VSS G6 Power/OtherVSS C5 Power/Other VSS Hl Power/OtherVSS C7 Power/Other VSS H23 Power/OtherVSS C9 Power/Other VSS H26 Power/OtherVSS 010 Power/Other VSS H4 Power/OtherVSS 012 Power/Other VSS J2 Power/OtherVSS 014 Power/Other VSS J22 Power/OtherVSS 016 Power/Other VSS J25 Power/OtherVSS 018 Power/Other VSS J5 Power/OtherVSS 020 Power/Other VSS K21 Power/OtherVSS 021 Power/Other VSS K24 Power/OtherVSS 024 Power/Other VSS K3 Power/OtherVSS 03 Power/Other VSS K6 Power/OtherVSS 06 Power/Other VSS Ll Power/OtherVSS 08 Power/Other VSS L23 Power/OtherVSS El Power/Other VSS L26 Power/OtherVSS Ell Power/Other VSS L4 Power/OtherVSS E13 Power/Other VSS M2 Power/OtherVSS E15 Power/Other VSS M22 Power/OtherVSS E17 Power/Other VSS M25 Power/OtherVSS E19 Power/Other VSS M5 Power/OtherVSS E23 Power/Other VSS N21 Power/Other



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intel~ Pin Listing and Signal DescriptionsPin Name Pin Signal Buffer DirectionNumber TypeVSS N24 Power/OtherVSS N3 Power/OtherVSS N6 Power/OtherVSS P2 Power/OtherVSS P22 Power/OtherVSS P25 Power/OtherVSS P5 Power/OtherVSS R1 Power/OtherVSS R23 Power/OtherVSS R26 Power/OtherVSS R4 Power/OtherVSS T21 Power/OtherVSS T24 Power/OtherVSS T3 Power/OtherVSS T6 Power/OtherVSS U2 Power/OtherVSS U22 Power/OtherVSS U25 Power/OtherVSS U5 Power/OtherVSS V1 Power/OtherVSS V23 Power/OtherVSS V26 Power/OtherVSS V4 Power/OtherVSS W21 Power/OtherVSS W24 Power/OtherVSS W3 Power/OtherVSS W6 Power/OtherVSS Y2 Power/OtherVSS Y22 Power/OtherVSS Y25 Power/OtherVSS Y5 Power/OtherVSSA AD22 Power/OtherVSSSENSE A4 Power/Other Output



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Pin Listing and Signal Descriptions

Table 4-2. Numerical Pin Assignment(Sheet 1 of 12)

Pin# Pin Name Signal Buffer DirectionType

A2 THERMTRIP# Asynch GTL+ OutputA3 VSS Power/OtherA 4 VSS_SENSE Power/Other OutputA5 VCC_SENSE Power/Other OutputA6 TESTHlll Power/Other InputA7 RESERVEDA8 VCC Power/OtherA9 VSS Power/OtherAl0 VCC Power/OtherAll VSS Power/OtherA12 VCC Power/OtherA13 VSS Power/OtherA14 VCC Power/OtherA15 VSS Power/OtherA16 VCC Power/OtherA17 VSS Power/OtherA18 VCC Power/OtherA19 VSS Power/OtherA20 VCC Power/OtherA21 VSS Power/OtherA22 RESERVEDA23 D2# Source Synch Input/OutputA24 VSS Power/OtherA25 D3# Source Synch Input/OutputA26 VSS Power/OtherB2 IGNNE# Asynch GTL+ InputB3 THERMDA Power/OtherB4 VSS Power/OtherB5 SMI# Asynch GTL+ InputB6 FERR#/PBE# Asynch AGL+ OutputB7 VCC Power/OtherB8 VSS Power/OtherB9 VCC Power/OtherBl0 VSS Power/OtherBll VCC Power/OtherB12 VSS Power/OtherB13 VCC Power/OtherB14 VSS Power/OtherB15 VCC Power/OtherB16 VSS Power/Other

i n t e l Table 4-2. Numerical Pin Assignment

(Sheet 2 of 12)Pin# Pin Name Signal Buffer DirectionType

B17 VCC Power/OtherB18 VSS Power/OtherB19 VCC Power/OtherB20 VSS Power/OtherB21 DO# Source Synch Input/OutputB22 Dl# Source Synch Input/OutputB23 VSS Power/OtherB24 D6# Source Synch Input/OutputB25 D9# Source Synch Input/OutputB26 VSS Power/OtherCl TOI TAP InputC2 VSS Power/OtherC3 PROCHOT# Asynch GTL+ Input/OutputC4 THERMDC Power/OtherC5 VSS Power/OtherC6 A20M# Asynch GTL+ InputC7 VSS Power/OtherC8 VCC Power/OtherC9 VSS Power/OtherCl0 VCC Power/OtherCll VSS Power/OtherC12 VCC Power/OtherC13 VSS Power/OtherC14 VCC Power/OtherC15 VSS Power/OtherC16 VCC Power/OtherC17 VSS Power/OtherC18 VCC Power/OtherC19 VSS Power/OtherC20 VCC Power/OtherC21 D4# Source Synch Input/OutputC22 VSS Power/OtherC23 D7# Source Synch Input/OutputC24 D8# Source Synch Input/OutputC25 VSS Power/OtherC26 D12# Source Synch Input/OutputDl UNTO Asynch GTL+ InputD2 BPRI# Common Clock InputD3 VSS Power/OtherD4 TCK TAP Input

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intel~Table 4-2. Numerical Pin Assignment


05 TOO TAP Output06 VSS Power/Other07 VCC Power/Other08 VSS Power/Other09 VCC Power/Other010 VSS Power/Other011 VCC Power/Other012 VSS Power/Other013 VCC Power/Other014 VSS Power/Other015 VCC Power/Other016 VSS Power/Other017 VCC Power/Other018 VSS Power/Other019 VCC Power/Other020 VSS Power/Other021 VSS Power/Other022 05# Source Synch Input/Output023 013# Source Synch Input/Output024 VSS Power/Other025 015# Source Synch Input/Output026 023# Source Synch Input/OutputEl VSS Power/OtherE2 OEFER# Common Clock InputE3 HITM# Common Clock Input/OutputE4 VSS Power/OtherE5 LlNTl Asynch GTL+ InputE6 TRST# TAP InputE7 VSS Power/OtherE8 VCC Power/OtherE9 VSS Power/OtherEl0 VCC Power/OtherEll VSS Power/OtherE12 VCC Power/OtherE13 VSS Power/OtherE14 VCC Power/OtherE15 VSS Power/OtherE16 VCC Power/OtherE17 VSS Power/OtherE18 VCC Power/Other




E19 VSS Power/OtherE20 VCC Power/OtherE21 OBIO# Source Synch Input/OutputE22 OSTBNO# Source Synch Input/OutputE23 VSS Power/OtherE24 017# Source Synch Input/OutputE25 021# Source Synch Input/OutputE26 VSS Power/OtherFl RSO# Common Clock InputF2 VSS Power/OtherF3 HIT# Common Clock Input/OutputF4 RS2# Common Clock InputF5 VSS Power/OtherF6 GTLREF Power/Other InputF7 TMS TAP InputF8 VSS Power/OtherF9 VCC Power/OtherFlO VSS Power/OtherFll VCC Power/OtherF12 VSS Power/OtherF13 VCC Power/OtherF14 VSS Power/OtherF15 VCC Power/OtherF16 VSS Power/OtherF17 VCC Power/OtherF18 VSS Power/OtherF19 VCC Power/OtherF20 GTLREF Power/Other InputF21 OSTBPO# Source Synch Input/OutputF22 VSS Power/OtherF23 019# Source Synch Input/OutputF24 020# Source Synch Input/OutputF25 VSS Power/OtherF26 022# Source Synch Input/OutputGl AOS# Common Clock Input/OutputG2 BNR# Common Clock Input/OutputG3 VSS Power/OtherG4 LOCK# Common Clock Input/OutputG5 RS1# Common Clock InputG6 VSS Power/Other

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Pin# Pin Name Signal Buffer DirectionTypeG21 VSS Power/OtherG22 010# Source Synch Input/OutputG23 018# Source Synch Input/OutputG24 VSS Power/OtherG25 OBI1# Source Synch Input/OutputG26 025# Source Synch Input/OutputH1 VSS Power/OtherH2 OROY# Common Clock Input/OutputH3 REQ4# Source Synch Input/OutputH4 VSS Power/OtherH5 OBSY# Common Clock Input/OutputH6 BRO# Common Clock Input/OutputH21 011# Source Synch Input/OutputH22 016# Source Synch Input/OutputH23 VSS Power/OtherH24 026# Source Synch Input/OutputH25 031# Source Synch Input/OutputH26 VSS Power/OtherJ1 REQO# Source Synch Input/OutputJ2 VSS Power/OtherJ3 REQ3# Source Synch Input/OutputJ4 REQ2# Source Synch Input/OutputJ5 VSS Power/OtherJ6 TROY# Common Clock InputJ21 014# Source Synch Input/OutputJ22 VSS Power/OtherJ23 OSTBP1# Source Synch Input/OutputJ24 029# Source Synch Input/OutputJ25 VSS Power/OtherJ26 OPO# Common Clock Input/OutputK1 A6# Source Synch Input/OutputK2 A3# Source Synch Input/OutputK3 VSS Power/OtherK4 A4# Source Synch Input/OutputK5 REQ1# Source Synch Input/OutputK6 VSS Power/OtherK21 VSS Power/OtherK22 OSTBN1# Source Synch Input/OutputK23 030# Source Synch Input/OutputK24 VSS Power/Other


(Sheet 6 of 12)Pin# Pin Name Signal Buffer DirectionTypeK25 OP1# Common Clock Input/OutputK26 OP2# Common Clock Input/OutputL1 VSS Power/OtherL2 A9# Source Synch Input/OutputL3 A7# Source Synch Input/OutputL4 VSS Power/OtherL5 AOSTBO# Source Synch Input/OutputL6 A5# Source Synch Input/OutputL21 024# Source Synch Input/OutputL22 028# Source Synch Input/OutputL23 VSS Power/OtherL24 COMPO Power/Other InputL25 OP3# Common Clock Input/OutputL26 VSS Power/OtherM1 A13# Source Synch Input/OutputM2 VSS Power/OtherM3 A10# Source Synch Input/OutputM4 A11# Source Synch Input/OutputM5 VSS Power/OtherM6 A8# Source Synch Input/OutputM21 027# Source Synch Input/OutputM22 VSS Power/OtherM23 032# Source Synch Input/OutputM24 035# Source Synch Input/OutputM25 VSS Power/OtherM26 037# Source Synch Input/OutputN1 A12# Source Synch Input/OutputN2 A14# Source Synch Input/OutputN3 VSS Power/OtherN4 A15# Source Synch Input/OutputN5 A16# Source Synch Input/OutputN6 VSS Power/OtherN21 VSS Power/OtherN22 033# Source Synch Input/OutputN23 036# Source Synch Input/OutputN24 VSS Power/OtherN25 039# Source Synch Input/OutputN26 038# Source Synch Input/OutputP1 COMP1 Power/Other InputP2 VSS Power/Other

44 Mobile IntelPentium 4 Processor supporting Hyper-ThreadingTechnology on 90-nmprocess technology Datasheet


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(Sheet 7 of 12)Pin# Pin Name Signal Buffer DirectionTypeP3 A19# Source Synch Input/OutputP4 A20# Source Synch Input/OutputP5 VSS Power/OtherP6 A24# Source Synch Input/OutputP21 034# Source Synch Input/OutputP22 VSS Power/OtherP23 OSTBP#2 Source Synch Input/OutputP24 041# Source Synch Input/OutputP25 VSS Power/OtherP26 OBI2# Source Synch Input/OutputR1 VSS Power/OtherR2 A18# Source Synch Input/OutputR3 A21# Source Synch Input/OutputR4 VSS Power/OtherR5 AOSTB1# Source Synch Input/OutputR6 A28# Source Synch Input/OutputR21 040# Source Synch Input/OutputR22 OSTBN#2 Source Synch Input/OutputR23 VSS Power/OtherR24 043# Source Synch Input/OutputR25 042# Source Synch Input/OutputR26 VSS Power/OtherT1 A17# Source Synch Input/OutputT2 A22# Source Synch Input/OutputT3 VSS Power/OtherT4 A26# Source Synch Input/OutputT5 A30# Source Synch Input/OutputT6 VSS Power/OtherT21 VSS Power/OtherT22 046# Source Synch Input/OutputT23 047# Source Synch Input/OutputT24 VSS Power/OtherT25 045# Source Synch Input/OutputT26 044# Source Synch Input/OutputU1 A23# Source Synch Input/OutputU2 VSS Power/OtherU3 A25# Source Synch Input/OutputU4 A31# Source Synch Input/OutputU5 VSS Power/OtherU6 TESTHI8 Power/Other Input



Pin# Pin Name Signal Buffer DirectionTypeU21 052# Source Synch Input/OutputU22 VSS Power/OtherU23 050# Source Synch Input/OutputU24 049# Source Synch Input/OutputU25 VSS Power/OtherU26 048# Source Synch Input/OutputV1 VSS Power/OtherV2 A27# Source Synch Input/OutputV3 A32# Source Synch Input/OutputV4 VSS Power/OtherV5 AP1# Common Clock Input/OutputV6 MCERR# Common Clock Input/OutputV21 OBI3# Source Synch Input/OutputV22 053# Source Synch Input/OutputV23 VSS Power/OtherV24 054# Source Synch Input/OutputV25 051# Source Synch Input/OutputV26 VSS Power/OtherW1 A29# Source Synch Input/OutputW2 A33# Source Synch Input/OutputW3 VSS Power/OtherW4 TESTHI9 Power/Other InputW5 INIT# Asynch GTL+ InputW6 VSS Power/OtherW21 VSS Power/OtherW22 OSTBN3# Source Synch Input/OutputW23 OSTBP3# Source Synch Input/OutputW24 VSS Power/OtherW25 057# Source Synch Input/OutputW26 055# Source Synch Input/OutputY1 A34# Source Synch Input/OutputY2 VSS Power/OtherY3 TESTHl10 Power/Other InputY4 STPCLK# Asynch GTL+ InputY5 VSS Power/OtherY6 BPM3# Common Clock Input/OutputY21 060# Source Synch Input/OutputY22 VSS Power/OtherY23 058# Source Synch Input/OutputY24 059# Source Synch Input/Output



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Y25 VSS Power/OtherY26 056# Source Synch Input/OutputAA1 VSS Power/OtherAA2 TESTHl1 Power/Other InputAA3 BINIT# Common Clock Input/OutputAA4 VSS Power/OtherAA5 BPM4# Common Clock Input/OutputAA6 GTLREF Power/Other InputAA7 VSS Power/OtherAA8 VCC Power/OtherAA9 VSS Power/OtherAA10 VCC Power/OtherAA11 VSS Power/OtherAA12 VCC Power/OtherAA13 VSS Power/OtherAA14 VCC Power/OtherAA15 VSS Power/OtherAA16 VCC Power/OtherAA17 VSS Power/OtherAA18 VCC Power/OtherAA19 VSS Power/OtherAA20 TESTHI6 Power/Other InputAA21 GTLREF Power/Other InputAA22 062# Source Synch Input/OutputAA23 VSS Power/OtherAA24 063# Source Synch Input/OutputAA25 061# Source Synch Input/OutputAA26 VSS Power/OtherAB1 A35# Source Synch Input/OutputAB2 RSP# Common Clock InputAB3 VSS Power/OtherAB4 BPM5# Common Clock Input/OutputAB5 BPM1# Common Clock Input/OutputAB6 VSS Power/OtherAB7 VCC Power/OtherAB8 VSS Power/OtherAB9 VCC Power/OtherAB10 VSS Power/OtherAB11 VCC Power/OtherAB12 VSS Power/Other



AB13 VCC Power/OtherAB14 VSS Power/OtherAB15 VCC Power/OtherAB16 VSS Power/OtherAB17 VCC Power/OtherAB18 VSS Power/OtherAB19 VCC Power/OtherAB20 VSS Power/OtherAB21 VSS Power/OtherAB22 TESTHI7 Power/Other InputAB23 PWRGOOO Power/Other InputAB24 VSS Power/OtherAB25 RESET# Common Clock InputAB26 SLP# Asynch GTL+ InputAC1 APO# Common Clock Input/OutputAC2 VSS Power/OtherAC3 IERR# Asynch GTL+ OutputAC4 BPM2# Common Clock Input/OutputAC5 VSS Power/OtherAC6 BPMO# Common Clock Input/OutputAC7 VSS Power/OtherAC8 VCC Power/OtherAC9 VSS Power/OtherAC10 VCC Power/OtherAC11 VSS Power/OtherAC12 VCC Power/OtherAC13 VSS Power/OtherAC14 VCC Power/OtherAC15 VSS Power/OtherAC16 VCC Power/OtherAC17 VSS Power/OtherAC18 VCC Power/OtherAC19 VSS Power/OtherAC20 TESTHI3 Power/Other InputAC21 TESTHI2 Power/Other InputAC22 VSS Power/OtherAC23 TESTHI5 Power/Other InputAC24 TESTHI4 Power/Other InputAC25 VSS Power/OtherAC26 ITP_CLKO TAP Input

46 Mobile IntelPentium4 Processor supporting Hyper-ThreadingTechnologyon 90-nmprocesstechnology Datasheet


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ADl BOOTSELEeT Power/Other InputAD2 VIDPWRGD Power/Other InputAD3 VID5 Power/Other OutputAD4 VSS Power/OtherAD5 BSELl Power/Other OutputAD6 BSELO Power/Other OutputAD7 vee Power/OtherAD8 VSS Power/OtherAD9 vee Power/OtherAD10 VSS Power/OtherADll vee Power/OtherAD12 VSS Power/OtherAD13 vee Power/OtherAD14 VSS Power/OtherAD15 vee Power/OtherAD16 VSS Power/OtherAD17 vee Power/OtherAD18 VSS Power/OtherAD19 vee Power/OtherAD20 VeelOPLL Power/OtherAD2l VSS Power/OtherAD22 VSSA Power/OtherAD23 VSS Power/OtherAD24 TESTHIO Power/Other InputAD25 DPSLP# Asynch GTL+ InputAD26 ITP_eLKl TAP InputAEl VID4 Power/Other OutputAE2 VID3 Power/Other OutputAE3 VID2 Power/Other OutputAE4 VIDl Power/Other OutputAE5 VIDO Power/Other OutputAE6 vee Power/OtherAE7 VSS Power/OtherAE8 vee Power/OtherAE9 VSS Power/OtherAE10 vee Power/OtherAEll VSS Power/OtherAE12 vee Power/OtherAE13 VSS Power/OtherAE14 vee Power/Other




AE15 VSS Power/OtherAE16 vee Power/OtherAE17 VSS Power/OtherAE18 vee Power/OtherAE19 VSS Power/OtherAE20 vee Power/OtherAE2l RESERVEDAE22 VSS Power/OtherAE23 VeeA Power/OtherAE24 VSS Power/OtherAE25 DBR# Power/Other OutputAE26 OPTIMIZED/ Power/Other InputeOMPAT#AFl VSS Power/OtherAF2 vee Power/OtherAF3 VeeVIDLB Power/Other InputAF4 VeeVID Power/Other InputAF5 vee Power/OtherAF6 VSS Power/OtherAF7 vee Power/OtherAF8 VSS Power/OtherAF9 vee Power/OtherAF10 VSS Power/OtherAFll vee Power/OtherAF12 VSS Power/OtherAF13 vee Power/OtherAF14 VSS Power/OtherAF15 vee Power/OtherAF16 VSS Power/OtherAF17 vee Power/OtherAF18 VSS Power/OtherAF19 vee Power/OtherAF20 VSS Power/Other

AF2l vee Power/OtherAF22 BeLKO Bus Clock InputAF23 BeLKl Bus Clock InputAF24 RESERVEDAF25 RESERVEDAF26 SKTOee# Power/Other Output



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Pin Listing and Signal Descriptions i n t e l Figure 4-1. Pinout Diagram (Top View-Left Side)

26 25 24 23 22 21 20 19 18 167 15

AF skroccs Reserved Reserved BelK1 BelKO vee VSS vee VSS vee VSS vee VSSOPTIMIZED/ OBR# VSS veeA VSS Reserved vee VSS vee VSS vee VSS veeeOMPAT#I TP_ el K1 O PS lP # TESTHIO VSS VSSA VSS vccio=u. vee VSS vee VSS vee VSSIT P_e lK O VSS TESTHI4 TESTHI5 VSS TESTHI2 TESTHI3 VSS vee VSS vee VSS vee

SlP# RESET# VS S PW R TESTHI7 VSS VSS

mobile pentium 4 hyper threading 90nm process technology datasheet

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