– 1 – data convertersflash adcprofessor y. chiu eect 7327fall 2014 flash adc

– 1 –

Data Converters Flash ADCProfessor Y. Chiu

EECT 7327Fall 2014

Flash ADC

Flash ADC Architecture

– 2 –


EECT 7327Fall 2014

• Reference ladder

consists of 2N equal

size resistors

• Input is compared

to 2N-1 reference

voltages

• Massive parallelism

• Very fast ADC

architecture

• Throughput = fs

• Latency = 1 T = 1/fs

• Complexity = 2N

… …

Enc

oder

VFS Vi

fs

Strobe

Dout

2N-1comparators

…

Do 0

Vi

Δ

2Δ

5Δ

6Δ

7Δ

VFS

……

0

1

5

6

7

Thermometer Code

– 3 –


EECT 7327Fall 2014

1

1

0

1

b2 b1 b0

001

010

110

111

000

ROM encoder

… … ……… …

VFS Vi

fs

Strobe

2N-1comparators

…

1

1

1

0

Thermometer code

1-of-n code

Flash ADC Challenges

– 4 –


EECT 7327Fall 2014

• VDD = 1.8 V

• 10-bit

• VFS = 1 V

• DNL < 0.5 LSB

• 0.5 mV = 3-5 σ

→ 1023 comparators

→ 1 LSB = 1 mV

→ Vos < 0.5 LSB

→ σ = 0.1-0.2 mV

• 2N-1 very large comparators• Large area, large power consumption• Very sensitive design• Limited to resolutions of 4-8 bits

1V

1mV

σ

Flash ADC Challenges

– 5 –


EECT 7327Fall 2014

4 6 8 10

2

8

32

128

N [bits]

Vos

, max

[mV

]

VFS = 1V

VFS = 2V

0.5

• DNL < 0.5 LSB

• Large VFS relaxes

offset tolerance

• Small VFS benefits

conversion speed

(settling, linearity of

building blocks)

A Typical CMOS Comparator

– 6 –


EECT 7327Fall 2014

Vos derives from:

• Preamp input pair

mismatch (Vth,W,L)

• PMOS loads and

current mirror

• Latch mismatch

• CI / CF imbalance

of M9

• Clock routing

• Parasitics

M1 M2

Vi

Vos

M3 M4

VDD

M5 M6

M8M7

M9

VSS

Φ

Vo+ Vo

-

Preamp Latch

Latch Regeneration

– 7 –


EECT 7327Fall 2014

Exponential regeneration due to positive feedback of M7 and M8

VDD

VSS

Vo

Φ PA tracking Latch reseting

Latchregenrating

Vo+

Vo-

VDD

M5 M6

M8M7

M9

VSS

ΦVo

+ Vo-

CL CL

Regeneration Speed – Linear Model

– 8 –


EECT 7327Fall 2014

Lmoo /Cgtexp0tV0tV

pole RHP single ,/Cgs01/sCgsΔ LmpLm

M8M7

CL CL

Vo+ Vo

-

0V

V

/sCg1

11

/sCVgV

VV

o

o

LmLomo

oo

Vo-

Vo+

CL gmVo-

-1

Reg. Speed – Linear Model

– 9 –


EECT 7327Fall 2014

0tV

tVln

g

Ct

o

o

m

L

M8M7

CL CL

Vo+ Vo

-

Vo = 1VVo(t=0)

t

Vo Vo(t=0) t/(CL/gm)

1V 100mV 2.3

1V 10mV 4.6

1V 1mV 6.9

1V 100μV 9.2

Reg. Speed – Linear Model

– 10 –


EECT 7327Fall 2014

amplifier. be to g

1

2

R,

Rg2

RgA

m7

9

9m7

9m5V2

M5 M6

M8M7

M9

Φ=1Vo

+ Vo-

Vm+ Vm

-

M1 M2

Vi

M3 M4

Vm+ Vm

-

Vo+ Vo

-R9

2R9

2

-1gm7

-1gm7

gm5Vm+ gm5Vm

-

X

m3

m1V1 g

gA

V2V1iVio AA0VA0V0V

LmV2V1io /CgtexpAA0VtV

x

Comparator Metastability

– 11 –


EECT 7327Fall 2014

Comparator fails to produce valid logic outputs within T/2 when input falls into a region that is sufficiently close to the comparator threshold


Curve AV1AV2 Vi(t=0)

10 10 mV

10 1 mV

10 100 μV

10 10 μV

Vo+

Φ

Vo-

1 2 3 4

T/2


– 12 –


EECT 7327Fall 2014

• Cascade preamp stages (typical flash comparator has 2-3 PA stages)• Use pipelined multi-stage latches; PA can be pipelined too• Avoid branching off comparator logic outputs

LSB1

ΔBER


Vi

DoΔ

j

Vos

j+1 Assuming that the input is uniformly distributed over VFS, then


– 13 –


EECT 7327Fall 2014

Vi

1

x

0

0

0

1 1 1

011

100

Logic levels can be misinterpreted by digital gates (branching off, diff. outputs)

– even a wrong decision is better than no decision!

CI and CF in Latch

– 14 –


EECT 7327Fall 2014

M5 M6

M8M7

Φ

Vo+ Vo

-

CL CLM9

CgdCgs

Vo+

Vo-

Φ

CM jump

• Charge injection and clock feedthrough introduce CM jump in Vo+ and Vo

-

• Dynamic latches are more susceptible to CI and CF errors

Dynamic Offset of Latch

– 15 –


EECT 7327Fall 2014

Dynamic offset derives from:

• Imbalanced CI and CF

• Imbalanced load capacitance

• Mismatch b/t M7 and M8

• Mismatch b/t M5 and M6

• Clock routing

Φ

Vo+

Vo-

offset50mV imbalance 10%

jump CM0.5V

Dynamic offset is usually the dominant offset error in latches

Typical CMOS Comparator

– 16 –


EECT 7327Fall 2014

• Input-referred latch

offset gets divided by

the gain of PA

• Preamp introduces

its own offset (mostly

static due to Vth, W,

and L mismatches)

• PA also reduces

kickback noise

M1 M2

Vi

Vos

M3 M4

VDD

M5 M6

M8M7

M9

VSS

Φ

Vo+ Vo

-

Preamp Latch

Kickback noise disturbs reference voltages, must settle before next sample

Comparator Offset

– 17 –


EECT 7327Fall 2014

M1 M2

Vi

Vos

M3 M4

VDD

M5 M6

M8M7

M9

VSS

Φ

Vo+ Vo

-

Preamp Latch

222

ov2

th2

os L

ΔL

W

ΔWV

4

1ΔVV

9m7

9m5V2 Rg2

RgA

m3

m1V1 g

gA

2V2

2V1

2dynos,

2V2

2V1

2os,78

2V1

2os,56

2os,342

os,122

osAA

V

AA

V

A

VVVV

Differential pair mismatch:

Total input-referredcomparator offset:

Matching Properties

– 18 –


EECT 7327Fall 2014

,DSWL

AΔPσ 22

P

2P2

Suppose parameter P of two rectangular devices has a mismatch error of ΔP. The variance of parameter ΔP b/t the two devices is

where, W and L are the effective width and length, D is the distance

Ref: M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989.

22 2 2Vth

th Vth

22β 2 2

β2

AThreshold : σ V = +S D

WLAσ β

Current factor : S Dβ WL

1st term dominatesfor small devices

Why Large Devices Match Better?

– 19 –


EECT 7327Fall 2014

1 S R1

LR R with std σ

W

X X X X X X X X…W

L10 identical resistors

R1 R2

R2 R1 R1 R

2 1 1

σ 10σ σ σ1 1 1

R 10R R R10 A WL

j

2 S 1 R2

102 2 2

R2 R R1 R2 R1j 1

LR R 10 10R with std σ ,

W

σ σ 10σ σ 10σ

“Spatialaveraging”

ADC Input Capacitance

– 20 –


EECT 7327Fall 2014

2

2 2Vthth g

Aσ V C 10 fF /

WLμm

• N = 6 bits

• VFS = 1 V

• σ = LSB/4

• AVT0 = 10 mV·μm

→ 63 comparators

→ 1 LSB = 16 mV

→ σ = 4 mV

→ L = 0.24 μm,

W = 26 μm

N (bits) # of comp. Cin (pF)

6 63 3.9

8 255 250

10 1023 ??!

• Small Vos leads to large device sizes, hence large area and power

• Large comparator leads to large input capacitance, difficult to drive and difficult to maintain tracking bandwidth

– 21 –


EECT 7327Fall 2014

Flash ADC Errors

Distributed Parallel Processing

– 22 –


EECT 7327Fall 2014

… …

Enc

oder

VFS Vi

Dout

2N-1PA + Latch

…

Do 0

Vi

Δ

2Δ

5Δ

6Δ

7Δ

VFS

……

0

1

5

6

7

…

fs

Strobe• SHA-less

• Signal and clock propa-gation delay

• 2N-1 PAs + latches must be matched

• Synchronized strobe signal is critical

Going parallel is fast, but also gives rise to inherent problems…

Preamp Input Common Mode

– 23 –


EECT 7327Fall 2014

Vi

…

VR1 VR

j

PA 1

S1

PA j

Sj

PA j+1

… …

……

Input CM difference creates systematic mismatch (offset, gain, Cin, tracking BW, and CMRR) among preamps

jR

1R VV

Sampling Aperture Error

– 24 –


EECT 7327Fall 2014

• Preamp delay and Vth of sampling switch (M9) are both signal-dependent → signal-dependent sampling point (aperture error)

• A major challenge of distributing clock signals across 2N-1 comparators in flash ADC with minimum clock skew (routing, Vth mismatch of M9, etc.)

M1 M2

Vin

M3 M4

Cgs1 Cgs2

CS

VR

RS

M5 M6

M8M7

M9

Φ

Vo+ Vo

-

Cgd1 Cgd2 Φ Mode

“high” Track

“low” Regen

Nonlinear Input Capacitance

– 25 –


EECT 7327Fall 2014

Vin Cin(Vout)

RS

Vout

t

Vin,Vout

Signal-dependent input bandwidth (1/RSCin) introduces distortion

Input Signal Feedthrough

– 26 –


EECT 7327Fall 2014

Feedthrough of Vin to the reference ladder through the serial connection of Cgs1 and Cgs2 disturbs the reference voltages

……

Vi

M1 M2

Vin

M3 M4

Cgs1 Cgs2

VRj

RS

Fully-Differential Architecture

– 27 –


EECT 7327Fall 2014

• VFS doubled

• 3-dB gain in SNR

• Better CMRR

• Noise immunity

• Input feedthrough cancelled

• Cin nonlinearity partially removed

• Effect of Vcmi diff. mitigated

…… … …

Enc

oder

…

VR+ VR

- Vi+ Vi

-

PA Latch

Dout… … …

Fully-Differential Comparator

– 28 –


EECT 7327Fall 2014

• Double-balanced, fully-differential preamp• Switches (M7, M8) added to stop input propagation during regeneration• Active pull-up PMOS added to the latch

M1 M2

Vi+

M5 M6

M9

Φ

Vo+ Vo

-

Fully-diff. PA Latch

M3 M4

Vi-VR

+ VR-

M7 M8 Φ

AC-Coupled Preamp

– 29 –


EECT 7327Fall 2014

• PA input node X sees constant bias throughout all preamps• Autozeroing eliminates PA offsets (stored in C)

Ref: A. G. F. Dingwall, “Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter,” IEEE Journal of Solid-State Circuits, vol. 14, pp. 926-932, issue 6, 1979.

PA

Vi

CΦ

Φ

Φ

VR LatchX

Bubbles (Sparkles)

– 30 –


EECT 7327Fall 2014

Vi

0

0

1

……

1

1

0

1 1 0

011

100

0010

Static/dynamic comparator errors cause bubbles in thermometer code

Bubbles (Sparkles)

– 31 –


EECT 7327Fall 2014

j+1…

…

Vi

j

0

1

0

1

VRj

VRj+1

t

Vj

Vj+1

VRj

VRj+1

Δt

1 LSB

Comparator offset Timing error

Bubble-Tolerant Boundary Detector

– 32 –


EECT 7327Fall 2014

Vi

1

0

1

0

1

1

……

1

0

1

1

Ref: J. G. Peterson, “A monolithic video A/D converter,” IEEE Journal of Solid-State Circuits, vol. 14, pp. 932-937, issue 6, 1979.

• 3-input NAND

• Detect “011” instead of “01” only

• “Single” bubble correction

• Biased correction

Built-In Bias

– 33 –


EECT 7327Fall 2014

0000101111

0000011011

0010011111

0001100111

A CB D

123

Case“011”Det.

“001”Det.

A B Fail C Fail

D Fail Fail

Inspecting more neighboring comparator outputs improves performance

Majority Voting

– 34 –


EECT 7327Fall 2014

Ref: C. W. Mangelsdorf, “A 400-MHz input flash converter with error correction,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 184-191, issue 1, 1990.

0000011111

0000011111

0000011111

0001100111

Case“011”Det.

Majorityvoting

A B Fail C D Fail Fail

0000101111

0000011011

0010011111

0001100111

A CB D

123

1j1j1jjj1j*

j CCCCCCC

Gray Encoding

– 35 –


EECT 7327Fall 2014

43

622

75311

TG

TTG

TTTTG

00111111

00001111

00000001

01100110

01111111

00000111

00001111

00011111

00000011

00111100

01010101

00001111

00110011

Thermometer Gray Binary

G3 G2 G1 B3 B2 B1T1 T2 T3 T4 T5 T6 T7

• One comparator output is ONLY used once → No branching!• Gray encoding fails benignly in the presence of bubbles• Codes are also robust over metastability errors

Only one transitionb/t adjacent codes

Gray Encoding

– 36 –


EECT 7327Fall 2014

Conversion of Gray code to binary code is quite time-consuming → “quasi” Gray code

43

622

75311

TG

TTG

TTTTG

001

101

111

100

111

010

000

100

131512

Thermometer Gray Decimal

111

111

111

111

111

111

111

111

111

111

111

Ref: Y. Akazawa, et al., “A 400MSPS 8b flash AD conversion LSI,” in IEEE International Solid-State Circuits Conference, Dig. Tech. Papers, 1987, pp. 98-99.

– 1 – data convertersflash adcprofessor y. chiu eect 7327fall 2014 flash adc

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