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Design of CMOS Comparators for FLASH ADCF F

International Journal of Aerospace and Electronics Systems, Vol. 1, No. 1-2, Jan-Dec 2011 47

Design of CMOS Comparators forFLASH ADC

M. MadhavilathaECE Deptt., Jawaharlal Nehru Technological University, Hyderabad,A.P, India, E-mail: [email protected].

G.L. MadhumatiECM Deptt., PVPSIT, Kanuru, Vijayawada, JNTU, Hyderabad,A.P, India, E-mail: [email protected].

K. Rama Koteswara RaoECE Deptt., DVRDHS & MIC, Kanchikacherla, JNTU, Hyderabad,A.P, India, E-mail: [email protected].

ABSTRACT: The analog to digital converters is the key componentsin modern electronic systems. As the digital signal processingindustry grows the ADC design becomes more and morechallenging for researchers. In these days an ADC becomes apart of the system on chip instead of standalone circuit for dataconverters. This increases the requirements on ADC designconcerning for example speed, power, area, resolution, noise etc.New techniques and methods are going to develop day by day toachieve high performance ADCs. Of all types of ADCs the flashADC is not only famous for its data conversion rate but also itbecomes the part of other types of ADC for example pipeline andmulti bit Sigma Delta ADCs. The main problem with a flashADC is its power consumption, which increases in number ofbits. The performance limiting blocks in such ADCs are typicallycomparators. This paper presents the comparison of powerconsumption of different comparators used in flash ADCs withCMOS technology. The layout comparisons are also done.

Keywords: Analog-to-digital converter (ADC), comparators, lowpower, high speed, low area, CMOS Technology.

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M. Madhavilatha, G.L. Madhumati and K. Rama Koteswara RaoF F

48 International Journal of Aerospace and Electronics Systems, Vol. 1, No. 1-2, Jan-Dec 2011

1. INTRODUCTIONIn today’s world, where demand for portable battery operateddevices is increasing, a major thrust is given towards low powermethodologies for high resolution and high-speed applications. Thisreduction in power can be achieved by moving towards smallerfeature size processes. One application where low power, highresolution and high speed are required is Analog-to-Digital Converters(ADCs) for mobile and portable devices. The performance limitingblocks in such ADCs are typically inter-stage gain amplifiers andcomparators. In the literature major emphasis has been made to theinter-stage gain amplifiers but very little effort has been madetowards the design of comparators. The accuracy of such compa-rators, which is defined by its offset, along with power consumptionis of keen interest in achieving overall higher performance of ADCs.In the past, pre-amplifier based comparators have been used forADC architectures such as flash and pipeline. The main drawbackof pre-amplifier based comparators is the high constant powerconsumption. To overcome this problem, dynamic comparators areoften used that make a comparison once every clock period andrequire much less power as compared to the pre-amplifier basedcomparators. Compared to the pre-amplifier based comparatorshowever, these dynamic comparators suffer from large offsetsmaking them less favorable in flash based ADC architectures.In pipeline ADCs, digital correction techniques along with adequateover-range protection can tolerate such large offsets.

The rest of the paper is organized as follows: Section 2 describesthe design of the Flash ADC and its various components. Section 3discusses the various types of comparators. Section 4 discusses thesimulation results.

2. ANALOG TO DIGITAL CONVERTERAnalog to digital converters are the basic building blocks thatprovide an interface between an analog world which accepts ananalog value (voltage/current) and converts it into digital form thatcan be processed by a microprocessor. As it is the main block in



mixed signal Applications, it becomes a bottleneck in data processingapplications and limits the performance of the over all system.Different architecture of ADCs include Flash, Sigma-Delta, Pipeline,Successive Approximation and Dual Slope ADCs.

2.1. Design of the Flash ADCFlash ADC’s have parallel architecture and is the fastest ADC [5]among all the other types and are suitable for high bandwidthapplications.

A typical flash ADC block diagram is shown in Figure 1 and itcan be seen that 2N – 1 comparators are required for an “N” bitconverter. The resistor ladder network is formed by 2N resistors,which generates reference voltages for the comparators. The referencevoltage for each comparator is one least significant bit (LSB) lessthan the reference voltage for the comparator immediately aboveit. When the input voltage is higher than the reference voltage ofcomparator it will generate a “1”, otherwise, the comparator outputis “0”.

Figure 1: Block Diagram of Flash ADC.



Figure 2: Resistor Ladder.

The comparators will generate a thermometer code of an inputsignal. This thermometer code will then decode into a binary formby thermometer-to-binary decoder. “The comparators are typicallya cascade of wideband and low gain stages. They are low gainbecause at high frequencies it’s difficult to obtain both wide band-width and high gain. They are designed for low voltage offset, suchthat the input offset of each comparator is smaller than a LSB of theADC. Otherwise, the comparator’s offset could falsely trip thecomparator, resulting in a digital output code not representative ofa thermometer code. A regenerative latch at each comparator outputstores the result. The latch has positive feedback, so that the endstate is forced to either a “1” or a “0”.

2.2. Components of Flash ADCIn flash ADC an array of comparators compares the input voltagewith a set of increasing reference voltages. All flash ADCs comprisesof following three blocks:

1. Resistor Ladder Block.2. Comparator Block.3. Decoder Block.The next section deals with each block.



2.2.1. Resistor LadderResistor ladder is used to generate the reference voltages for thecomparators. It is assumed that the feed through at nodes ref-lowand ref-high is negligible due to proper decoupling. Maximum feedthrough will occur on the mid node.

2.2.2. ComparatorA comparator is used to detect whether a signal is greater or smallerthan reference signal. Various comparator include multiple stagecomparators, Regenerative Comparators (positive feedback),Resistive Driving Comparators and fully differential Dynamiccomparators.

Dynamic latch comparator can solve the power problem byremoving the pre-amplifying stage, while achieving a smaller area.Although latch comparators typically have a high offset voltage inthe range of 100mV, their fast speed and low power make themsuitable for several applications.

2.2.3. DecoderThe Digital decoder is required to transform the thermometer outputcode from the comparator block output to binary code. There aremany techniques to design a decoder, which convert thermometercode into binary for example ROM decoder, Wallace Tree decoder,FAT tree decoder, multiplexer decoder, etc.

3. COMPARATORS AND ITS TYPESA comparator is a differential amplifier with no feedback loop,whose function is to compare the analog signals presented at itsinputs. Depending on the polarity of the differential input the logicoutput is produced. As it is the case with several types of ADCs,usually one of the comparator’s input is connected to a constantpotential or reference. The circuit symbol and ideal transfer functionof a comparator is shown in Figure 3. It can be seen that if the voltagedifference Vin

+ – Vin– is positive the comparator’s output will go high

(VOH), otherwise its output will go low (VOL).



3.1. Performance MetricsDue to fabrication limits and process variations, the comparatorperformance is affected by non-ideal effects. As a result, the responsedeviates from the ideal one. The main parameters that characterizethe performance of comparators are

Static Parameters: The static parameters describes the perfor-mance of a comparator under DC or steady-state conditions. Themain parameters are resolution, gain, offset, noise, and ICMR.

Resolution is the minimum input difference that can be resolvedby the comparator in order to switch between its binary states. Whenemployed in ADCs, the resolution specification must be equal orlower than the least-significant-bit (LSB) defined by the converter.

The gain, Av, is one of the key limiting factors in achieving thedesired resolution for the comparator.

Offset is defined as the minimum amount of input voltagerequired for the binary-state transition to take place. In a real compa-rator the offset adds to the minimum voltage for which the resolutionwas designed reducing the resolution of the circuit.

Noise has great influence on the operation of the comparator,thus affects the performance of an ADC. The effect of noise in thecircuit’s response can be seen as uncertainty in the time when thecomparator’s output switches between its two states.

Input common-mode range (ICMR) is the permissible voltagerange over which the input common-mode signal can vary whileall transistors remain biased in the saturation region.

(a) (b)

Figure 3: Comparator (a) Circuit Symbol (b) Ideal transfer function



Dynamic Parameters: Three of the most important dynamicparameters that determine the speed of a comparator are

Propagation Delay is the time that elapses between an inputtransition and the corresponding output change. It is usuallymeasured at the midpoints between the input and output signals.

Settling Time is defined as the time needed for the output to besettled within a specified percent of its final value.

Slew Rate is a large-signal behavior that sets the maximum rateof output change. It is limited by the output driving capability ofthe comparator.

3.2. ArchitecturesComparators can be roughly classified into open-loop (continuous-time) comparators and regenerative comparators. The main differenceresides on whether or not feedback is applied to the op amp used.To obtain the benefits offered by both types of comparators, manyconfigurations have been developed that employ a combination ofopen-loop stages with regenerative stages that use positive-feedback.

3.2.1. Two Stage Open-loop ComparatorsAn open-loop comparator is an operational amplifier designed tooperate with its output saturated, close to the supply rails, based onthe polarity of the applied differential input. The op amp does notemploy the use of feedback and hence no compensation is requiredto achieve stability in the system. This does not poses a problemsince the linear operation is of no interest in comparator design.The main advantage of not compensating the op amp is that it canbe designed to obtain the largest possible bandwidth, therebyimproving its time response.

The circuit of open-loop comparator is shown in Figure 4. It isbased on the commonly used two-stage op amp. The first stage is aNMOS differential-pair consisting of transistors M1 and M2, withPMOS transistors M3 and M4 acting as a diode-connected active load.NMOS Transistor M3 is used to bias the input pair. The output stageis a current-sink inverter consisting of transistors M5 and M6.



Figure 4: Two-Stage Open-Loop Comparator.

The advantage of open-loop comparators is that, if enough gainis provided, the minimum detectable differential input can be verysmall (< 1mV).

Av = –

––

OH OL

in in

V V

V V+

Comparator with the largest gain provides infinite resolution.However, increasing the gain also reduces the bandwidth of opamps, i.e. If resolution will improves then the time response of thecomparator will degrade. Thus, a tradeoff between speed and resolu-tion must be made. The absolute maximum resolution of open-loopcomparators is limited by input-referred noise and the offset voltagepresent in the op amp used.

3.2.2. Regenerative ComparatorsUnlike open-loop comparators, regenerative comparators make useof positive feedback to realize the comparison between two signals.These comparators operate in discrete-time rather than continuous-time form. They operate with a clock that divides the operation ofthe circuit into two phases. During the first phase the comparator



tracks the input and during the second phase the positive feedbackis enabled. Depending on the polarity of the input, the latch’s outputwill go high as the other will go low [1].

Figure 5: Latch Comparator Circuit.

The basic principle of regeneration consists in employing a latchcircuit. In figure 5. the latch employs positive feedback through thecross-coupled connection of the NMOS (or PMOS) transistors andits operation is divided into two phases using a non-overlappingclock circuit. During the first phase, the latch command is issuedand the circuit tracks the input voltage applied between its terminalsVin

+ and Vin–. During the second phase (latch), transistors M5 and M6

isolate the latch from the input as these are turned “off”. The regene-ration occurs between the drain and gate terminals of transistorsM9 and M10, finalizing when one of its outputs turns high and theother low. When a new comparison cycle begins (latch command),the latch output is reset to VDD through transistors M7 and M8. Digitalinverters are usually connected at the outputs to raise the signals tofull digital logic levels. One of the advantages of using positivefeedback is that the time response can be very fast thanks to thepositive exponential transfer characteristic of the latch [3].



Due to mismatch present in the transistors, the resulting offsetvoltage limits the maximum resolution achievable with this circuit.To operate latch in the exponential region of its transfer characteristic,the minimum resolvable input must be large enough to overcomethe large offset voltage, typically in the range from 30 to 100 mV.

3.2.3. Resistive Driving ComparatorsFigure 6 shows the structure of resistive driving latch. TransistorM3 – M6 forms a cross-coupled latch and M7 – M8 forms an inputcomparing circuit. As CLK is low, the circuit works in the reset mode.It is disconnected from GND by M9 while M1 – M2 is on and pre-charge the outputs to VDD. During this time the power consumptionis only due to VDD charging the two output capacitors When CLK ishigh, the circuit works in the regeneration mode. M1 and M2 are cutoff, and M9 is on. In this mode, the circuit can compare the inputvoltages by using input transistors operated in the triode region.

Figure 6: Resistive Divider Comparator.

The comparing circuit which can be modeled has values ofresistors R1 and R2 can be described in the equations. Assume thatWA = W7 and WB = W8 and Vtn is the threshold voltage of the NMOStransistor. If Vin = 1 and Vref = 0 then node Out-will try to dischargethrough M5 and M7 but the transistor M3 try to charge up node Out.Therefore it is very important to make transistor M3 and M4 very



weak as compared to M5, M7 and M6, M8, so that the output willdischarge very fast and the propagation delay will decrease.

3.2.4. Fully Differential Dynamic ComparatorFully differential circuit is useful in rejecting common-mode noisein integrated circuits that do both analog and digital signal processing.In such circuits, comparators provide a link between the analog anddigital domains. Fully differential comparators usually subtract adifferential reference voltage from a differential input voltage (orvice versa).

A fully differential dynamic comparator based on two differentlysized cross coupled differential pairs is shown in Figure 7. In thisthe current sources are switch able and the latch circuit is connecteddirectly between the source coupled pairs and the supply voltage.

Figure 7: Fully Differential Pair Comparator.

When the comparator is inactive the latch signal Vlatch is at OV,which means that the current source transistors M5 and M6 areswitched off and no current path between the supply voltages exists.Simultaneously the PMOS switch transistors Mg and M12 reset theoutputs by shorting them to Vdd. The NMOS transistors M7 and Mgof the latch conduct and force also the drains of all the input



transistors M1 – M4 to V & potential. When Vlatch is risen to Vdd theoutputs are disconnected from the positive supply and the switchingcurrent sources M5 and Ms enter saturation and begin to conduct.These two transistors determine the bias currents of the twodifferential pairs M1 – M2 and M3 – M4, respectively. The thresholdvoltage of the comparator is determined by the current division inthe differential pairs and between the cross coupled branches.

4. RESULTS AND CONCLUSIONThe performance of the comparators are summarized in Table 1.Among all comparators considered Fully Differential DynamicComparators have low power dissipation. The layout [3] of the twostage open loop comparator is shown in Figure 8. Two stage openloop comparator occupies 160 µ2m. In this paper various types ofcomparators have been considered. The propagation delay in allcases and offset voltage measurements are to be found.

Table 1Comparison of Simulation Results

Comparator Type Power Layout (WXH)Two Stage Open-loop Comparators 0.301 mW 20µm × 8 µmRegenerative Latch Comparators 0.208 mW 22µm × 15µmResistive Driving Comparators 7.031 µW 22µm × 9µmFully Differential Dynamic Comparator 0.515 µW 22µm × 13µm

Figure 8: The Layout of the two Stage Open Loop Comparator.



REFERENCES[1] Behzad razavi, bruce a. Wooley, “Design Techniques for High-Speed, High-

Resolution Comparators”, IEEE Journal of Solid-State Circuits, 27. No. 12.December 1992.

[2] Christian Jesus B. Fayomi, Gordon W. Roberts’ and Mohammad Sawan,“Low Power/Low Voltage High Speed CMOS Differential Track and LatchComparator with Rail-to-Rail Input”, In ISCAS 2000 - IEEE InternationalSymposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland.

[3] Baker R.A Li H. W, and Boyce D.E., “CMOS Circuits Design, Layout andSimulation” IEEE Press Series on Microelectronic System.

[4] P. Cusimato et al., “Analysis of the Behavior of a Dynamic Latch Comparator”,IEEE, Trans. on Circuits and Systems-I: Theory and Applications, 45, No. 3,pp. 294-298, Mar. 1998.

[5] Rudy Van De Plassche, “CMOS Integrated Analog-to-Digital and Digital-to -Analog Converters”, Springer International Edition, 2005.

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