cmos comparators

F. Maloberti

:

Design of CMOS Analog Integrated Circuits -

CMOS Comparators 6/1

D

ESIGN

OF

CMOS A

NALOG

I

NTEGRATED

C

IRCUITS

Franco Maloberti

Integrated Microsistems LaboratoryUniversity of Pavia

CMOS COMPARATORS

F. Maloberti

:



PERFORMANCE CHARACTERISTICS

r

A comparator detect when its input is larger or smaller than a reference voltage. Its output is a large voltage with an appropriate sign.

r

The output is assumed to represent a digital 1or 0 level.

+ vout

vref

vin

vinvref

F. Maloberti

:



PERFORMANCE

Voltage gain:

is the DC differential gain of the comparator. The outputpeak-to-peak swing is in the range of 3-5 V. Therefore, for low speed, in or-der to detect a 1 mV signal a voltage gain of 5000 is sufficient.

Input offset:

is the voltage that must be applied to the input to get the tran-sition between the low and the high state (same as the op-amp).

Response time:

is the time interval be-tween the application of a step inputand the time when the output reachesthe respective logic level. The responsetime depends on the amplitude of thestep input.

0 2 4 6 8 103

4

5

6

7

8

Input Step Amplitude [mV]R

espo

nse

Tim

e [n

sec]

F. Maloberti

:



Overdrive recovery time:

if the input is driven with a voltage largerthan the one required to cause the output saturation, the comparatoris over driven. The response time for a given input amplitude, de-pends on the value of the overdrive voltage at which the comparatorwas driven.

0 20 40 60 80 100 1200

10

20

30

40

50

Overdrive Voltage [mV]

Res

pon

se

Tim

e [n

sec]

2 mV

vov

F. Maloberti

:



Latching compatibility.

A latch command and an unlatch commandstores and releases the output logic state. Typically the load set-uptime is around 2 nsec.

Power supply rejection.

Transfer function between the supply railsand the output of the comparator.

Power consumption.

Power dissipated at DC (static) and during thecomparison (dynamic).

Hysteresis.

The threshold voltage for rising input signals is differentfrom the threshold voltage for falling input signals.

F. Maloberti

:



BASIC CONSIDERATION

r

A comparator is basically an

open loop gain stage

. The required DC gain is

80 dB (sometime more).

Key points:

r

Gain obtained by the use of complex schemes or by the use of the cascade of simple schemes.

r

How to do V

os

cancellation.

r

Power supply rejection.

r

Overdrive recovery.

r

Power consumption

All solution are strongly conditioned by the

offset cancellation

(Vos

3- 10 mV).

F. Maloberti

:



Comparator Gain:

Due to the finite bandwidth of the circuit, the output voltage reachesA

v

V

in

with a delay with respect to the time when the input is applied(response time t

r

).

The same output voltage is get, with the same response time, by theuse of stages having different speed but different DC gain.

0 1 2 3 40,0

0,2

0,4

0,6

0,8

1,0

time (arbitrary scale)

A

A

A

AAAAA

tr

Av vin

F. Maloberti

:



Single stage:

if:

The speed is increase by increasing g

m

/C

L

.

typically:

g

m

= 0.5 mA/V C

L

= 0.5 pF g

m

/C

L

= 1/nsec

Hence, the gain after a delay of 10 nsec is 10.An improvement is get by the use of a chain of identical stages. Under thesame assumption:

gm RL CL

+

Out

vi

t t RLCL=

Vout gmRLVi 1 et RLCL( )

( ) VigmCL-------t@=

Vout VingmCL-------

n tn

n!-----=

F. Maloberti: Design of CMOS Analog Integrated Circuits - CMOS Comparators 6/9

For a given gain, it exists an optimum number of stages which givesthe best response time. For example: a very small gain is reached us-ing one only stage with a response time t1 smaller than the one ob-tained with a chain of n identical gain stages.

For a given gain an optimum n results:

n 1 2 3 4 5 6 7 8 9An 2 4.5 10.6 26 64.8 163 416 1067 2755

Ann 1+( )n

n!--------------------=

tn n 1+( )CLgm-------=


OFFSET CANCELLATIONr Autozero techniquer Autozero in multistage comparatorsr Differential schemesr Compensation by auxiliary input stages

AUTOZERO TECHNIQUEBasic idea: sample the offset duringone phase and sum it tothe signal during the mea-sure phase.

+

vinoutv

S/H

vx

vos

++ 1

2


Two phase are required:

Phase 1: AutozeroPhase 2: Measure

r Time domain analysis:

if the offset changes slowly Vos(0) Vos(T)r Frequency domain analysis

(Laplace Transform):

The low freq.of the offset are cancelled.

A

A

A

1

2

A

A

A

0 T

t

t

Vin T( ) V+ T( ) V- T( ) Vos T( ) Vx T( ) Vos 0( )( )= =

0.0 0.25 0.5 0.750

1

2

3

fT

AAAAAAA

AAAAAAA

A

A

A

A

A

A

A

A

A

Fos(f)

Vin s( ) Vx s( ) Vos s( ) 1 esT

( )+=

Fos s( ) 1 esT

2je sT 2 sT 2( )sin= =


Autozero in single stage, implementation:

r During phase 1 the gain stage is in unity gain closed-loop configuration.

r During phase1 C acts as an output load of the gain stage.r During phase 2 the gain stage is in open loop configuration.

+

vx

vos

1

2

1

S1

S2

S3

vout


r The finite gain Av of the gain stage produces a residual offset error

r Exists the problem of the clock feedthrough at the opening of S1; it determines an equivalent offset error (Vos,ck).

r If the complex gain stages are used it is worth to compensate the stage only during the autozero phase.

Vos res, Vos VosAv

1 Av+---------------- Vos

11 Av+----------------= =

Vos res, Vos1

1 Av+---------------- Vos ck,+=

ViVout

S11

VosS21

2

S3 C

+

CC1S4


Clock feedthrough and signal attenuation:

r The charge injected by the switch S1 is integrated onto C and the input capacitance of the gain stage.

r The input signal is attenuated by the factor C/(C + Cin).r In order to reduce the attenuation and the equivalent offset [Vos,ck

= Qck/(C + Cin)] C must be chosen large and >> Cin

+

outv

vx

vos

1

2

1

S1

S2

S3C

Cin


Autozero in multistage comparators:

A = A1A2......Anr The offset of the third stage is referred to the input attenuated by the

factor A1A2. Usually its contribution is negligible.r The clock feedthrough from S1 and S2 causes the rising of two

equivalent offset voltages, Vos,1 and Vos,2 at the input of A1 and A2.The resulting input offset is:

vx

1

2

1

S1 S2

S3

C11

C2

A1 A2 A3 An

Vos Vos 1,1

A1------Vos 2,+=


Improved solution (sequential offset andfeedthrough cancellation):

Drive S1 with F 1 and S2, S3 with F 1r The charge injected by S1 is collected on C2, the equivalent offset is

amplified by A1. Since S2 is still on, the output voltage of A1 is sampled and stored onto C2.

r An autozero of the effect of Vos,1 results.

The offset becomes:

r Vos,1 and Vos,2 must be such to not saturate A1 and A2 (gain of A1 and A2 low, suitable values of C1 and C2).

F 1

F 1

Vos1

A1------Vos 2,=


Implementation:

r Each gain stage can be implemented with a CMOS Inverter:

(Av = 5 - 20)

Differential schemes:

r The clock feedthrough due to the opening of S1 and S2 gives a common mode signal. Its effect is cancelled. Residual offset is due to the mismatching.

M1

M2

M3

M4

M5

M6

M7

M8outin

1 1

1

2

C 1 C 2

+VR

1

2

1

S1

Vin

S21

C

C

2

1

Vout-

Vout+


Fully differential blocks:r Very low gainr Low gain with CMFBr Conventional fully differential amplifierVery low gain:

Advantage:CMFB not necessary

Disadvantage:The capacitance Cgs of the loadsM3 and M4 act as load of the out-put.I1

M1 M2

M3 M4

in

out


Low gain with CMFB:

J Low capacitive load at the output

L Two bias lines

Improved solution:r Minimum capacitive load at

the nodes A and B.r Low impedance output.r Optionally the CMFB stage

can be used as gain stage with single ended output.

M1 M2

M3M4

in

out

MA MB

VB1

VB2

12---Cgs A, .......+

M1 M2

M3M4

in

VB1

VB2

Out

M5

M10M9

M7

M12M8M6

M11


Compensation by auxiliary input stages:Basic idea: store the offset at the output of the gain stage and use it in feed-back connection to cancel the input offset.

During phase 1 the inputs of A1 are short circuited. The output of A1 goes toA1Vos,1

CAZvos,1

+

Out

vos,2

+

+

+A2

A1

S1

S2

1

1

A1Vos 1, A2 Vos 2, Vo( )+ Vo=

VoA1

1 A2+----------------Vos 1,

A21 A2+----------------Vos 2,+=


Referred to the input of A1, the equivalent offset is:

r The switch at the input of A1, S1 is opened while S2 is closed. The offset, caused by charge injection from S1, is attenuated by (1 + A2).

r When the switch S2 is opened the charge that it inject is collected onto CAZ and an offset Vos,inj appears. It is amplified by A2 and appears at the output; it is equivalent to an input offset equal to:

Veq os,Vos 1,1 A2+----------------

Vos 2,A1

--------------+=

Vin os, Vos inj,A2A1------

=


gm1 gm6 in order to haveA1 10 A2

Degenerated current mirror:

J No additional supply current

L Bad PSRR

M1 M2

M3M4

in

out

aux in

VB2

M7M6

M8M5

VB1

M1

M6M5

M8M7

M2

M9

VB2

+

_

M10 M3 M4 M11

Outin

aux in


LATCHESr A comparator can be followed by a latch. The input can be differential or

single ended; in the latter case one of the inputs can be replaced by a reference voltage.

r During F 1 M1, M3 and M2, M4 form two inverters with active load. The parasitic capacitances incident nodes 1 and 2 are pre-charged to a logic signals.

M1 M2

M3M4

out +

M7

M6M5

out -

in + in -

strobe

VB

1 2


r During F 2 the latch is enabled and it assumes a stable state.

Typically: latching time 2- 10 nsec with Vin = 10 mV

r When F 1 comes along, the output voltages will both try to rise. Because of the difference in input voltages one is faster and starts the regenerative action.

M3

out +

M6

M5

out -

in + in -

strobe

VB

M2M1

M4


J Strobed at the drain: carrier mobility faster at zero substrate bias.

J Small load capacitance of the flip-flop.

M8

out +out -

in + in -

M6M5

M9

M1 M4

M3M2

strobe strobe

strobe strobeM10M7


Combination gain stage / latch:

r When the strobe signal is down, the gain stage pre-charge the parasitic capacitances of the latch, when the strobe goes up, starts the regenerative action of the latch.

M3M4

out +

M7in -

strobe

VB2

VB1

M6

strobe

out -

in +

M7

M9

M5

M7

M8


Combination gain stage / latch with double regenerative loop and out-put flip-flop:

r When the latch signal F is on, the bias current is switched from the gain stage to the latch.

M20

M1 M2

M4M3

M5 M6

M7

M8 M9

M10 M11 M12 M13 M14 M15

M16 M17

M18 M19

Vb

Vin+Vin

VoutVout+

stro

bestrobe


POWER CONSUMPTIONr Comparator gain including offset compensation and output latch

r The voltage swing at the output of the first stage is

r The voltage swing at the output of the second stage is:

+

+

Vi

2

1 Cin

Vin1

A1gm, 1 Vin

Vo

C1A2

gm, 2 Vo C2

Latc

h Vout

Vo t( )gm 1,C1

------------ Vi t( ) td0

t

=

Vout t( )gm 2,C2

------------ Vo t( ) td0

t

=


r For constant or slowly varying signal at the end of the comparison phase (g / fck) the output voltage Vout is

r Theoretical minimum of power consumptionr MOS transistors in strong inversion ( )

r MOS transistors in weak inversion ( )

Vout12---Vi

gm 1, gm 2,C1C2

------------------------- gfck------

2=

ID Ilim>

gm2 m CoxIDW

nL----------------------------=

ID Ilim

gm 1,VcritC1fck

Vi min, g--------------------------> Vi min, Vcrit


for

Theoretical minimum of power consumptionr In practical cases security margins have to be taken into account

ID 1,VcritC1fck

g

--------------------------> Vi min, Vcrit>


CONCLUSIONS

r Key issues in comparator design Optimization of the number of stages to achieve the desired

response time with a given power consumption Offset cancellation Autozero technique Clock feedthrough, power supply and common mode

rejection ratios Fully differential structures Overdrive recovery Limit the voltage swing at critical

nodes or when possible introduce a reset phase

cmos comparators

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