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Microelectronic Engineering 73–74 (2004) 542–546

Fabrication of nanoscale vertical colloid device architectures

A.J. Parker a,b,*, P.A. Childs a, R.E. Palmer b

a Emerging Devices Technology Research Group, School of Engineering, Electronic, Electrical and Computing Engineering,

Edgbaston, Birmingham B15 2TT, UKb Nanoscale Physics Research Laboratory, School of Physics and Astronomy, The University of Birmingham, Edgbaston,

Birmingham B15 2TT, UK

Available online 14 March 2004

Abstract

The design, fabrication and preliminary testing of a vertical nanodevice comprising an active region of gold colloidal

nanoparticles deposited within a silicon nanopillar architecture is presented. Each step of the fabrication is a parallel

process, starting with the production of an array of silicon pillars using natural lithographic techniques. Electrical

measurements through a small array of these pillars show linear behaviour in the current–voltage curves, which lead to

a pillar resistance value fully commensurate with the known geometry. The results in this paper show the fabrication at

each stage, and when combined with characterisation data represent a demonstration of the ‘proof of principle’ of our

approach.

� 2004 Published by Elsevier B.V.

Keywords: Vertical nanodevice; Gold colloidal nanoparticles; Silicon nanopillar; Natural lithography

1. Introduction

Since the experimental observation of the

Coulomb blockade to electron tunnelling, there

has been a great deal of research centred on the

phenomenon, with the view to incorporating it

within electronic devices. Many of these devices

are designed around a small conducting cluster

(<20 nm in diameter) which is electrically isolated

from a set of surrounding contacts, a route whichis particularly favoured, as these small clusters

inherently exhibit Coulomb blockade at elevated

temperatures [1]. The patterning, however, of both

* Corresponding author.

0167-9317/$ - see front matter � 2004 Published by Elsevier B.V.

doi:10.1016/j.mee.2004.02.082

the cluster and an electrode arrangement of a de-

vice is primarily reliant on relatively slow e-beamlithographic techniques, while by contrast, depo-

sition of pre-formed clusters from solution is both

simple, quick and parallel [2–4]; this makes the

latter approach particularly attractive within an

industrial environment. A key challenge, however,

in using solution-based clusters, is the repeatable

and controlled deposition of as few as possible

(preferably one) into the active centre of a device.Whilst significant research has centred on the pro-

duction of ordered films of these clusters [5–11],

with more recent work on site-selective deposition

[12,13], the difficulties of patterning nanoscale

contacts remains. An interesting route which

A.J. Parker et al. / Microelectronic Engineering 73–74 (2004) 542–546 543

circumvents these issues, whilst additionally facil-

itating higher density ICs, is to design vertical

device architectures. Growth of cluster films can

readily be restricted to monolayer formation [14],

and thereby affords good control over the critical

vertical dimension in such devices; further, it re-moves the reliance on high-resolution lithography.

2. Experimental

Here, we report on the continuation of our

previous work detailing the design and fabrication

of a vertical nanodevice utilising gold colloidalnanoparticles as active centres in silicon pillars.

Details of the device design and fabrication pro-

cedure can be found in more depth in [15], only an

outline is presented here. Fig. 1, schematically

depicts the fabrication route for the device, which

begins in Fig. 1(a) with the production of an array

of silicon pillars. For these pillars to provide both

the lateral confinement of the device and as thebottom contact to the nanoparticles, they need

electrically isolating and the surface requires pla-

narisation. Deposition of a dielectric medium,

Fig. 1(b), with subsequent removal of the upper

Fig. 1. Schematic outline of the fabrication procedure for a

vertical device: (a) The generation of a nanopillar array by

natural lithography. (b) Isolation of the pillars and surface

planarisation. (c) Exposure of pillar tops, followed by (d) pillar

etch for pit production. (e) SAM formation and colloid depo-

sition atop the pillars and in the pits. The device is completed

(f), with the filling of the pit with an organic insulator and the

evaporation of a top contact. The arrow indicates the flow of

current through the pillar to the colloids.

part of the film to reveal the pillar tops, Fig. 1(c),

facilitates the generation of nanoscale tubes via a

controlled silicon etch, Fig. 1(d). Measurement of

the electrical conduction of the silicon pillars prior

to this etch, can be achieved on the structure

shown in Fig. 1(c) by the deposition of a metalcontact. With the tops of the pillars removed,

simple deposition of passivated clusters from so-

lution will give a short cluster tube, the same width

as the etch pit, positioned atop the underlying

silicon pillar, which can then be electrically pro-

bed. A more controlled method for deposition of

nanoparticles into the tubes is achieved by the

growth of a self-assembled monolayer (SAM),which will bond to the silicon and to which the

metal particles will attach, Fig. 1(e) [14]. Final

deposition of a non-conducting polymer to isolate

the clusters from the metal top contact completes

this incarnation of the device, Fig. 1(f).

Silicon pillars were fabricated in n+ type (0.06–

0.12 X cm) silicon using the process of natural li-

thography [16–18]. Two microns polystyrenespheres were drop deposited onto the surface from

aqueous solution, and self assembled into a hex-

agonal array during the evaporation of the water.

This is followed by deposition of �100 nm of

chromium, which patterns the silicon through the

interstices of the polyballs. The spheres are dis-

solved in chloroform prior to an anisotropic

plasma etch [19]: sulphur hexafluoride (SF6) andcarbon tetrafluoride (CF4) in the mixture 25:25

sccm, at a radio frequency power of 100 W for up

to 240 s. This etch gives near-vertical side wall

silicon pillars of around 1 lm height, an example

of which is shown in the scanning electron mi-

croscope (SEM) image, Fig. 2(a), taken with an

FEI XL-30 SFEG, where the triangular cross-

section originates from the metal mask which canstill be seen to be in place. Spin casting of a

polyimide dielectric layer is the most repeatable

route to isolating the pillars and planarising the

surface. The polyimide used: Durimide 7505 ob-

tained from Arch Chemicals, is a photosensitive

dielectric compound which is processed in the

same manner as standard photoresist [20]. Once

spin cast, the solvent is driven out of the materialby a 350 �C bake under nitrogen for 60 min, which

transforms the layer into a rigid and chemically

Fig. 3. Measured current vs. applied voltage through an array

of 13, 1.2 lm tall pillars. Resistance measurements of linear

region of the device are commensurate with device geometry.

Fig. 2. SEM images showing various stages in the device pro-

duction: (a) Hexagonal arrays of triangular pillars in silicon,

each pillar is �0.3 lm across and �1 lm tall. (b) The polyimide

planarising layer after blanket exposure reveals pillar tops. (c)

Patterning of a 3.5 lm hole through a photoresist film to isolate

six pillars for electrical characterisation. (d) RIE in SF6 gener-

ates nanoscale pits in the polyimide film, which can once again

be isolated with photoresist (e) prior to passivated cluster de-

position (f). (g) Hybrid pillar-colloid device, after dielectric

layer removal.

544 A.J. Parker et al. / Microelectronic Engineering 73–74 (2004) 542–546

inert solid. The removal of the top of this film to

expose the pillars can only be achieved with re-

peatability via an Argon ion mill, as the polyimide

is resilient to any form of controlled chemical etch.

The result of this mill can be seen in Fig. 2(b),

which shows the hexagonal array of pillar topsthrough the dielectric polyimide layer.

Prior to the second silicon etch for generation

of nanoscale tubes, electrical transport measure-

ments are made through as few pillars as possible.

Such measurements are achieved by patterning a

small hole, �4 lm across, through a photoresist

film which is spin cast over the structure shown in

Fig. 2(b). The result of this can be seen in Fig. 2(c),

which shows a single hexagon of isolated pillars

exposed through a �500 nm thick photoresist film

of Chestech S1805. Subsequent deposition of a

�300 nm thick gold top contact will make contact

only with these six pillars and, as the photoresist is

sufficiently insulating to avoid any short circuits,will allow an approximate calculation of their re-

sistance. This measurement is made on each sam-

ple prior to nanotube formation to ensure that the

pillar is indeed conducting, that the polyimide film

is insulating and finally as it will allow for some

comparison with measurements made on full de-

vices containing nanoparticles.

3. Results

Fig. 3 shows a plot of measured current vs.

applied voltage for a similar structure to that

shown in Fig. 2(c), except that thirteen 1.2 lm high

pillars were accessed through the hole in the pho-

toresist rather than six. As each pillar is �200 nmacross, measured from point to flat of the cross

section, simple ohmic behaviour in the current–

voltage characteristic is expected. Immediately

evident is that the relationship is non-linear

around the origin; this is common to all of the

measurements made on such systems, to greater or

lesser degrees, and is attributed to Schottky-type

barrier formation at the contacts. This suppositionis further supported when the non-symmetry

A.J. Parker et al. / Microelectronic Engineering 73–74 (2004) 542–546 545

around 0 V is considered alongside the full device

geometry. The back contact is formed by scoring

the reverse side of the wafer to increase the surface

area, prior to deposition of a 5� 5 mm2 gold

contact (with a �10 nm chromium adhesion layer).

Considering the high doping of the silicon this canbe expected to make a good ohmic contact, by

contrast, the contact area atop the pillars is very

much smaller and could certainly lead to more of a

barrier to transport in one direction.

Moving away from the origin of the plot in

Fig. 3, above 1 V and below )2 V, the curve is

linear. Calculation of the overall resistance of the

pillars for a nominally forward bias, gives a valueof 23.7 kX; as this is through 13 pillars it leads to

an average individual resistance of 308 kX. Whilst

this value seems reasonably high, it relates to a

conduction channel with a diameter lying between

50 and 80 nm for a 1.2 lm pillar with doping in the

region 0.06–0.12 X cm. This value is quite com-

mensurate with the size of the pillar but does as-

sume that there has been no depletion of carriersfrom the pillar, suggesting that the actual con-

duction channel could, therefore, be larger.

Ten minutes in acetone under ultra sonic agi-

tation removes the photoresist film and most of the

top contact (that which made contact with the

pillars through the resist aperture remains), re-

turning the samples to the state shown in Fig. 2(b).

Tube formation is achieved by short exposure to alow pressure reactive ion etch (RIE) of SF6 gas.

This selectively removes the exposed pillar tops to

leave small pits in the polyimide surface with the

silicon pillar providing the base, this can be seen in

Fig. 2(d). This is the structure shown schematically

in Fig. 1(d). Clearly observable in this image, is

that the polyimide film has remained rigid and that

there has been no sagging nor swelling into thetube. At this point, metallic nanoclusters can be

deposited into the tubes following one of two

methods: the simple drop deposition of passivated

clusters held in a non-polar organic solvent over

the whole structure [12,13], or the growth of a self

assembled monolayer (SAM), with subsequent

binding of colloidal particles held in an aqueous

solution [14,15].A sample such as that in Fig. 2(d), with etched

pits in the surface, is spin coated with Chestech

S1805 photoresist and a small hole patterned

through to the underlying polyimide layer. This

structure can be seen in Fig. 2(e), note that this

architecture is very similar to that of Fig. 2(c) ex-

cept that in this case the protruding tops of the

silicon pillars have been removed. The hexagonalpatterning visible in the bright photoresist layer is a

result of the charge build up on the resist surface

having an electrical earth through to the pillar at

the bottom of the etched tube, thereby giving a

lower surface charge in these areas. Six microlitres

of passivated gold cluster solution, 3 nm gold cores

surrounded by dodecanethiol ligands and held in

solution with toluene, were drop deposited over theentire sample; once again, only those etch pits lying

in line with the photoresist aperture can be ad-

dressed. Fig. 2(f) is a SEM image of the sample

shown in Fig. 2(e) after this deposition of clusters.

Immediately evident is that the photoresist aperture

has not been affected by the deposition and that the

clusters, observed as the grey film, have completely

covered the polyimide structure and filled the tubesto contact the shortened silicon pillar. This struc-

ture is similar to that expressed in Fig. 1(e), except

that the whole of the tube is filled with nanoclusters

rather than just the surface of the pillar top. Simple

evaporation of a metallic top contact over such a

sample, will give a device similar to that in Fig. 1(f),

which is expected to show markedly different elec-

trical characteristics from the simple pillar devicesseen in Fig. 3. To obtain a more controlled depo-

sition, the growth of an aminopropyltrimethoxysi-

lane (APTMS) SAM with subsequent binding of

nanoparticles, precise details given previously [15],

will generate the structure shown in Fig. 1(e). Such

an arrangement can be seen in the SEM image of

Fig. 2(g), which shows a pillar decorated with gold

colloids after the dielectric medium has been re-moved. Pillars patterned in this manner, still re-

quire electrical isolation of the colloids and a more

substantial insulating layer to avoid short circuits

prior to the deposition of a top contact.

4. Conclusion

In conclusion, we have demonstrated the feasi-

bility of constructing a vertical nanoscale device

546 A.J. Parker et al. / Microelectronic Engineering 73–74 (2004) 542–546

which incorporates clusters as the active device

centre. Preliminary electrical measurements taken

at room temperature through arrays of nanoscale

silicon pillars, show linear characteristics which

are commensurate with the known geometry and

semiconductor doping levels. The inclusion of atop contact into the structure shown in Fig. 2(f), to

generate a hybrid pillar-cluster device, would be

expected to exhibit very different electrical behav-

iour. Given the number of clusters involved,

however, a coulomb gap around the origin is all

that could be expected, with the Coulomb staircase

being obscured. More reliable electrical behaviour,

with the opportunity for near room temperatureoperation, would follow from a device constructed

from the structure shown in Fig. 2(g), prior to

dielectric removal. Either a long alkane chain thiol

or amine terminated molecule will bind to both the

colloid and the exposed SAM, and provide elec-

trical isolation of the pillar and colloid with a

contact deposited on top. Finally, transistor action

in this device could be obtained with an annularmetal contact deposited around the active region,

which would be used to adjust the coulomb levels

of the colloids.

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