fpga sdk for nanoscale architectures
TRANSCRIPT
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FPGA SDK for Nanoscale Architectures
Ciprian.Teodorov Loic.Lagadec @ univ-‐brest.fr ReCoSoC’11 – Montpellier, 21-‐23 June 2011
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Overview
• Emerging Technologies • Nanoscale Architecture Template • FPGA Tools for Nano • Results
FPGA SDK for Nanoscale Architectures 2
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Context
• CMOS reaching its limits – Physical – Material – Power-‐Termal – Technological – Economical
? Emerging Technologies
FPGA SDK for Nanoscale Architectures 3
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FPGA SDK for Nanoscale Architectures 4
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! boolean data inputs A and B (logic levels at Vss=0V and Vdd=1V) + circuit output Y
! four-phase non-overlapping clock signals
– two pre-charge inputs PC1, PC2
– two evaluation inputs EV1, EV2
! control inputs VbgA, VbgB, VbgC to configure circuit to 1 of 14 functions (back-gate bias -1V / p-type and +1V / n-type)
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QCA, Notre Dame
NanoCell, J. M. Tour
I. O’Connor (INL) Nanofabric, S.C. Golstein
NanoPLA, A. DeHon
CMOL, K. Likharev
FPNI, HP, G.S. Snider
Nasic, C.A. Moritz
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NASIC Fabric Principles
FPGA SDK for Nanoscale Architectures 5
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Rou\ng Problem
FPGA SDK for Nanoscale Architectures 6
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FPGA SDK for Nanoscale Architectures 7
Routing Block
Logic
Conn
ectio
n
CMOS I/O
VDD
GNDpre
eva
CMOS-gated NWFET
MultiNW-gated FET
OutputInput
Hei
ght Ce
ll
WidthCell
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FPGA SDK for Nanoscale Architectures 8
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R2D NASIC
• Compa\bility with the NASIC • Adaptability to a variety of technological and applica\ve constraints
• Compa\bility with NASIC fault-‐tolerance techniques • Regularity => custom placement and rou\ng • Max-‐rate pipeline designs based on its pipelined rou\ng architecture
• Simplified delay es\ma\on, due to the dynamic logic evalua\on and pipelined rou\ng architecture
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Tools for nano
PLAMap – PLA extrac\on
VFLib – tech. mapping
Proprietary tools & algos
VPR NanoPLA &
CMOL
Madeo @ nanoscale
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Madeo FPGA Toolkit
• Reconfigurable architecture & generic tools – P&R, alloca\on, circuit edi\on
• High-‐level logic compiler – HLS & op\mized arithme\cs
• System and architecture modeling (SoC) – logic primi\ves, processes – hardware-‐plagorm management – system ac\vity.
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Madeo at Nanoscale
• Model extensions: – nanogrid, nanowire (crossbar fabric level) – Turn connec\ons, and PLAs (R2D Nasic)
• HDL evolu\on for nano model instan\a\on • Algorithmic extensions: – Espresso PLA op\miza\on – Netlist par\\oning for PLAs – PLA placement – New rou\ng algorithms
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R2D NASIC Design Flow
Placement
Rou\ng
PLAMap
PLA Family Explora\on Architecture
SIS
Metrics
Layout
PLAMap
SIS
MADEO
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Results – Area
alu4
17.35X
apex2
1.32X
apex4
48.43X
des
2.18X
ex5p
24.06X
misex3
12.05X
seq
8.76X
100
10
1
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Speed
43MHz 67MHz
40MHz
9MHz
167MHz
29MHz 27MHz
1
10
100
1000
alu4 apex2 apex4 des ex5p misex3 seq
Freq
uency
Opera\ng frequency of the slowest logic stage / throughput
Results assume 1GHz for the slowest logic stage
Too slow
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Max-‐Rate Pipeline System
Add REs
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ab
c d
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Results – Speed
alu4
24.21X
apex2
10.56X
apex4
23.78X
des
77.15X
ex5p
4.8X
misex3
32.58X
seq
31X
Net Performance Improvement
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Results – Area
seqmisex3ex5pdesapex4apex2alu4
17.35X
1.32X
48.43X
2.18X
24.06X
12.05X8.76X
2.72X
0.03X
11.52X
0.06X
12.76X
1.24X
0.46X
100
10
1
0.1
0.01
Normalized density advantageover 45nm standard cell design
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Performance*Area
66X
0,32X
274X
5X
61X 40X
14X
0,1
1
10
100
1000
alu4 apex2 apex4 des ex5p misex3 seq
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Room for Improvement
AVG
255
seq
334
misex3
243
ex5p32
des
740
apex465
apex2
301
alu4
149
misex3 switch-use mapStd. dev. ofswitch ressource use
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Conclusion
• Regular nano architecture template – Custom placement & rou\ng
• Incremental DSE with MADEO toolkit
• Future work: – R2D NASIC wrt. fault tolerance and \ming issues under variability assump\ons.
– Improve toolkit’s extensibility by further decoupling the tools from the target architecture
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Thanks for your alen\on!
FPGA SDK for Nanoscale Architectures 23
Q&A