experiment 5 lab 8 digital logic and state machine design as you wait for the lab to start : is your...

Experiment 5

Lab 8

Digital Logic and

State Machine Design

As you wait for the lab to start : Is your laptop up-to-date ?

CS CS 22042204CS CS 22042204

Spring Spring 20142014Spring Spring 20142014

Lab 8 Outline Presentation

Analysis of the term project Analysis of Block 1 of the term project (using Term Project pages

11 – 16) Analysis of Block 6 of the term project (using Term Project pages

38 - 48) Implementing a machine player A machine playing strategy

Xilinx sequential circuit components

Individual work Experiment 5

Develop the BCD up counter of the Information Gathering Subblock of Machine Player of the Ppm term project

Experiment 5 Lab 8CS 2204 Spring 2014

Analysis of the Term Project Polytechnic Playing Machine, Ppm

The term project is human vs. machine

The black-box view


From page 2 of the Term Project Handout

Figure 1. The Ppm black box view.

Ppm13 19

From the input devices To the output devices


PpmInput/outputrelationship

Ppmoperationdiagram

Fro

m p

ag

e 8

of

the T

erm

Pro

ject

Han

dou

tLD0-LD2 on the FPGA board show the current state

The Ppm Digital System Partitioning


From page 9 of the Term Project Handout

Digital Systems A digital system performs microoperations

A digital system consists of digital circuitsA digital system consists of

A data unit (datapath) It performs microoperations

A control unit It controls the datapath


Digital Systems This first partitioning of a digital system is

universal

A microprocessor is a digital system An iPhone is a digital system A computer is a collection of digital systems


control signalsstatus signals

Sequencer

Registers ALUs buses Data Unit

Control Unit

Figure 7. A large scale view of a digital system.

Other digital systems/Input/Output devices (Datapath)

Digital Systems The Data Unit has registers, ALUs and

buses to perform microoperationsRegisters keep (store) data (operands and

results)Arithmetic Logic Units (ALUs) perform

additions, subtractions, multiplications, ANDS, ORs, etc.

Buses interconnect registers and ALUs


Digital Systems The Control Unit (Sequencer)

The control unit determines the sequence of microoperations based on the current state and status signals

In each state, it enables the microoperations of that state to happen in the data unit based on the status signals

• Microoperations must start at the right time with correct inputs and end at the right time with correct outputs

We should not lose data and we should not use old data

• Glitches, gate delays must be accounted for When we design it, we account for every possible gate delay

The control unit also determines which state is next : Next State


Digital Systems The Control Unit (Sequencer)

The state register indicates the current state Logic to generate the control signals and the next state

more irregular than the Data Unit


State

Status signals Control signals

CurrentState

NextState

Control signal andnext state valuegeneration circuits

Figure 8. A general view of the sequencer.

Register

(To the Data Unit)(From the Data Unit)

Fro

m p

ag

e 1

1 o

f th

e T

erm

Pro

ject

Han

dou

t

Digital Systems The Control Unit (Sequencer) design

Hardwiring vs microprogramming

Since our Ppm system is simple, we use hardwiring and so we will concentrate on hardwiring from this point on


Random


Figure 9. Digital system sequencers.

a. A general view of a hardwired sequencer.

NextState

CurrentState

Memory


NextState

CurrentState

b. A general view of a microprogrammed sequencer.

StateRegister

StateRegister

Logic

Gate/FF networks = random logic = irregular

Highlyregularbut slower

Memory bits generate control signals and NS

Not as regularas the datapath

Look-uptable


Hardwired Control Unit design First partitioning on the Control Unit

•Control Signal generation Subblock•Next State Generation Subblock


State


CurrentState

NextState



Register


Often a counter is used instead of a register since we frequently trace the states sequentially

Often a decoder is used to generate the control and next state signals


Hardwired Control Unit design Often a counter+decoder combination is used in the

sequencer


n-b

it u

p c

ou

nte

r

n

clock n-t

o-2

n D

ecod

er D0

D1

D3

S0

S1

.....S2(n-1)

Load

Data

nControlsignals

NextState

ControlSignals

&NextState

Circuits

Next state Current stateIf it is state 0, S0 is 1

Status signals

The Ppm Control Unit Block 1, the Control Unit (the sequencer)

It controls the Data Unit It determines the sequence of microoperations

Which microoperation happens when


Block 120 23


The control unit determines the sequence of microoperations based on the status signals Implemented by using the finite-state machine

(FSM) technique Uses hardwiring

• Gate and flip-flip networks generate control signals Partitioned into

• Control Signal generation Subblock • Next State Generation Subblock




ControlSignalGenerationSubblock

Gate and flip-flop networks generate control and next state signals

HardwiredControl Unit

NextStateGenerationSubblock

Controlsignals

Counter-Decodercombinationto keep trackof the currentstate

Digital Systems How can we design a digital

system ? If the digital system is complex

It is the case with real chips, such as microprocessors

• Write an HDL program ► VHDL program ► Verilog HDL program


Digital Systems How can we design a digital system ?

If the digital system is simple It is the case with our term project

• Use the finite state machine (FSM) technique ► We draw a finite-state diagram

• One obtains the operation diagram then converts it to a FSM state diagram with same number of states ► Get a finite-state diagram directly from the operation

diagram


Digital Systems How can we design a digital system ?

If the digital system is simple It is the case with our term project

• Use the finite state machine (FSM) technique ► Obtain a high-level state diagram directly from the operation diagram

Use the Register-Transfer Level (RTL) notation

► Obtain the datapath from the high-level state diagram ► Obtain the low-level state diagram from the datapath and high-level

state diagram ► Obtain the Control Unit


Register ← Source

Wire/bus = Source

Digital System Design Using FSM The Data Unit (Datapath)

The data unit performs microoperations based on the control signals

The data unit goes through states• The high-level state diagram indicates the microoperations

► Each state indicates the microoperations to perform in that clock period

The Data Unit generates status signals as it performs microoperations

► In each state, the control signals indicate which microoperations

should happen The low-level state diagram indicates which

control signals should be active


Digital System Design Using FSM The Control Unit (Sequencer)

The control unit determines the sequence of microoperations based on the status signals

The control unit goes through states• Each state has a unique number to identify

► The state register value is the current state number

• In each state, it enables the microoperations of that state to happen in the data unit based on the status signals

• It generates the control signals and next state signals timely


State


CurrentState

NextState



Register


Digital System Design Using FSM The Control Unit (Sequencer)

The sequencer is treated as a state machine A low-level state diagram (with finite number of

states) shows which microoperation happens when in terms of control signals

• Each state shows ► Which control signal is active ► Which state to go to next based on status signals


State


CurrentState

NextState



Register


Digital System Design Using FSM On paper

1. Start with the black box view and the textual input/output relationship of the digital system

2. Convert the textual input/output relationship to an operation diagram

3. Convert the operation diagram to a high-level state diagram with microoperations with the same number of states A diagram with finite number of states

4. From the high-level state diagram, obtain the datapath

5. From the high-level state diagram and the datapath, obtain the low-level state diagram

6. Decide about how to implement the control unit (sequencer) Hardwiring or microprogramming

• Hardwiring is acceptable if it is not a complex digital system• It is the case with the Ppm term project


Digital System Design Using FSM On paper

7. Implement the sequencer which is treated as a state machine The low-level state diagram (a state diagram with finite

number of states) shows which microoperation happens when• Each state shows ► Which control signal is active ► Which state to go to next based on status signals• Each state has a unique number to identify ►The state register value is the current state

Convert control signal and next state information of the low-level state diagram to sequencer hardware• Place the counter (state register) + decoder combination if

hardwiring is used• Obtain Expressions ► Obtain gate networks of the sequencer

Start implementing the circuits on computer7. Start drawing the schematics by using the design on

paper


Digital System Design Using FSM


The Textual Input/Output Relationship •Starting with the Reset state

• Input 8 numbers on K in eight successive clock periods• Determine sequence number of largest number• Output the sequence number of the largest number in 9th clock period and also a one clock period long valid signal

• Repeat these every 9 clock periods• Keep the output value at 0 until the next output value is calculated


The black-box view

DigitalSystem

8

K

Clock

3

OUT

Valid

Digital System Design Using FSM



Clock

N0 N1 N2 N3 N4 N5 N6 N7

Cp 1 Cp 2 Cp 3 Cp 4 Cp 5 Cp 6 Cp 7 Cp 8 Cp 9

Store it

Compare Compare& store & store

Compare& store

Compare& store

Compare& store

Compare& store

Compare& store

Output zero until the new result is obtained

Valid

9 clock period cycle

OutputSNUM

OutputSnum

OUT OUT


• After Reset• Input 8 numbers on K• Choose the largest• Determine sequence number (SNUM) of largest number• Output SNUM in 9th clock period and also a one clock period long valid signal

• Repeat every 9 clock periods• Keep the output value at 0 until the next output value is calculated

2. Convert the textual input/output relationship to an operation diagram

Store 1st number & store SNUM as 00

If K > 1st number then store K & update SNUM

1

2

If K > current largest then store K & update SNUM3



If K > current largest then store K & update SNUM

6


If K > current largest then store K & update SNUM

8 Output SNUM and Valid


3. Convert the operation diagram to a high-level state diagram with microoperations with the same number of states

A K ; B 00

If K > A then A K & B 1

1

OUT = B ; Valid = 1


2






3

4

5

6

7

8


3. Convert the operation diagram to a high-level state diagram with microoperations with the same number of states

RTL notation

RegisterA K ; B 00


1

OUT = B ; Valid = 1


2






3

4

5

6

7

8

Wires


4. Obtain the datapath from the high-level state diagram

A K ; B 00


1

OUT = B ; Valid = 1


2






3

4

5

6

7

8 Valid

Val

A

8

K

Store

8

Compare

Gt

Clock

AB

AGTB

31

3

B

StoreClock

SNUM

OUT

3-bit 2-to-1 MUX

3

3

0Sel

0


4. Obtain the datapath from the high-level state diagram

Registers

Remember : Registers need Store signals MUXes need Select signalsALUs need ALUcontrol signals Others may need Enable signalsSpecial signals may be needed

Snum signalsVal signal

A

8

K

Store

8

Compare

Gt

Clock

AB

AGTB

Valid

Val

31

3

B

StoreClock

SNUM

OUT

3-bit 2-to-1 MUX

3

3

0Sel

0


5. Obtain the low-level state diagram from the high-level state diagram and the datapath

Store = 1 ; SNUM = 0 ; Sel = 00

SNUM = 1 ; Sel = 0 If Gt == 1 then Store = 1

1

Val = 1 ; Sel = 1

2

3

4

5

6

7

8

SNUM = 2 ; Sel = 0 ; If Gt == 1 then Store = 1







6. Decide about how to implement the control unit (sequencer)

We use hardwiring since it is a very simple digital system

Data Unit

Control Unit

Gt

Store

Sel

3

OUT

Six control signals

One status signal

8

K

Valid

Val

SNUM

3

Clock

Clock


How do we implement the roundrobin trace of the states ?

0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8

We need a combination of ► 4-bit Up counter ► 3-to-8 DecoderTo keep track of the current state

7. Convert control signal and next state information of the low-level state diagram to sequencer hardware


We need a combination of ► 4-bit Up counter ► 3-to-8 DecoderTo keep track of the current state

7. Convert control signal and next state information of the low-level state diagram to sequencer hardware Place the counter+decoder combination if hardwiring is used

How do we implement the roundrobin trace of the states ?

0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8

We have to load 0 after the count is 8 !

4-b

it u

p c

ou

nte

r Q0

Q1

Clock 3-t

o-8

Decod

er

A0

A1

D0

D1

D2

D3

S0

S1

S2

S3

Q2 A2

E

Q3

D4

D5

D6

D7

S4

S5

S6

S7

S8

STC0

STC1

STC2

STC3

D0

D1

D2

D3

0

0

0

0

LDSTC3


Store is 1 when it is ► State 0 OR ► (state 1 OR state 2 OR state 1 OR state 3 OR state 4 OR state 5 OR state 6 OR state 7) AND Gt = 1


Obtain Expressions

Store is 1 when it is ► State 0 OR ► (NOT state 8) AND Gt = 1

Store = S0 + (S8Gt)



Place the counter+decoder combination if hardwiring is used• Obtain Expressions

• Obtain gate networks of the sequencer

Control Unit

Store

S8

Gt

S0

Store = S0 + S8Gt


Sel is 1 when ► It is state 8


Obtain Expressions

Val is 1 when ► It is state 8

Sel = S8

Val = S8


Sel

S8




Control Unit

Sel = S8 Val = S8

Val

S8


SNUM = 0 when it is state 0SNUM = 1 when it is state 1SNUM = 2 when it is state 2SNUM = 3 when it is state 2SNUM = 4 when it is state 4SNUM = 5 when it is state 5SNUM = 6 when it is state 6SNUM = 7 when it is state 7


Obtain Expressions

SNUM2 = STC2

SNUM1 = STC1

SNUM0 = STC0


SNUM2

STC2




Control Unit

SNUM2 = STC2 SNUM1 = STC1 SNUM0 = STC0

SNUM1

STC1

SNUM0

STC0


Control Unit


Digital System Design Using FSM Final digital system design on paper Start implementing the circuits on computer

Start drawing the schematics by using the design on paper


Datapath

Control Unit

Gt

Machine Play Block, Block 6 How is it designed ?

Machine player gathers information and then decides It must have inputs to gather information

• The number of inputs depends on the strategy• But, a few inputs are required for some strategies

It must have outputs to be able to play the game• The number of outputs depends on the strategy• But, a few outputs are required for any strategy


Block 6? ?

Machine Play Block, Block 6 How is it designed ?

Machine player gathers information and then decides It must have a subblock to gather information

• Information gathering is a major operation It must have a subblock to decide how to play

• Decision making is another major operation Any other subblock (major operation) ?


Block 6? ?

Machine Play Block, Block 6 The machine player is active in state 4 to think and

play/skip

Machine player stays at least one clock period in state 4 to gather information and decide

It stays more than one clock period if gathering information is done sequentially Because the information needed is not available all at once and

so must be collected one by one Collecting information in parallel requires a lot of hardware !

• The loop-back arrow indicates that more than once clock period is spent in state 4



play/skip


It stays more than one clock period if gathering information is done sequentially It collects the information in a number of clock periods and then

in one more clock period it plays The course web site machine player is like that

• It collects information for 8 clock periods and decides to play/skip in the 9th clock period !



play/skip The course web site machine player collects information for

8 clock periods and decides to play/skip in the 9th clock period !



play/skip


It stays more than one clock period if gathering information is done sequentially We need a controlling major operation to determine the

sequence of information gathering and then deciding !• A controller subblock is needed in addition to the information

gathering and decision making blocks ! • Since the machine player is a complex sequential circuit with a

controller then Block 6 is a tiny digital system itself



play/skip


A controller subblock is needed in addition to the information gathering and decision making blocks ! Since the machine player is a complex sequential circuit with a

controller then Block 6 is a tiny digital system itself


Sequencing Control Unit

Data UnitInformationGathering

DecisionMakingBlock 6


play/skip

It stays more than one clock period if gathering information is done sequentially

The required inputs if it stays more than one clock period Other inputs are needed to gather information


Block 6P2sturn

Clearp2ffs

P2clk

.

.

.


play/skip


If the information needed is available all at once, then the machine player stays one clock period in state 4 It collects the information and decides to play/skip in one clock

period !• The loop-back arrow is not needed then !

Today’s machine player is a simple one and so takes only one clock period !



play/skip


If the information needed is available all at once, then the machine player stays one clock period in state 4 We do not need a controlling major operation to determine the

sequence of information gathering and then deciding !• A controller block is not needed in addition to the information

gathering and decision making blocks ! • The machine player can be a combinational circuit that gathers

information and decides how to play in one clock period• The machine player can have sequential circuits to gather

information and decide how to play in one clock period• Because, the information needed to make a decision is available all

at once



play/skip


If the information needed is available all at once, then the machine player stays one clock period in state 4 Since the machine player is a combinational circuit, there are

only two subblocks in Block 6


InformationGathering

DecisionMaking

Block 6


play/skip

The machine player stays one clock period in state 4 There is no required input if it stays one clock period

But, other inputs are needed to gather information


Block 6

.

.

.

.


play/skip

How can the machine player indicate how it plays after collecting information and deciding (taking one or more clock periods) ?

It needs to have outputs to indicate its decision If it decides to play the random digit

• Output lines to indicate which position : P2SEL• An output line to indicate whether it is an addition or direct play :

P2add• An output line to indicate that it is playing, not skipping : P2played

If it decides to skip• An output line to indicate it is skipping : P2skip


Machine Play Block, Block 6 The machine player is active in state 4 to think and play/skip

How can the machine player indicate how it plays after collecting information and deciding (taking one or more clock periods) ?

It needs to have outputs to indicate its decision The required outputs whether it stays one clock period or longer

• Other outputs may be needed for the strategy, but not recommended


Block 6

P2SEL

P2add

P2played

.

.

4

P2skip


play/skip It needs to have outputs to indicate its decision

The required outputs whether it stays one clock period or longer


P2add is 1 if the machine player adds the random digit to a display

P2played is 1 if the machine player plays the random digit on a display

P2SEL has a 1 corresponding to the position played when the machine player plays the random digit

P2skip is 1 if the machine player skips the plays

Block 6

P2SEL

P2add

P2played

.

.

4

P2skip

Machine Play Block, Block 6 Let’s design a machine player slightly more complex than last week’s

machine player To design it we must have a playing strategy !

We develop a machine player strategy then !


Block 6? ?

A simple playing strategy !

There is a zero display ?

N

Play on the (rightmost) largest position with an addition (Action 2)

Y

Play on the (rightmost) zero position directly (Action 3)

RD > 3 ?

N Y

Play randomly using a 4-bit random value as described below (Action 0)

Leftmost bit of a 4-bit random value is 1 ?

N Y

Skip(Action 1)

Machine Play Block, Block 6 Let’s design a machine player slightly more complex than last

week’s machine player To design it we must have a playing strategy !

Let’s analyze the strategy• If there is a zero display, it plays on the zero display position directly• If the random digit is greater than 3, it plays on the largest display position with

an addition• If the leftmost bit of a 4-bit random value is 1, it skips• Otherwise, it plays on a position indicated by the middle two bits of the 4-bit

random value and whether to do an addition is indicated by the rightmost bit of the 4-bit random value such that if it is 0, it plays directly , else with an addition


Random Value

RV3 RV2 RV1 RV0

1 : Skip0 : Play

00 : Position 001 : Position 110 : Position 211 : Position 3

0 : Play directly1 : Play by adding

Block 6? ?

Machine Play Block, Block 6 Let’s design a machine player slightly more complex than

last week’s machine player To design it we must have a playing strategy !

How do we implement the random value ?• We will use the technique used for generating random digits for the

game• We will use a high speed modulo-10 up counter that will

continuously count such that we cannot predict its output !• The clock input will be the same as the clock input of the random

digit generation counter (U119) in Block 4 : Rdclk


Random Value

RV3 RV2 RV1 RV0

1 : Skip0 : Play



Block 6? ?

Machine Play Block, Block 6 To design it we must have a playing strategy !

We develop a machine player strategy then !


Block 6? ?

We need to collect the display values and random digit : DISP, RD

We input 16 bits : DISP 15 – DISP0

We input 4 bits : RD3 – RD0

We input a clock signal for the modulo-10 up counter : Rdclk


play/skip


If the information needed is available all at once, then the machine player stays one clock period in state 4 The DISP and RD lines are available all at once, so no need to

have more than one clock period



play/skip

The DISP information is available all at once, and so the machine player stays one clock period in state 4

We do not need a controlling major operation to determine the sequence of information gathering and then deciding ! The machine player hass a sequential circuit but it gathers

information and decides how to play in one clock period since the information collected (DISP and RD) is available all at once



play/skip

The DISP information is available all at once, and so the machine player stays one clock period in state 4

Since the machine player takes only one clock period to play, there are only two subblocks in Block 6



DecisionMaking

Block 6


play/skip

The machine player stays one clock period in state 4 It needs 16 DISP lines, 4 RD lines and Rdclk line to be input


Block 6

DISP16

RD4

Rdclk


play/skip

How can the machine player indicate how it plays after collecting information and deciding ?

It needs to have outputs to indicate its decision The required outputs

• P2SEL• P2add• P2played• P2skip


Block 6

P2SEL

P2add

P2played

.

.

4

P2skip


play/skip

The black box view of the machine player


Block 6

P2SEL

P2add

P2played

4

P2skip

We must also output 8 P2CODE lines to avoid unnecessary warnings

DISP16

RD4

Rdclk

Machine Play Block, Block 6 The design of the machine player that is completely

combinational The partitioning of the machine player block


Block 6P2SEL

P2add

P2played

4

DISP16


DecisionMaking

P2skip

P2CODE8

RD

4

Rdclk


combinational The Information Gathering Subblock


ZERODISP

Aposzero2M3

Already designed


M2 LRGDISPPOS2

DISP16

Rdclk RV Circuit RV4


combinational The Information Gathering Subblock


DISP16

ZERODISP

Aposzero

2M3

M2 LRGDISPPOS2

DISP16

RV CircuitRdclk RV4

Machine Play Block, Block 6 The design of the machine player that is

completely combinational The Information Gathering Subblock

The RV circuit is a modulo-10 up counter circuit• Xilinx has a modulo-10 up counter !• But, in order to gain insight into sequential circuit design,

we will implement the modulo-10 up counter by using a Xilinx modulo-16 up counter

• We will convert a Xilinx modulo-16 up counter to a modulo-10 up counter by using class notes !


RV CircuitRdclk RV4


combinational The Decision Making Subblock


DecisionMaking

ZERODISP

Aposzero

2

P2SEL

P2add

P2played

4

P2skip

P2CODE8

LRGDISPPOS2

RD4

RV4

Machine Play Block, Block 6 Generating P2skip output

We skip if There is no zero display AND The random digit < 4 AND The leftmost bit of RV is 1


DecisionMaking

ZERODISP

Aposzero

2P2played

P2skip

P2CODE8

LRGDISPPOS2

RD4

RV4

P2SEL

P2add

4

Machine Play Block, Block 6 Generating P2skip output

We skip if There is no zero display AND The random digit < 4 AND The leftmost bit of RV is 1


Aposzero is 0 AND

RD3 = 0 AND RD2 = 0 AND

RV3 is 1

P2skip = Aposzero RD3 RD2 RV3

AposzeroRD3

RD2RV3

P2skip

Random Digit < 4 ?

RD3 RD2 RD1 RD0 0 0 x x

Machine Play Block, Block 6 Generating P2played output

We play if we do NOT skip That is, we play if

• There is a zero display OR• The random digit > 3 OR• The leftmost bit of RV is 0


P2skip P2played

P2played = P2skip

Machine Play Block, Block 6 Generating P2add output

It plays with an addition if There is no zero display AND

• RD > 3 OR• RV 3 is 0 AND RV0 is 1


P2add = Aposzero ((RD3 + RD2) + (RV3 RV0))

Random Digit > 3 ?

RD3 RD2 RD1 RD0 x 1 x x

1 x x x





Random Digit > 3 ?


1 x x x

Random Value

RV3 RV2 RV1 RV0

1 : Skip0 : Play







P2add = Aposzero ((RD3 + RD2) + (RV3 RV0))

P2add

AposzeroRD3

RD2RV3

RV0

Random Digit > 3 ?


1 x x x

Machine Play Block, Block 6 Generating P2SEL outputs

P2SEL outputs depend on zero displays, RD and RV There are three choices for P2SEL lines

• If there is a zero display, it plays on the rightmost zero display position

• If there is no zero display AND RD > 3, it plays on the rightmost largest display position

• If there is no zero display AND RD < 4 AND RV3 is 0, it plays on the position indicated by the middle two RV lines

We need to select between these three choices• We need to use a MUX to select !

In general, if there are multiple actions that play the random digit (Action 0, Action 1, Action 2, etc.) then, the Decision Making Subblock must have a MUX !



P2SEL outputs depend on if there is a zero display There are three choices for P2SEL lines

• We need to use a MUX to select ! We need a 2-bit 4-to-1 MUX !


RV2

2-bit

4-to-1

MUX

RV1

A1

A0

P2POSSEL1Y1

P2POSSEL0Y0

LRGDISPPOS1C1

C0LRGDISPPOS0

Select1Sel1

ZERODISP1

ZERODISP0

D1

D0

Select0Sel0


We need a 2-bit 4-to-1 MUX ! We need two select lines !

• How do we generate Select1 and Select0 lines ?


RV2

2-bit

4-to-1

MUX

RV1

A1

A0

P2POSSEL1Y1

P2POSSEL0Y0

LRGDISPPOS1C1

C0LRGDISPPOS0

Select1Sel1

ZERODISP1

ZERODISP0

D1

D0

Select0Sel0



• How do we generate Select1 and Select0 outputs ?


Select1 Select0

When Aposzero = 1 then it is Action 3 Select1 = 1 AND Select0 = 1

When Aposzero = 0 AND RD > 3 then Action 2Select1 = 1 AND Select0 = 0

When Aposzero = 0 AND RD < 4 AND RV3 = 0 then Action 0Select1 = 0 AND Select0 = 0

11 : ZERODISP10 : LRGDISPPOS01 : Unused00 : RV





When Aposzero = 1

Action 3

Aposzero Action3

Generate Action lines first





When Aposzero = 0 AND RD > 3 Action 2

Action2Aposzero

RD3

RD2





Select1 = 1 AND Select0 = 1 when Action3 = 1

Select1 = 1 AND Select0 = 0 when Action3 = 0 AND Action2 = 1


Select1 Select0









Select1 = 1 when Action3 = 1 OR Action2 = 1

Action3

Action2Select1

Select1 = Action3 + Action2

Select1 Select0









Select0 = 1 when Action3 = 1 Select0= Action3

Select0Action3

Select1 Select0



P2SEL outputs depend on if there is a zero display There are three choices for P2SEL lines We need to select between three choices

• We need to use a MUX to select ! We need a 2-bit 4-to-1 MUX !

• The MUX outputs P2POSSEL lines We need to convert the 2-bit P2POSSEL lines to 4 P2SEL lines

• We need a 2-to-4 decoder !


P2POSSEL12-to-4

DecoderP2POSSEL0

I1

I0

P2SEL3Y3

P2SEL2Y2

P2SEL1Y1

P2SEL0Y0

Machine Play Block, Block 6 Generating P2CODE outputs

P2CODE outputs are always zero


0 P2CODE7

P2CODE6

P2CODE5

P2CODE4

P2CODE3

P2CODE2

P2CODE1

P2CODE0

0

0

0

0

0

0

0

DecisionMaking

ZERODISP

Aposzero

2

P2SEL

P2add

P2played

4

P2skip

P2CODE8

LRGDISPPOS2


combinational The Decision Making Subblock



combinational


Information Gathering Decision Making

Machine Playing Strategies Teams have to come up with a primary playing

strategy before they can design their machine player

A playing strategy is shown as a graph and consists of Conditions shown as ovals

• Game situations Actions shown as rectangles

• Playing the random digit on a display• Skipping the plays

The graph is NOT with respect to time The graph is with respect to game situations !

Teams must also have to come up with a secondary strategy to resolve game situations where the primary playing strategy results in multiple playable positions


Playing Strategy of Player 1 of Ppmmvsm Its Implementation


Play on the(rightmost)largest regular reward position (directly if equal)(Action 0)

A Machine Player Strategy Its Implementation


Play on the(rightmost)largest regularrewardposition(directlyif equal)(Action 0)

Skip

N y

Largest regular reward = 0 ?




Skip

NY

Play on the(rightmost)zero position(directlyif equal)(Action 1)

NY

Player 2 does not have (64)10 or more points & there is a position with a zero and RD is not zero


A Machine Player Strategy




Skip

N Y

Player 1 does not have (64)10 or more points & there is a position with a zero and RD is not zero

Play on the(rightmost)zero positiondirectly(if equal)(Action 2)

N

Y

Player 1 does not have (64)10 or more points & the largest regular reward is less than (64)10

N

Play on the(rightmost)largest position(directlyif equal)(Action 1)

Y

Playing Strategy of Term Project Its Implementation


SequencingInformation gathering

Decision making

Xilinx FFs, Registers, Counters Many do not have direct set and direct

clear inputs togetherTo avoid cases where both are active

They have either A direct set input

OrA direct clear input


Xilinx FFs, Registers, Counters Direct set and direct clear inputs

Asynchronous As we studied in class

• If the direct input is active, it affects the output immediately

The name of the FF, register, counter has a • “C” near the end if it is the direct clear input

► FDC : a D FF with an asynchronous direct clear input

• “P” near the end if it is the direct set (preset) input

► FDP : a D FF with an asynchronous direct set input


Xilinx FFs, Registers, Counters Direct set and direct clear inputs

Synchronous If the direct input is active, it affects the output when

there is the active clock edge The name of the FF, register, counter has an

• “R” near the end if it is the direct clear input ► FDR : a D FF with a synchronous direct clear input

• “S” near the end if it is the direct set input

► FDS : a D FF with a synchronous set input


Xilinx FFs, Registers, Counters Some of them have an additional input

Clock Enable (CE) The name of the FF, register, counter ends with an

“E” It controls the clock input

• If it is 1, the clock input gets the clock signal► It can be clocked (stored)

• If it is 0, the clock input gets 0► It cannot be clocked (cannot be

stored) The CE input is connected the Store signal of a register

FDCE : A D FF with an asynchronous direct clear input and a clock enable input



Xilinx FFs, Registers, Counters Clock Enable (CE)

FDCE : A D FF with an asynchronous direct clear input and a clock enable input

CLR CE D C Q1 X X X 0 (Store 0)0 1 0 0 (Store 0)

0 1 1 1 (Store 1)

0 1 X 0 NS0 0 X X NS

Xilinx FFs, Registers, Counters Clock Enable (CE)

The clock enable is often connected the “Store” signal


D

C

CLR

Qa

Reset

y0

CE is equivalent to

Storey0

Clock

a

Storey0

Clock

Reset

y0

This way of “gating the clock” is not recommended

Assignment by next lab Make sure that you have completed Experiment

1, Experiment 2, Experiment 3 and Experiment 4 The last day to submit Experiment 4 as a team is

March 28, 2014 The last day to submit Experiment 5 as a team is

April 4, 2014 It will be graded and returned by the following

lab Develop the playing strategy of your machine

player that will be designed starting next lab


Submit your Experiment 4 during a lab session !

Not during Open Lab Hours !

QUESTIONS ?


DigitalLogic and

State Machine Design

Read slides at the end to learn about the software, Project Manager, Schematic design and other related topics

Continue reading the Term Project handout

Think about the machine player strategy

Do not leave the lab before your partners finish► Help your partners

Make sure you have the LABS account and see the S driveMake sure you have installed WebPACK 12.4 on your laptop

Make sure you create a CS2204 folder on both

Today’s Individual Xilinx Work We will continue to study (analyze) the

term projectWe will use our knowledge of sequential

circuits to develop a machine player with two conditions and three actions

Help our partners complete today’s project

We will continue reading the Term Project handout

Also read slides at the end to learn about the software, Project Manager, Schematic design and other related topics


Today’s Individual Xilinx Lab Work

1. Open the ppm project in the exp4 foldera) Open the Project Manager and then

open the Ppm project in the exp4 folder

b) Look at the six Ppm schematicsc) Enter the team information to the schematics

if it has not been entered Save the schematic if the team information is

entered


Today’s Individual Xilinx Lab Work1. Open the ppm project in the exp4 folder

d) Make sure Experiment 1, Experiment 2, Experiment 3 and Experiment 4 are completed That is you have the following in Schematic 3 and a circuit in Schematic 6 on the next

slide :


Experiment 2

And the next slide

Experiment 1


d) Make sure Experiment 1, Experiment 2, Experiment 3 and Experiment 4 are completed That is you have the following on Schematic 6 and a circuit on Schematic 3o n the previous

slide :


Experiments 3 and 4

Today’s Individual Xilinx Lab Work1. Make sure Experiment 1, Experiment 2, Experiment 3

and Experiment 4 are completed That is on the screen you have the following :


Experiment 2

Experiment 1

Experiments 3 and 4

Make sure your circuits in blocks 3 and 6 follow the Term Project Check List handout


d) Make sure Experiment 1, Experiment 2, Experiment 3 and Experiment 4 are completed If they are not complete finish the designs by studying

• Lab 4 presentation for Experiment 1• Lab 5 presentation for Experiment 2• Lab 6 presentation for Experiment 3• Lab 7 presentation for Experiment 4• So that eventually Block 3 and Block 6 look like as follows :



Experiment 1

Experiment 2

Experiments 3 and 4

Today’s Individual Xilinx Lab Work2. Submit the Experiment 4 project after deciding

whose project is the best to submit Decide whose project on the team will be submitted

Block 3 and Block 6 must look like as follows :



Experiments 3 and 4

Experiment 1

Experiment 2

Today’s Individual Xilinx Lab Work2. Submit the Experiment 4 project after deciding whose

project is the best to submit Fill out a Term Project Check List handout before signaling to

the TA Block 3 and Block 6 must look like as follows :



Experiment 1

Experiment 2

Experiments 3 and 4

Today’s Individual Xilinx Lab Work3. By using Microsoft and Xilinx ISE create exp5

from the exp4 Remember that we must create a new project from an

earlier one by using Microsoft and Xilinx ISE We will experiment with the Ppm schematics

4. Open the Ppm project in exp55. Look at the six Ppm schematics6. If it has not been entered, place your

team info on the schematics Save the schematic if you enter the team

information


Today’s Individual Xilinx Lab Work7. Switch to schematic 48. Zoom into the upper right area, containing

the Random Digit Generation Subsubblock9. There is a Xilinx macro (a Xilinx Design

Block, XDB) with label U119 A BCD Up Counter, CD4CE, in the subsubblock

It counts up 0 to 9, inclusive• Its clock is always enabled (CE = 1)• Its direct clear input is always inactive (CLR = 0)

It implements the BCD Up counter similar to the modulo-12 counter implemented in class• We used a generic counter in class

See Block 4 on next three slides


Today’s Individual Xilinx Lab Work Ppm Block 4


Xilinx BCD UpCounter



Xilinx BCDUp Counter

Xilinx 4-bit registers which are stored 3 random digits when Grd (Get Random Digit) is raised to 1 by the control unit when BTN1or BTN2 is pressed



The Random Digit Clock at 192 Hz : Rdclk

Xilinx BCDUp Counter

Random Digit Counter outputs : RDC

Today’s Individual Xilinx Lab Work10. Analyze the BCD up counter to determine how it

is used Why is it used ?

In order to generate BCD random digits to play on the displays• These digits should not be predictable• They should give the impression that they are random• Generating a truly random digit is hard and out of our scope

We then generate BCD pseudo-random digits• If a number of conditions are satisfied it gives the impression

that the digits are random We will refer to it as random digit even though it is pseudo-random

The BCD up counter runs at a high speed and its output is stored as a random digit when BTN1 or BTN2 is pressed• The counter output stored is hard to predict by humans• If the human player presses BTN1 and BTN2 in irregular time

intervals, the digits stored seem random !


Today’s Individual Xilinx Lab Work10.Analyze the BCD up counter to

determine how it is used See the correspondence between this circuit

and your class notes The Xilinx counter is an Up counter and so does not

have the U/D input Its internal design is for BCD counting and so no

external gate is needed Do a Hierarchy Push and see how it is implemented

by Xilinx See the internal circuit on next slide


Today’s Individual Xilinx Lab Work10. Analyze the BCD up counter to determine how it is used

See the correspondence between this circuit and your class notes


No T FFs !

Only

D F

Fs &

m

an

y g

ate

s !

Today’s Individual Xilinx Lab Work10. Analyze the BCD up counter to determine how

it is used Close the schematic of the internal circuit of the Xilinx

BCD up counter It counts up at the rate of Rdclk (Random digit clock)

Rdclk is generated in the Timing Subblock of schematic 2 Rdclk is derived from a 32-bit frequency divider in Block 2 Rdclk is derived from Q1 which is one of the outputs of a 16-

bit Xilinx binary counter , CB16CE, U67, that is one of the two counters of the 32-bit frequency divider

Q1 has the frequency of 192 Hz ► The counter counts at a high rate

The BCD counter output is stored on a register (U120) when a random digit is needed !• It is highly improbable that we can guess what its output will

be when we store it



it is used It counts up at the rate of Rdclk (Random digit clock)

Only three outputs of the counter, RDC1, RDC2 and RDC3 are stored on a Xilinx 4-bit register, FD4CE, U120 The counter value is stored on the register as the random

digit when Grd (Get random digit) is 1 The rightmost output of the counter, RDC0, is not stored on

the register ! If this output is connected to the register, the random digit

is always odd (1, 3, 5, 7 and 9) It is a problem of the Xilinx software and so to get around it

the register is connected Q7 from U67 in schematic 2 Outputs RDC1 and RDC3 are also used by the Code Digit

generation circuit, M1, in Block 4 to generate code digits



it is used It counts up at the rate of Rdclk (Random digit clock) Search for the inputs and outputs of the counter

Confirm that component U67 in Block 2 generates the clock signal Q1 which is renamed as Rdclk by using a buffer

Confirm that component U120 in Block 4 uses outputs RDC3, RDC2 and RDC1

Confirm also that component M1 in Block 4 uses outputs RDC3 and RDC1

To search for a wire click on Edit -> Find… or press Ctrl+F to find the wire with a name Select the Nets mode Select With Name Enter Rdclk and then press Enter The software will automatically switch to schematic 2 that has

the wires with this name and show the wires in yellow


Today’s Individual Xilinx Lab Work11. Perform functional simulations on the Xilinx

BCD counter You will confirm the input/output relationship of the

counter Select the wires as follows

• RDCLK line as the input• RDC as the four output lines



BCD counter You will confirm the input/output relationship of the

counter RDCLK line as the input RDC as the four output lines

Start functional simulations Click on Restart on the upper tool bar so that the

starting time is 0 seconds

Change the observation duration time to 150ns during the simulations


Today’s Individual Xilinx Lab Work11. Perform functional simulations on the Xilinx BCD counter

In order to simulate the counter, a clock signal must be input to the counter. Follow the steps to generate a clock signal as an input

• Right click on the Rdclk and select Force Clock…



BCD counter In order to simulate the counter, a clock signal must

be input to the counter. Follow the steps to generate a clock signal as an input

• The Define Clock window will pop up to be entered values • Enter the following values in the window

► Leading Edge Value is 1 ► Trailing Edge Value is 0 ► Period is 10ns

• After you enter the values the Define Clock window will look like the one on the next slide





1 means the first edge of the simulation is a positive edge

0 means the second edge of the simulation is a negative edge

Duty cycle is 50% means 50% of the clock period is 1 and 50% of the clock period is 0

The clock period duration is 10ns

Therefore, the clock frequency is 100 MHz


BCD counter In order to simulate the counter, a clock signal must

be input to the counter. Follow the steps to generate a clock signal as an input :

• Click OK to close the Define Clock window


Today’s Individual Xilinx Lab Work11.Perform functional simulations on the

Xilinx BCD counter Click on the icon to do a simulation for

150ns The simulator starts with the initial value of 0

• See the next slide that shows the simulation for 15 clock periods


Today’s Individual Xilinx Lab Work The simulation window for the Xilinx BCD

Counter


0 1 2 3 4 5 6 7 8 9 0 1 2 3 4

The first edge is a positive edge


Click on the icon to continue the simulation for 150ns more The simulation below shows the values for 30 clock periods


Today’s Individual Xilinx Lab Work12. Draw the gate network of the BCD Up Counter by using

your class notes in schematic 6 You will implement the RV outputs by using a Xilinx counter

and as few gates as possible You will need to design a circuit to generate the load signal for

the up counter to count up to 9, not to 15 First draw the complete schematic on a sheet of paper by

using your class notes Compare your schematic with your partners’ and make sure

the schematic is correct before you start the design on your computer

Draw the schematic on your computer based on your design on the sheet You will use the Add Symbol button on the leftmost side (or

Ctrl+M) to get the component list You will use the Add Wire button on the leftmost side (or

Ctrl+W) to draw wires To rotate components right press ctrl-r Note, wires cannot be rotated

But, by pulling from one end of a wire, it can be rotated !


Today’s Individual Xilinx Lab Work12. Draw the gate network of the BCD Up Counter by using your

class notes in schematic 6 Move up and left the M2 and M3 circuits developed last two weeks

to create space You can move M2 and M3 circuits closer to each other to create more

space Do not change the Decision Making Subblock circuit from last week Draw a divider line to separate the RV circuitry from M2 and M3

circuits Draw a longer divider vertical line to separate the Information

Gathering Subblock from the Decision Making Subblock


Implement BCD Up counter in this area

Make sure your circuits in Block 6 follow the Term Project Check List handout

Today’s Individual Xilinx Lab Work12. Draw the gate network of the BCD Up Counter

by using your class notes in schematic 6 You will use a Xilinx 4-bit modulo-16 counter called

CB4CLE It is a Loadable counter with asynchronous Clear,

Synchronous Load and Clock Enable• Here is the meaning of the characters in its name C : It is a counter B4 : 4-bitBinary counter, i.e. a divide-by-16 or modulo-16

counter C : Asynchronous clear L : Loadable synchronously E : Clock Enable

• Its clock is positive-edge triggered• See the next slide for a larger view



by using your class notes in schematic 6 A Xilinx 4-bit modulo-16 counter


Today’s Individual Xilinx Lab Work12.Draw the gate network of the BCD Up

Counter by using your class notes in schematic 6

You will use a Xilinx 4-bit modulo-16 counter called CB4CLE Observe the internal structure of the Xilinx CB4CLE

• Do a Hierarchy Push and see how it is implemented ► It has 4 loadable T FFs ! ► See internal implementation of Xilinx CB4CLE on the next slide


Today’s Individual Xilinx Lab Work Observe the internal structure of the Xilinx CB4CLE


Xilinx T FFsFTCLEX


by using your class notes in schematic 6 You will use a Xilinx 4-bit modulo-16 counter called

CB4CLE Observe the internal structure of the Xilinx FTCLEX

• Do a Hierarchy Push and see how it is implemented ► It is a Xilinx specific Toggle/Loadable FF with asynchronous Clear, Synchronous Load and Clock Enable ► It has 6 inputs and only one output ! T (Toggle) as the regular Toggle input D (Data) to load data L (Load) to indicate when to load CE (Clock Enable) C (Clock) which is positive-edge triggered CLR (Clear) to asynchronously clear the FF

• See the next slide for a larger view



by using your class notes in schematic 6 A Xilinx FTCLEX FF



by using your class notes in schematic 6 In order to count Up and load, it has a T FF that is

called FTCLEX Observe the internal structure of the Xilinx FTCLEX FF

• Do a Hierarchy Push and see how it is implemented ► It does not have a T FF ! ► See internal implementation of the Xilinx FTCLEX FF on the next slide


Today’s Individual Xilinx Lab Work Xilinx FTCLEX FF is not implemented as a T FF


Xilinx D FF

Xilinx MUX


by using your class notes in schematic 6 How can we design a modulo-10 up counter by using a

Xilinx CB4CLE counter ? Let’s start with the simplest inputs to work on

• The counter will count all the time and so its Clock Enable (CE) input is always enabled by connecting it to 1 permanently

• The counter will never be cleared and so its Clear (CLR) input will be disabled by connecting it to 0 permanently

• The counter uses Rdclk and so its Clock (C) input will be connected to Rdclk




Xilinx CB4CLE counter ? The Load circuitry will detect (9) on the four outputs and

generate a 1 output since the CB4CLE has an active-high Load input

You will use an AND gate to detect number 9 in Unsigned binary (1001)• In class, number 12 in Unsigned Binary (1100) is detected• The detection circuit requires that two counter outputs be

inverted• In order to avoid using inverters, the AND4B2 gate is used

which internally inverts two of the inputs• Label the output of this AND gate Loadrvc, meaning “Load

RV Counter”




Xilinx CB4CLE counter ? When the counter is loaded, the value to load is

(0000)• In class, we loaded (0001) to the counter

All D inputs are permanently connected to 0 The outputs are labeled as RV3, RV2, RV1 and RV0




Xilinx CB4CLE counter ? First draw the complete schematic on a sheet of paper by

using your class notes and Xilinx component figures Compare your schematic with your partners and make

sure the schematic is correct before you start the design on your computer




Xilinx CB4CLE counter ? First draw the complete schematic on a sheet of paper by

using your class notes Then, draw the schematic based on your design on

the sheet You will use the Add Symbol button on the leftmost

side (or Ctrl+M) to get the component list• You will use the Add Wire button on the leftmost

side (or Ctrl+W) to draw wires• To rotate components right press ctrl-r• Note, wires cannot be rotated

But, by pulling from one end of a wire, it can be rotated !

Label the wires (inputs and outputs) based on your analysis in part (9)



your class notes in schematic 6 Label the components

• We have to have a consistent way of labeling components

• We have to label the components in one subblock and then label the components in another subblock, sweeping the subblocks from left to right and top to bottom

• Therefore, we need to label the Information Gathering Subblock components and then label the components in the Decision Making Subblock

• Relabel the 2-bit 4-to-1 MUX as U306, 2-to-4 decoder as U307 and the inverter as U308 in the Decision Making Subblock

• Label the components of BCD Up counter starting at U304

• The last label of BCD Up counter implementation will be U305



your class notes in schematic 6 Label the components

• At this point where the Decision Making Subblock is the same as the Experiment 4 circuit, component labels in Block 6 are from U289 through U308

Determine that there is no component labeled above the last component count of Experiment 5

How can I search for a component in the schematics ?• To search for components click on Edit -> Find… or press

Ctrl+F to find the component with a label• Select the Instance mode• Select With Name• Enter a label number and then press Enter

Save the schematic See modified Block 6 on the next slide



your class notes in schematic 6


Modulo-10 Upcounter implemented

The Decision Making Subblock is the same as Experiment 4 for the time being !

Today’s Individual Xilinx Lab Work

13.Do a schematic check on the new design The schematic check is to see if there

are simple errors to catch on all schematics Select Tools Check Schematic

• The Console panel will indicate that there are no errors but three warnings

See the next slide


Today’s Individual Xilinx Lab Work13. Do a schematic check on the new design

The schematic check is to see if there are simple errors to catch on all schematics Read the bottom portion of the Console panel for warnings and

correct them if there are any• There are five warnings !

The five warnings are OK since we do not need these outputs We will ignore these unneeded output warnings and decide there

is nothing to correct Next Slide explains why we ignore them



The schematic check is to see if there are simple errors to catch on all schematics

You might wonder how the project works if wires are not connected to outputs nor inputs

• The Xilinx software integrates all the schematics during its implementation

• If the wire names are the same, it would not matter where the wires are placed, the software connects them internally

Schematic checks do not catch all the errors That is why after the Schematic checks we have to

perform Functional simulations Xilinx IMPLEMENTATIONs Timing simulations


Today’s Individual Xilinx Lab Work14. Perform functional simulations on this BCD Up

counter in schematic 6 to verify that it is working

Note that to do functional simulations, you must perform a synthesis

You will see that there are 130 warnings, many of them new due to copying this project from exp4ReRun the synthesis so that you eliminate most of the new warningsThere will be 60 warnings after the second synthesis


Today’s Individual Xilinx Lab Work14. Perform functional simulations on this BCD Up

counter in schematic 6 to verify that it is working

You will confirm the input/output relationship of the counter Select the wires as follows

• RDCLK line as the input• LOADRVC as the output line• RV as the four output lines


Today’s Individual Xilinx Lab Work14.Perform functional simulations on this

BCD Up counter in schematic 6 to verify that it is working

See part (11) about supplying the periodic clock signal

Note that to catch possible mistakes we have to observe the Loadrvc line and verify that it is 1 when the counter reaches 9 each time

Click on the icon to do a simulation for 150ns The simulator starts with the initial value of 0



Today’s Individual Xilinx Lab Work The simulation window for the Xilinx BCD

Counter


0 1 2 3 4 5 6 7 8 9 0 1 2 3 4

Loadrvc is 1when the count is 9


Today’s Individual Xilinx Lab Work14. Perform functional simulations on this BCD Up counter in

schematic 6 to verify that it is working Click on the icon to continue the simulation for 150ns

more The simulation below shows the values for 30 clock periods



Today’s Individual Xilinx Lab Work14.Perform functional simulations on this

BCD Up counter in schematic 6 to verify that it is working

If you catch errors correct them on schematic 6

Before completing this step, make sure the circuit in schematic 6 is beautified and the schematic is saved again


Today’s Individual Xilinx Lab Work15. Modify the Decision Making Subblock to

complete the implementation of the new machine playing strategy as explained on slides 59 to 92

Modify the Decision Making Subblock schematic Draw the new schematic by following slides 69 to 92

• Appropriately label the components such that the highest components label is U315

• Note that there are two buffers used but their labeling is different

Beautify your circuits Save the schematic See modified Block 6 on the next slide


Today’s Individual Xilinx Lab Work15. Modify the Decision Making Subblock to complete the

implementation of the new machine playing strategy as explained on slides 59 to 92



There will be 0 errors and 5 warnings The 5 warnings are the same as in step 13 above Since all these five warnings are acceptable there is

nothing to correct


Today’s Individual Xilinx Lab Work17.Perform functional simulations on the

new design to verify that it is working In order to do logic simulations, perform a

synthesis The number of synthesis warnings is 58 Perform logic simulations to observe that the machine

player follows the playing strategy


Today’s Individual Xilinx Lab Work18. Perform a Xilinx IMPLEMENTATION

• Xilinx IMPLEMENTATION is required after a schematic is changed• When we indicate IMPLEMENTATION we mean Synthesis,

Implement Design and Generate Programming File steps we see on the Project Navigator window

• Since we changed schematic 6 we have to do a Xilinx IMPLEMENTATION

• Xilinx IMPLEMENTATIONS are needed for three reasons Catching more errors not discovered via schematic

checks and functional simulations as the software analyzes the schematics

Catching even more errors by doing timing simulations possible after the Xilinx IMPLEMENTATION

Creating a new bit file



• Xilinx IMPLEMENTATION maps the schematics to the FPGA resources (CLBs and wires) If the mapping is complete then there are no errors but

there can be warnings• Mapping allows real components to be considered,

hence timing simulations• Xilinx IMPLEMENTATION consists of 3 major steps

• Synthesis to translate the schematic to a netlist file after converting the schematic to a VHDL file

• Implement Design which consists of• Translate, Map, Place & Route

Generate Programming File to generate the bit file



Click on Design Summary (out of date) to be able to see the number of errors and warnings

Right click on Generate Programming File and select Rerun All We will do the Synthesis, Implement Design and Generate Programming

File steps altogether• Even though we already did the synthesis, we will do it again to get

practice on this as we will do it many times Wait until the IMPLEMENTATION completes

• If it does not complete, it stops at one of the steps We have to read the errors on the Design Summary panel

Once completed, there are no marks next to any one of the steps just performed



For the current IMPLEMENTATION we will get 0 Errors 60 Warnings 4% Slice utilization

Read the warnings by clicking on 60 Warnings on the Design Summary window whether or not the Xilinx IMPLEMENTATION completes

• We often check Design Summary for the warnings and the FPGA utilization Most warnings we check are in the Synthesis section The FPGA utilization is lower than expected if there are

errors or warnings that must be corrected In Experiment 5, the number of warnings will be 60

This number will change depending on the experiment Note that out of 60 warnings, 58 of them are Synthesis

warnings and 2 are Place & Route warnings


Today’s Individual Xilinx Lab Work18.Do a Xilinx IMPLEMENTATION

Make sure there are no errors Always read the warnings !


Today’s Individual Xilinx Lab Work19. Perform timing simulations on the BCD Up Counter

Timing simulations are based on delays for the components and signal propogations on the wires

Xilinx ISE records these delay only if we perform a Generate Post-Place & Route Simulation Model

We select this option by expanding the Place & Route step


Click here


Timing simulations are based on delays for the components and signal propogations on the wires

Xilinx ISE records these delay only if we perform a Generate Post-Place & Route Simulation Model

Since the Generate Post-Place & Route Simulation Model step has a question mark next to it, we have to perform the step by double clicking on it


Double click on this line


When it stops the Generate Post-Place & Route Simulation Model step has a check mark which means we can do timing simulations



• Double click here, on the Simulate Post-Place & Route Model step to start the timing simulation



• To simulate the counter we need to select its inputs and outputs

• We will select one input and five outputs as in the case functional simulations in part (15)

• We search for Rdclk and see that a number of results are shown in the “Search Results” panel• We select the one which is Rdclk

• We search for Loadrvc and see that two results are shown in the “Search Results” panel• We select the one which is Loadrvc

• We enter RV to select RV3, RV2, RV1 and RV0• We see that the software lists a number of items related to RV,

including the four wires we will select• We select RV3, RV2, RV1 and RV0 for our timing simulations !



• To simulate counter we need to select its inputs and outputsMake sure you select the signals as follows :



Click on Restart on the upper tool bar so that the starting time is 0 seconds

Change observation duration time from 1 microseconds to 2 microseconds

Click on the icon to do a simulation for 2 microseconds The simulator starts with the initial value of 0



Today’s Individual Xilinx Lab Work19. Perform timing simulations on the BCD

Up Counter In order to simulate the counter, a clock

signal must be input to the counter. Follow the steps to generate a clock signal as an

input• Enter the following values in the Define Clock window

► Leading Edge Value is 1 ► Trailing Edge Value is 0 ► Period is 100ns

• After you enter the values the Define Clock window will look like the one on the next slide




• Enter the following values in the Define Clock window


Today’s Individual Xilinx Lab Work19. Perform timing simulations on the BCD Up

Counter



0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9



Zoom into the leftmost side and determine how long it takes for the counter to change its output from 0000 to 0001 It takes 0.645 nanoseconds to change Remember that the clock period duration is 100ns

• The counter output change takes place in less than 1% of the clock period duration !



Zoom into other areas and measure the time delay For example it takes 0.641 nanoseconds for the counter to change its

output from 0001 to 0010 Remember again that the clock period duration is 100ns

• The counter output change takes place in less than 1% of the clock period duration !


0.641ns



output from 0111 to 1000


0.646ns

Notice the glitch on the loadrvc line



output from 1001 to 0000


1.61ns


Click on the icon to continue the simulation for 2 microseconds more The simulation below shows the values for 40 clock periods



Today’s Individual Xilinx Lab Work20.Download the Ppm project to the FPGA

chip and play the game and to verify that the schematic works correctly

In order to test the circuit fast you can input random digits directly to the machine player After you play, when the state is 3, leave one of

switches SW7 – SW4 on to signal you will input the random digit

Use switches SW3 – SW0 to select a random digit value

Press push button BTN2 so the machine player starts with the random digit you input

Turn off the signaling switch (one of SW7 – SW4) before you press push button BTN3 to play




Play the game and verify that the random values are not If it the random values are not random looking, inspect your circuit in Block 6 and correct the circuit




If it does not work, inspect your circuit in Block 6 and correct the circuit

If you are sure your Experiment 5 circuit is correct then Copy your experiment 5 folder from the S drive to

your laptop Make sure you refresh your memory about

the game rules and how to play the game


Today’s Individual Xilinx Lab Work21.Ensure again that all circuits related to

Experiment 1, Experiment 2, Experiment 3 and Experiment 4 are complete

Including Component labels Well drawn circuits

22.Help your partners complete today’s project


Today’s Individual Xilinx Lab Work23. Submit your exp5 project once everyone

completes the design If all the team members have finished the new

machine player design, they will decide whose project will be submitted

Students will fill out a Term Project Check List handout so that feedback can be given to them by the grading TAs

Students will signal to a TA who will copy their project

24. Develop the playing strategy of your machine player that will be designed starting next lab


Today’s Individual Xilinx Lab Work25.Continue Reading the Term Project

handout Study and play the other two types of the

Ppm game to think more about the our machine player’s strategy Human vs. human : ppmhvsh Machine vs. machine : ppmmvsm

• Think about the playing strategy of the machine player that will be designed

Also read slides at the end to learn about the software, Project Manager, Schematic design and other related topics


Understand Critical WiresRD : 4 bits

The random digitR1D : 4 bits

Next random digitR2D : 4 bits

The random digit after next random digitDISP : 16 bits

They represent the four position displays In Hex

DISP15-DISP12 : The leftmost position display, PD3 DISP11-DISP8 : position display PD2, etc

NPDISP : 16 bits The result of RD to each display digit

In Hex NPDISP15-NPDISP12 : The leftmost position, PD3, value + RD NPDISP11-NPDISP8 : Position display PD2 value + RD

NPSELDISP : 4 bits Selects one of NPDISP display values

In Hex


Understand Critical WiresBRWD : 4 bits

Basic reward In Hex

The digit played and also minimum points earned It is selected from RD or NPSELDISP

Based on how the player played : Directly or with an addition

Brwdeqz : 1 bit BRWD is zero when it is 1

PDPRD : 4 bits Display overflow bits after addition

Pdprd : 1 bitThe display overflow bit of the position played

Selplyr : 1 bit The current player

If it is 0, it is the human player, otherwise, it is the machine player


Understand Critical WiresP1SEL : 4 bits

The position played by the human playerP2SEL : 4 bits

The position played by the machine playerPSEL : 4 bits

Position Select bits of current playerENCPSEL : 2 bits

The number of the position playedEQ : 4 bits

The equality of the four displays to the digit playedNSD : 2 bits

The number of similar digits, i.e. the adjacency information of the position played

RWD : 8 bits The regular reward points calculated based on adjacencies

In Unsigned Binary CODERWD : 8 bits

The code reward points calculated based on the code digits In Unsigned Binary


Understand Critical WiresP1PT : 8 bits

Player 1 points In Hex

P2PT : 8 bits Player 2 points

In Hex

PT : 8 bits The points of the current player

In Hex

NPT : 8 bits New player points for the current player

In Hex

Ptovf : 1 bitThe points overflow

if it is 1, the new player points is above (255)10


Understand Critical WiresP1add : 1 bit

Player 1 adds when it is 1

P2add : 1 bit Player 2 adds when it is 1

Add : 1 bit The current player adds when it is 1

P1skip : 1 bit Player 1 skips when it is 1

P2skip : 1 bit Player 2 skips when it is 1

P1played : 1 bit Player 1 has played when it is 1

P2played : 1 bit Player 2 has played when it is 1


Understand Critical WiresDISPSEL : 2 bit

Selects one of four values for displays 00 Selects position displays (displays that RD is played on) 01 Selects player points 10 Selects next two random digits 11 Selects discovered code digits

Add : 1 bitShows that the current player has selected to add

Stp1pt : 1 bit Store Player 1 points

Stp2pt : 1 bit Store Player 2 points

Grd : 1 bit Signals to generate a new random digit

The random digit counter output is stored as P2RD while P2RD and P1RD are shifted to generate the new P1RD and RD

Bpds : 1 bitBlink one or all displays slowly

Bpdf : 1 bitBlocks a display fast after a display overflow


Understand Critical WiresClear : 1 bit

Clear FFs, registers, counters, etc. during reset in Block 2, Block 4 and Block 6 so that it can play again

Clearp2ffs : 1 bit Clears Player 2 FFs, counters and registers

Clff : 1 bit Clears FFs in Block 2 so that the next player can play if there

is no overflowS1 : 1 bit

State 1 where when it is 1, the Ppm is in state 1P2sturn : 1 bit

Signals that Player 2 has the turn It is 1 when the Ppm is in state 4

Sysclk : 1 bit System clock of the operation diagram at 6 Hz

P2clk : 1 bit The clock signal of Player 2 at 48 Hz

Rdclk : 1 bit The random digit counter clock at 192 Hz


experiment 5 lab 8 digital logic and state machine design as you wait for the lab to start : is your...

Documents

digital systemsthis

digital systemsthe data

term project handoutcs

term project pages

ppmthe term project

term projectpolytechnic

digital systeman iphone

digital systema computer