cs 2204 spring 2007 experiment 5 lab 9. experiment 5 lab 9cs 2204 spring 2007 page 2 experiment 5...

CS 2204 Spring 2007CS 2204 Spring 2007Experiment 5Lab 9

Experiment 5 Lab 9

CS 2204 Spring 2007

Experiment 5 Lab 9 Outline Presentation

Digital Design Conventions Using Digital Product Development

A brief description of Ppm Block 4 and Block 5

Individual workDeveloping non-core circuits of Ppm Block 5

Using Experiment 5 Design Checks

New handout Experiment 5 Design Checks

Experiment 5 Lab 9

CS 2204 Spring 2007

Presentation Digital Design Conventions

Digital Circuit Printing Conventions The printout must be readable

• Labels, component names, symbols, etc. If the circuit is large, it must be printed on several

pages• The sheets must be attached to each other• Lines, labels, etc. must be continuous from one sheet

to the next

Experiment 5 Lab 9

CS 2204 Spring 2007

Digital Design Conventions Digital Circuit Printing Conventions

CS2204 Related Part 1 of Experiment 5 Design Checks

• The team info on the lower right corner is ► Line 1 : the name of the student who designed the schematic +

a partner’s name ► Line 2 : partner(s)’ name(s) ► Line 3 : CS2204, Section name, Spring 2007

Experiment 5 Lab 9

CS 2204 Spring 2007

Digital Design Conventions Digital Circuit Drawing Conventions

Part 2 of Experiment 5 Design Checks Remember to beautify the circuit before submitting

it• Place components of a (sub)block next to each other

and separate (sub)blocks from each other• Only horizontal and vertical wires drawn• No unnecessary wire turns• No Unnecessary line tanglings• No need to draw long wires

► One can draw short wires and name them

• Components form horizontal and vertical columns• Wires are not drawn over components, buffers, pads

Experiment 5 Lab 9

CS 2204 Spring 2007

Digital Design Conventions Logic Circuit Design Conventions

Part 3 of Experiment 5 Design Checks If a component has multiple outputs, make sure you

use the needed ones Outputs should not be short-circuited unless they

are tri-state If an output is not needed, leave it unconnected

Experiment 5 Lab 9

CS 2204 Spring 2007


Part 4 of Experiment 5 Design Checks Do not forget to save schematics

• Then, do a Xilinx IMPLEMENTATION to have the changes affect the output

From time to time clear the Implementation data on the Project Manager window by following

• Project -> Clear Implementation Data After clearing the data, next time you do a Xilinx

IMPLEMENTATION, reenter the IMPLEMENTATION options

Experiment 5 Lab 9

CS 2204 Spring 2007


Part 5 of Experiment 5 Design Checks Perform simulations

• If an output value is Hi-Z during simulation, make sure it is correct

Read the Implementation Log file and work on the warnings and errors listed

• If you do back to back Xilinx IMPLEMENTATIONs, the new IMPLEMENTATION data is appended to the end

Experiment 5 Lab 9

CS 2204 Spring 2007

Xilinx Project Development Steps Develop the schematic

DESIGN the schematic Design blocks, (sub)blocks

• Place the components and wires Do integrity TESTs TEST the schematic via functional simulations MODIFY the schematic to correct an error

Do a Xilinx IMPLEMENTATION It maps the components to the CLBs of the chip

Do timing simulations to TEST the schematic It generates the bit file

Download the bit file to the FPGA and test the design on the board

It programs the chip

What are thesecomponents ?

Develo

pm

ent

Cycl

e o

n

Com

pute

rs

Develo

pm

ent

Cycl

ew

ith F

PG

A c

hip

s

Experiment 5 Lab 9

CS 2204 Spring 2007

CS2204 Components Available components for a new chip

Generic componentsLectures, homework, exams

Xilinx components Labs

Gates Flip-flopsPopular digital circuits Gates Flip-flopsPopular digital circuits

ANDORNOTNANDNOR…

DJKTSR…

ADDerComparatorMultiplexerDeMuxDecoderEncoderALUCounterRegister…

ANDORNOTNANDNOR…

DJK

ADDerComparatorMultiplexerDeMuxDecoderEncoderALUCounterRegister…

Try not to use these components

Use Xilinx macros as much as possible

Lab design

Experiment 5 Lab 9

CS 2204 Spring 2007

Designing a New Chip DESIGN

2) Implement each circuiti. One or more Xilinx Design Blocks, XDBs or Xilinx

non-programmable macros (not gates and FFs) implement the circuit ? A few gates and FFs here and there ?• If yes, draw the schematic and move to the TEST

step

ii. One or more Programmable Xilinx macros implement the circuit ? A few gates and FFs here and there ? If yes, draw the schematic, program the macros and

move to the TEST step

CS2204

Experiment 5 Lab 9

CS 2204 Spring 2007

Designing a New Chip DESIGN

2) Implement each circuitiii. Simple enough to be designed quickly using

Switching Theory (less than 5 inputs or less than 5 FFs) so a few gates and/or FFs needed ?• If yes, draw the schematic and move to the TEST

step

iv. The circuit can be licensed ?• If yes, borrow it, place it and move to the TEST step

v. If no to all the above questions, go back to step 1(b) to partition it further or repartition one level up, two levels up,,, or, all the way up

CS2204

Experiment 5 Lab 9

CS 2204 Spring 2007

The Ppm Term Project The black-box view

A large number of FFs are used !The Ppm is partitioned based on major

operations First partitioning of the digital system

• Control Unit• Data Unit

Second partitioning (Data Unit partitioning)• Interfacing to the input/output devices• Handling human player’s play• Controlling display operations based on game rules• Calculating new player points• Determining the machine player play

Figure 1. The Ppm black box view.

Ppm11 19

From the input devices To the output devices

Experiment 5 Lab 9

CS 2204 Spring 2007

The Ppm Digital System Partitioning

Input/Output Devices

Control Unit, Block 1

Play Check Block

Figure 6. Block partitioning of the Ppm term project.

(Block 1)

Block 4

Machine Play BlockBlock 6

Datapath(Data Unit)

(Experiment 6)

Core

means the blockis partially core

Human Play Block

Block 3 Core

Points Calculation

Block, Block 5

(Experiment 5)

Input/

Block,

Block 2

Output

Core

**Core

M1M2

M3

Experiment 5 Lab 9

CS 2204 Spring 2007

The Ppm Data Unit Block 4, Play Check Block

It has three major operations Storing the displays, player points and random digit

Position Displays, Points Storage and Random Digit Generation Subblock

Handling display manipulations Display Manipulation Subblock

Determining display digits similar to the digit played Similar Digit Determination Subblock

Block 426 52

Experiment 5 Lab 9

CS 2204 Spring 2007


Block 426 52

Experiment 5 Lab 9

CS 2204 Spring 2007


Position Displays, Points Storage & Random Digit GenerationSubblock

Display ManipulationSubblock

Similar DigitDeterminationSubblock

Equal to Lines

EQ

Experiment 5 Lab 9

CS 2204 Spring 2007


Important outputs of the block DISP : 16 lines for the position displays

• 4 bits each for a display to show the value in Hex P1PT : 8 lines for the Player 1 points in Unsigned Binary P2PT : 8 lines for the Player 2 points in Unsigned Binary RD : 4 lines for the random digit in BCD PSEL : 4 lines for the position select signals of the current

player• It is either P1SEL or P2SEL

ENCPSEL : 2 lines that encode PSEL in Unsigned Binary BRWD : 4 lines for the digit played and also the minimum

reward points that can be earned EQ : 4 lines one for each display indicating if the

corresponding display is equal to the digit played Pdprd : A single line indicating if the current play resulted

in a display overflow

Experiment 5 Lab 9

CS 2204 Spring 2007

The Ppm Data Unit Block 5, Points Calculation Block

Main goal : calculate the new points for the current player

Experiment 5 targets Block 5 There are two black boxes, macros, to implement

M1 and M2

Block 532 19

How can we implement the block ?

Experiment 5 Lab 9

CS 2204 Spring 2007


Get pencil and paper On paper study the input/output relationship

32 inputs and 19 outputs

Block 532 19

Experiment 5 Lab 9

CS 2204 Spring 2007


Outputs of the block NSD : 2 bits indicating the adjacency of the current play in

Unsigned Binary• The Control Unit uses it to allow the current player to request

a random reward or to play again if there is an adjacency• The machine player at the course web site uses it to

determine the highest adjacency position RWD : 8 bits indicating the reward points earned by the

current player in Unsigned Binary• The Machine Play Block uses it to make a decision on how to

play the random digit NPT : 8 bits indicating the new points of the current player

in Unsigned Binary• The Play Check Block stores it on the corresponding player

points register Ptovf : 1 bit indicating if the current player has exceeded

the points limit and so has won the game• It is an overflow bit used by Block 2 to store it on a FF

► Then, the Control Unit uses it the following clock period to stop the game

Experiment 5 Lab 9

CS 2204 Spring 2007


There is another major operation left to implement for Ppm : machine playing

These two major operations may need to be tightly coupled if the machine player is highly intelligent

The course web site term project does not tightly couple them !

A real game chip might have to tightly couple them !Block 6 will be discussed next week !

Block 6 is designed in Experiment 6

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development How can we design Block 5 ?

Try to implement the block immediately According to the Digital Product Development rules,

we need to search the Xilinx component library to see

• If this whole block can be implemented by one or more non-programmable macros and perhaps with a few additional gates? ► No, this is not possible !

• If this whole block can be implemented by one or more programmable macros & perhaps with a few additional gates ? ► No, this is not possible !

• If this whole block is simple enough to be implemented by gates right away? ► No, this is not possible !

• Then we have to partition this block into a few subblocks based on the major operations of this block

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Points Calculation Block partitioning

There are several different ways to partition it, one of them is based on the following major operations :

Determine the adjacency of the position played Determine the reward points of the position played Determine new player points by adding the reward

points to the current player points Therefore, Block 5 has three subblocks

Adjacency Subblock : core circuit Reward Calculation Subblock : core circuit Points Subblock : Macro M1 and Macro M2

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Points Calculation Block partitioning

M1

PointsSubblock

M2

AdjacencySubblock

CoreReward CalculationSubblock

Core

AdjacencyNSD

RewardPointsRWD

New Player PointsNPT

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Points Calculation Block partitioningAdjacency

Reward points

New playerpoints

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development The Adjacency Subblock

Determines the adjacency of the position played On paper study the input/output relationship

7 inputs and 2 outputs• The adjacency of the position played by the current player is output

► The adjacency is in the Unsigned Binary format

A completely combinational circuit

The operation table of the Adjacency Subblock

How can we implement the subblock ?

Adjacency

Brwdeqz ENCPSEL NSD

1 X 00

0 00 Use EQ1, EQ2 and EQ3




Experiment 5 Lab 9

CS 2204 Spring 2007


Example for position 0 If EQ1 = EQ2 = EQ3 = 0 NSD = 00 If EQ1 = 1 & (EQ2 = 0 or EQ3 = 0) NSD = 01 If EQ1 = EQ2 = 1 & EQ3 = 0 NSD = 10 If EQ1 = EQ2 = EQ3 = 1 NSD = 11

The operation table of the Adjacency Subblock

Adjacency

Brwdeqz ENCPSEL NSD

1 X 00





Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subblock immediately According to the Digital Product Development rules, we need to

search the Xilinx component library to see• If this whole subblock can be implemented by one or more non-

programmable macros and perhaps with a few additional gates ? ► No, this is not possible !

• If this whole subblock can be implemented by one or more programmable macros and perhaps with a few additional gates ? ► No, this is not possible !

• If this whole subblock is simple enough to be implemented by gates right away ? ► No, this is not possible !

• Then we have to partition this subblock into a few subsubblocks based on the major operations of this subblock

Adjacency

Brwdeqz ENCPSEL NSD

1 X 00





Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Adjacency Subblock partitioning


Obtain the unencoded adjacency for all four display from EQ lines

• The Adjacent Similar Digits Subsubblock

Select one of them as the unencoded adjacency based on the played position number (ENCPSEL)

• The Unencoded Adjacency Subsubblock

Encode the Unencoded adjacency in Unsigned Binary to obtain the encoded adjacency to be used easily by other circuits (NSD)

• The Encoded Adjacency Subsubblock

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Adjacency Subblock partitioning

FourUnencodedadjacencies

Unencodedadjacencyof the positionplayed

Encodedadjacencyof the positionplayed

Adjacency

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Adjacent Similar Digits Subsubblock

Obtains the unencoded adjacency for all four display from EQ lines

On paper study the input/output relationship 4 inputs and 12 outputs

• Three outputs show the unencoded adjacency for a display ► They indicate the number of identical adjacent digits in a row for that position

The adjacency information is unencoded

Digit playedBRWD

2

Display Positions Before the PlayDISP7204

EQ Outputs0100 From Table 26

How can we implement the subsubblock ?

Experiment 5 Lab 9

CS 2204 Spring 2007


Obtains the unencoded adjacency for all four display from EQ lines

Three outputs show the unencoded adjacency for a display• They indicate the number of identical adjacent digits in a row for that

position ► The adjacency information is unencoded

Digit playedBRWD

2


RDP3EQ OutputsRDP3EQ2, RDP3EQ1, RDP3EQ0

100

From Table 26


000


100


000

EQ Outputs0100

Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subsubblock immediately According to the Digital Product Development rules, we need to

search the Xilinx component library to see• If this whole subsubblock can be implemented by one or more non-

programmable macros and perhaps with a few additional gates ? ► No, this is not possible !

• If this whole subsubblock can be implemented by one or more programmable macros and perhaps with a few additional gates ? ► Yes, this is possible if we use 12 Xilinx 16x1-bit ROMs

One ROM for each output as we will see later in the semester !

This does not seem a simple and quick implementation !

► Therefore, we decide not to accept this solution !

• If this whole subsubblock is simple enough to be implemented by gates right away ? ► Yes, this is possible since we have only four inputs and we can quickly get the expressions by using textual input/output relationships

Our design will have gate networks then !

Experiment 5 Lab 9

CS 2204 Spring 2007


Let’s try to get the expressions for the RDP3EQ lines There is one adjacency if only position 2 is identical to BRWD and

so only one line (RDP3EQ2) is 1• That is if EQ2 = 1, there is one adjacency

► We then say that RDP3EQ2 = EQ2

There are two adjacencies if position 2 AND position 1 are identical to BRWD and so two lines (RDP3EQ2 and RDP3EQ1) are 1

• That’s is if EQ2 = 1 AND EQ1 = 1 ► We then say that RDP3EQ1 = EQ2 EQ1

There are three adjacencies if position 2 AND position 1 AND position 0 are identical to BRWD and so three lines (RDP3EQ2, RDP3EQ1 and RDP3EQ0) are 1

• That’s is if EQ2 = 1 AND EQ1 = 1 AND EQ0 = 1 ► We then say that RDP3EQ2 = EQ2 EQ1 EQ0

RDP3EQ2

RDP3EQ1RDP3EQ0

Experiment 5 Lab 9

CS 2204 Spring 2007


The current implementation uses gates and buffers Buffers are used to rename wires

• Xilinx does not allow giving multiple names to a wire

BUFEQ2

EQ1

EQ0

RDP3EQ2

RDP3EQ1

RDP3EQ0

Figure 22. The RDP3EQ circuit in the Adjacent Similar Digits Subsubblock.

AND2AND2

Circuit for RDP3EQ

RDP3EQ2 = EQ2

RDP3EQ1 = EQ2 EQ1

RDP3EQ0 = EQ2 EQ1 EQ0

Experiment 5 Lab 9

CS 2204 Spring 2007


The current implementation uses gates and buffers Draw the gates and buffers on paper Draw the output wires of these components

• This will help figure out what to connect to their inputs Draw inputs of the gates and buffers appropriately Move the design from paper to the computer Label the components

Experiment 5 Lab 9

CS 2204 Spring 2007


Components used6 Xilinx 2-input AND gates, AND26 Xilinx buffers, BUFTotal : 12 components used

On paper, after you determine the components to use► Draw the components► Draw the output wires of the components► Draw the input wires of the components

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Unencoded Adjacency Subsubblock

Selects one of them as the unencoded adjacency based on the played position number (ENCPSEL)


• The adjacency for the played position is output ► The adjacency information is unencoded


Brwdeqz ENCPSEL UENCNSD

1 X 000

0 00 RDP0EQ

0 01 RDP1EQ

0 10 RDP2EQ

0 11 RDP3EQ

Experiment 5 Lab 9

CS 2204 Spring 2007


Selects one of them as the unencoded adjacency based on the played position number (ENCPSEL)

The adjacency for the played position is output• The adjacency information is unencoded

Digit playedBRWD

2



100


000


100


000

Position playedENCPSEL

3

Digit played is not zeroBrwdeqz

0

Adjacency of Position 3 is output : RDP3EQUNENCNSD = 100

Brwdeqz ENCPSEL UENCNSD

1 X 000

0 00 RDP0EQ

0 01 RDP1EQ

0 10 RDP2EQ

0 11 RDP3EQ

Experiment 5 Lab 9

CS 2204 Spring 2007


Example for different ENCPSEL combinations If ENCPSEL is 00 output RDP0EQ If ENCPSEL is 01 output RDP1EQ If ENCPSEL is 10 output RDP2EQ If ENCPSEL is 11 output RDP3EQ

Realize that this is a select (multiplexing) operation We select one out of four so it is a 4-to-1 MUX When we select, we output three bits, so it is a 3-bit 4-to-1

MUX If Brwdeqz is 1, the outputs are zero

• Brwdeqz can be used as the enable/disable signal to the MUXesBrwdeqz ENCPSEL UENCNSD

1 X 000

0 00 RDP0EQ

0 01 RDP1EQ

0 10 RDP2EQ

0 11 RDP3EQ

Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subsubblock immediately According to the Digital Product Development rules, we

need to search the Xilinx component library to see• If this whole subblock can be implemented by one or more

non-programmable macros and perhaps with a few additional gates ? ► Yes, this is possible !

Brwdeqz

ENCPSEL UENCNSD

1 X 000

0 00 RDP0EQ

0 01 RDP1EQ

0 10 RDP2EQ

0 11 RDP3EQTable 27. The operation table of the Unencoded Adjacency Subsubblock

Experiment 5 Lab 9

CS 2204 Spring 2007


According to the Digital Product Development rules, we need to search the Xilinx component library to see if there is such a 3-bit 4-to-1 MUX and if there is not, determine how to implement it with smaller MUXes

No 3-bit 4-to-1 Xilinx MUX, but 2-bit and 1-bit 4-to-1 MUXes• One 2-bit 4-to-1 MUX : X74_153 • One 1-bit 4-to-1 MUX : M4_1E

Draw the MUXes Draw the output wires of the MUXes

This will help figure out what to connect to the MUX inputs Draw Brwdeqz to the Enable inputs of the MUXes appropriately

We need to use an inverter to invert Brwdeqz for one of the MUXes

• The M4_E has an active high Enable input !

Draw the select lines of the MUXes by using ENCPSEL lines Draw the PDxPRD inputs to the MUX data inputs appropriately

Distribute them to the inputs, do not cluster them ! Move the design from paper to the computer Label the components

Experiment 5 Lab 9

CS 2204 Spring 2007


Components used1 Xilinx inverter, INV1 Xilinx 4-to-1 MUX, M4_1E1 Xilinx 2-bit 4-to-1 MUX, X74_153Total : 3 components used

Brwdeqz

ENCPSEL UENCNSD

1 X 000

0 00 RDP0EQ

0 01 RDP1EQ

0 10 RDP2EQ

0 11 RDP3EQ


Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Encoded Adjacency Subsubblock

Encode the Unencoded adjacency to obtain the encoded adjacency to be used easily by other circuits (NSD)


• The adjacency for the played position is output ► The adjacency information is in the encoded format

The adjacency is in the Unsigned Binary format UNENCNSD NSD

000 00100 01

110 10111 11


Experiment 5 Lab 9

CS 2204 Spring 2007


Example for different UNENCNSD combinations If UNENCNSD is 000 output 00 since there is no 1 If UNENCNSD is 100 output 01 since there is only one 1 If UNENCNSD is 110 output 10 since there are two 1s If UNENCNSD is 111 output 11 since there are three 1s

Realize that this is nothing but adding the ones of UNENCNSD !

How can we add the 1s ? We can do that by using an adder !

• Since we add three bits, it is a Full Adder !UNENCNSD NSD

000 00100 01

110 10111 11

Experiment 5 Lab 9

CS 2204 Spring 2007



search the Xilinx component library to see • If the whole subsubblock can be implemented by one non-

programmable macros and perhaps with a few additional gates ? ► No Full Adder, but 4-bit Adders We can use a single 4-bit Adder as a Full Adder

Xilinx will remove the hardware for the unneeded bits of the Adder

UNENCNSD NSD

000 00100 01

110 10111 11

Experiment 5 Lab 9

CS 2204 Spring 2007


Draw the Adder Draw the output wires to the outputs of the Adder

This will help figure out what to connect to the Adder inputs

Draw UNENCNSD lines to the Adder inputs appropriately Distribute them to the inputs, do not cluster them !

Move the design from paper to the computer Label the component

Components used1 Xilinx 4-bit ADDer, ADD4Total : 1 component used

On paper, after you determine the component to use► Draw the component► Draw the output wires of the component► Draw the input wires of the component

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development The Reward Calculation Subblock

Determines the reward points of the position played On paper study the input/output relationship

11 inputs and 8 outputs• The reward points for the current player are output

► The reward points is in the Unsigned Binary format

Input Operation

New NSD and/or BRWD and/or Rdrwdsel

Determine the amount of reward points for the current player. The reward points, RWD, has eight bits to reward up to (255)10 points

Table 28. The operation table of the Reward Calculation Subblock


Reward points

Experiment 5 Lab 9

CS 2204 Spring 2007


The operation table on the previous slide looks too complex so we get a different looking operation tableBRWD NSD Rdrwdse

lRWD

0 X X 0

Non-zero 00 X BRWD

Non-zero 01 0 2*BRWD

Non-zero 01 1 2*BRWD + RDRWD





From Table 29 : A Different Operation Table for the Reward Calculation Subblock.

Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subblock immediately According to the Digital Product Development rules, we need to

search the Xilinx component library to see• If this whole subblock can be implemented by one or more non-

programmable macros and perhaps with a few additional gates ? ► No, it looks like this is not possible !

• If this whole subblock can be implemented by one or more programmable macros and perhaps with a few additional gates ? ► No, it looks like this is not possible !

• If the whole subblock is simple enough to be implemented by gates immediately ? ► No, it looks like this is not possible !

• Then we have to partition this subblock into a few subsubblocks based on the major operations of this subblock

BRWD NSD Rdrwdsel RWD

0 X X 0

Non-zero 00 X BRWD







Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development The Reward Calculation Subblock partitioning

There are several different ways to partition it, one of them could be based on the following major operations :

Compute the regular reward based on the digit played and adjacency

• Multiplication by 1, 2, 4 and 8 to calculate the regular reward ► To multiply by 1, 2, 4 and 8, we need shifting by 0, 1, 2 and 3 bit positions

Generate random reward• A random reward between 0 and (63)10 is generated

Calculate the final reward• If necessary add the regular reward and the random reward

BRWD NSD Rdrwdsel

RWD

0 X X 0

Non-zero 00 X BRWD







Experiment 5 Lab 9

CS 2204 Spring 2007


Shall we use a multiplier ? No !

• We remember that we studied multiplication by 2, 4 and 8 in class

► It can be done with just wires : we do not need gates !

► Since we have four different multiplications, we need to select

one of the multiplication results and output it !

► To output the result of the multiply by 2, 4, and 8 (to shift

by 1, 2 and 3 bit positions), we use multiplexing !

► Therefore, we change our mind and revisit the partitioning !

Shall we have separate subsubblocks for random reward generation and final reward calculation ?

No !• The random reward generation circuit can output 0, if it is to be ignored• The final reward calculation circuit is a single adder then !• We can combine the two circuits into one subsubblock !

► Therefore, we change our mind and revisit the partitioning !

Experiment 5 Lab 9

CS 2204 Spring 2007


The new partitioning of the subblock Compute the regular reward based on the digit

played and adjacency• Regular Reward Determination Subsubblock

Calculate the final reward• Final Reward Determination Subsubblock

► The random reward is also generated

Experiment 5 Lab 9

CS 2204 Spring 2007


Regular Reward

Final Reward

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Regular Reward Determination Subsubblock

Computes the regular reward based on the digit played and adjacency


• Eight outputs show the regular reward ► Based on the digit played and the adjacencyBRWD NSD Brwdeqz REGRWD

0 X 1 0

Non-zero

00 0 BRWD

Non-zero

01 0 2*BRWD

Non-zero

10 0 4*BRWD

Non-zero

11 0 8*BRWDFrom Table 30 : A Operation Table for the Regular Reward Determination Subsubblock.How can we implement the subsubblock ?

8

Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subblock immediately According to the Digital Product Development rules, we

need to search the Xilinx component library to see• If this whole subsubblock can be implemented by one or more

non-programmable macros and perhaps with a few additional gates ? ► Yes, this is possible ! This subblock can be implemented by non-programmable Xilinx macros, MUXes, and one additional gate

• To output the result of the multiply by 1, 2, 4, and 8 (to shift by 0, 1, 2 and 3 bit positions), we use multiplexing ! ► 8-bit 4-to-1 MUX The shifting is done via wires on the MUX inputs

It is 4-to-1 since we choose one out of four multiplication results

It is an 8-bit one since for each choice we have eight bits

BRWD NSD Brwdeqz REGRWD

0 X 1 0

Non-zero 00 0 BRWD




8

Experiment 5 Lab 9

CS 2204 Spring 2007


There is no Xilinx macro that implements this 8-bit 4-to-1 MUX immediately

But, four 2-bit 4-to-1 Xilinx MUXes implement the large MUX• Four 2-bit 4-to-1 MUXes : X74_153

How do we output REGRWD = 0 when BRWD =0 ?• Use Brwdeqz as the disabling input

Do we need four MUXes ? No !

• We see that the largest regular reward is (120)10 = 8 * (15)10

► To represent (120)10 we need only seven bits ► The leftmost bit, bit 7, is 0 all the time !

• We see that bit 6 is 1 only if BRWD is NOT zero AND there are three adjacencies AND the leftmost bit of BRWD is 1 ► If Brwdeqz is 0 AND NSD is 11 AND BRWD3 is 1 ► This is a single 4-input AND gate with an inverted input !

We then use • Three 2-bit 4-to-1 MUXes : X74_153 • One 4-input AND gate

BRWD NSD Brwdeqz REGRWD

0 X 1 0

Non-zero 00 0 BRWD




8

Experiment 5 Lab 9

CS 2204 Spring 2007


Draw the MUXes on paper Draw and label the output wires of the MUXes

This will help figure out what to connect to the MUX inputs Draw the select lines of the MUXes by using the NSD

lines Connect the appropriate BRWD lines and 0s to the MUX

data inputs Distribute them to the inputs, do not cluster them !

Draw the single-gate circuit for the bit 6 output Draw the single wire connected to 0 for bit 7 Move the design from paper to the computer Label the components

Experiment 5 Lab 9

CS 2204 Spring 2007


Components used3 Xilinx 2-input 4-to1 MUXes, X74_1531 Xilinx 4-input AND gate, AND4B1Total : 4 components used


Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Final Reward Determination Subsubblock

Calculates the final reward The random reward is also generated


• Eight outputs show the reward points for the current player

Clrtoplay Rdrwdsel

Sysclk Operation

1 X X RWD = REGRWD + 0

0 0 X RWD = REGRWD + 0

0 1 RWD REGRWD + RDRWDFrom Table 31 : A Operation Table for

the Final Reward Determination Subsubblock.


Experiment 5 Lab 9

CS 2204 Spring 2007



need to search the Xilinx component library to see• If this whole subsubblock can be implemented by one or more

non-programmable macros and perhaps with a few additional gates ? ► No, this is not possible !

• If this whole subsubblock can be implemented by one or more programmable macros and perhaps with a few additional gates ? ► No, it looks like this is not possible !

• If the whole subsubblock is simple enough to be implemented by gates immediately ? ► No, it looks like this is not possible !

• Then we have to partition this subsubblock into a few subsubblocks based on the major operations of this subblock

Clrtoplay

Rdrwdsel

Sysclk Operation



0 1 RWD REGRWD + RDRWD

Experiment 5 Lab 9

CS 2204 Spring 2007


partitioning There are several different ways to partition it, one of

them is based on the following major operations : Generate random reward

• Random Reward Generation Subsubsubblock• A random reward between 0 and (63)10 is generated

Calculate the final reward ► Reward Addition SubsubsubblockClrtopla

yRdrwdsel Sysclk Operation



0 1 RWD REGRWD + RDRWD

Experiment 5 Lab 9

CS 2204 Spring 2007


partitioning

Reward Addition Subsubsubblock

Core

8

RWD

8

RDRWD

8

REGRWD

Random Reward DeterminationSubsubsubblock

Rdclk Sysclk Clrtoplay

Core

8

RDRWD

Rdrwdsel

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Random Reward Determination Subsubsubblock

Generates random reward On paper study the input/output relationship

4 inputs and 8 outputs

Random Reward DeterminationSubsubsubblock

Rdclk Sysclk Clrtoplay

Core

8

RDRWD

Clrtoplay

Rdrwdsel Sysclk RDRWD

1 X X 0

0 0 X Not Stored

0 1 Store the output of theRandom reward

counter

Rdrwdsel

How can we implement the subsubsubblock ?

Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subsubsubblock immediately According to the Digital Product Development rules, we need to

search the Xilinx component library to see• If this whole subsubsubblock can be implemented by one or more


• If this whole subsubsubblock can be implemented by one or more programmable macros and perhaps with a few additional gates ? ► No, it looks like this is not possible !

• If the whole subsubsubblock is simple enough to be implemented by gates immediately ? ► No, it looks like this is not possible !

• Then we have to partition this subsubsubblock into a few subsubblocks based on the major operations of this subsubsubblock

Experiment 5 Lab 9

CS 2204 Spring 2007


partitioning There are several different ways to partition it, one of

them is based on the following major operations : Count at a high speed

• Random Reward Counter Subsubsubsubblock ► An 8-bit counter runs at a high speed continuously

Store the output of the random reward counter as the final reward

• Store Random Reward Subsubsubsubblock ► The register is cleared when Clrtoplay is 1

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Random Reward Counter Subsubsubsubblock

Counts up at a high speed On paper study the input/output relationship

1 input and 8 outputs

Random Reward CounterSubsubsubsubblock

Rdclk

Core

8

RDRWDCNT

Rdrwdsel Operation

0 Do Not Count up

Count Up

How can we implement the subsubsubsubblock ?

Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subsubsubsubblock immediately According to the Digital Product Development rules, we need

to search the Xilinx component library to see• If this whole subsubsubsubblock can be implemented by one or

more non-programmable macros and perhaps with a few additional gates ? ► Yes, this is possible ! This subblock can be implemented by a non-programmable Xilinx macro, an 8-

bit counter, CB8CE The counter is never cleared and its clock is

always enabled

Draw the counter on paper Draw and label the output wire (the bus) of the counter

• This will help figure out what to connect to the counter inputs Connect to the CE, C and CLR lines of the counter the 1, Rdclk

and 0 lines, respectively Move the design from paper to the computer Label the components

Experiment 5 Lab 9

CS 2204 Spring 2007


Components used1 Xilinx 8-bit Up Counter, CB8CETotal : 1 component used


Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Store Random Reward Subsubsubsubblock

Stores the output of the random reward counter as the final reward


Clrtoplay

Rdrwdsel Sysclk RDRWD

1 X X 0

0 0 X Not Stored

0 1 Store RDRWDCNT

Store Random RewardSubsubsubsubblock

Sysclk Clrtoplay

Core

8

RDRWD

Rdrwdsel8

RDRWDCNT

How can we implement the subsubsubsubblock ?

Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subsubsubsubblock immediately According to the Digital Product Development rules, we need to

search the Xilinx component library to see• If this whole subsubsubsubblock can be implemented by one or more

non-programmable macros and perhaps with a few additional gates ? ► Yes, this is possible ! This subblock can be implemented by two non-programmable Xilinx macros, two 4-bit

registers, FD4CE The register is stored when Rdrwdsel is 1 AND there is a

positive edge on Sysclk We store only six bits of RDRWDCNT since we have to generate a random reward between 0

and (63)10

The remaining two inputs are connected 0 permanently The register is cleared when Clrtoplay is 1

Draw the registers on paper Draw and label the output wires of the registers

• This will help figure out what to connect to the register inputs Connect to the D, CE, C and CLR lines of the counter by using the

RDRWDCNT, Rdrwdsel, Sysclk and Clrtoplay lines, respectively Move the design from paper to the computer Label the components

Experiment 5 Lab 9

CS 2204 Spring 2007


Components used2 Xilinx 4-bit Registers, FD4CETotal : 2 components used


Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Reward Addition Subsubsubblock

Calculate the final rewardOn paper study the input/output relationship

16 input and 8 outputs

Operation

RWD = RDRWD + REGRWDReward Addition Subsubsubblock

Core

8

RWD

8

RDRWD

8

REGRWD

How can we implement the subsubsubblock ?

Experiment 5 Lab 9

CS 2204 Spring 2007


Try to implement the subsubsubblock immediately According to the Digital Product Development rules, we need

to search the Xilinx component library to see• If this whole subsubsubblock can be implemented by one or

more non-programmable macros and perhaps with a few additional gates? ► Yes, this is possible ! This subblock can be implemented by a non-programmable Xilinx macro, an 8-

bit adder, ADD8 The adder always adds and its CIN input is

always 0

Draw the adder on paper Draw and label the output wires of the adder

• This will help figure out what to connect to the adder inputs Connect to the A and B inputs of the adder by using the

REGRWD and RDRWD lines Move the design from paper to the computer Label the component

Experiment 5 Lab 9

CS 2204 Spring 2007


Components used1 Xilinx 8-bit Adder, ADD8Total : 1 component used


Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development The Points Subblock : Macro M1 and Macro M2

Determines new player points by adding the reward points to the current player points


• The new points for current player and the points overflow are output ► The player points in the Unsigned Binary format

Input Operation

New Selplyr or P1PT or P2PT

Select the current player points from P1PT and P2PT and output as PT

New RWD or PT

Add to the points of the current player (PT), the reward (RWD) to generate the new player points (NPT). Generate the points overflow bit (Ptovf) which is 1 if PT + RWD is greater than (255)10Table 32. The operation table of the Points Subblock.


New playerpoints

Experiment 5 Lab 9

CS 2204 Spring 2007



need to search the Xilinx component library to see• If this whole subblock can be implemented by one or more


• If this whole subblock can be implemented by one or more programmable macros and perhaps with a few additional gates ? ► No, it looks like this is not possible !

• If the whole subblock is simple enough to be implemented by gates immediately ? ► No, it looks like this is not possible !

• Then we have to partition this subsubsubblock into a few subsubblocks based on the major operations of this subblock

Input Operation



New RWD or PT Add to the points of the current player (PT), the reward (RWD) to generate the new player points (NPT). Generate the points overflow bit (Ptovf) which is 1 if PT + RWD is greater than (255)10

Experiment 5 Lab 9

CS 2204 Spring 2007



Select the points of the current player• The Select Player Points Subsubblock

Add the current player points and the reward points to obtain the new player points and the points overflow bit

• The Points Addition Subsubblock

Input Operation



New RWD or PT

Add to the points of the current player (PT), the reward (RWD) to generate the new player points (NPT). Generate the points overflow bit (Ptovf) which is 1 if PT + RWD is greater than (255)10

Experiment 5 Lab 9

CS 2204 Spring 2007


Points Subblock partitioning

Figure 25. The Points Subblock (M2) partitioning.

8P1PTSelply r

8P2PT

8

PT

8PT

8RWD

P t o v f

8

NPT

Points Addition Subsubblock Select Player Points Subsubblock M 1 M 2

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Select Player Points Subsubblock : Macro M1

Selects the points of the current player On paper study the input/output relationship

17 inputs and 8 outputs• Eight outputs are the points of the current player

► The points is in Unsigned Binary

Selplyr PT

0 P1PT1 P2PT


Experiment 5 Lab 9

CS 2204 Spring 2007


Try different Selplyr combinations and realize that this is a select (multiplexing) operation

If Selplyr is 0 output P1PT If Selplyr is 1 output P2PT We select one out of two so it is a 2-to-1 MUX When we select, we output eight bits, so it is an 8-

bit 2-to-1 MUXSelplyr PT

0 P1PT

1 P2PT

Experiment 5 Lab 9

CS 2204 Spring 2007



need to search the Xilinx component library to see if there is such an 8-bit 2-to-1 MUX and if there is not, determine how to implement it with smaller MUXes

• No 8-bit 2-to-1 Xilinx MUX, but 4-bit 2-to-1 MUXes

► Two 4-bit 2-to-1 MUXes : X74_157

Draw the MUXes on paper Draw and label the wires connected to the outputs of the

MUXes• This will help figure out what to connect to the MUX inputs

Draw and label the wires connected to the inputs of the MUXes

Move the design from paper to the computer Label the components

Selplyr PT

0 P1PT

1 P2PT

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5, Points Calculation Block Development Points Addition Subblock : Macro M2

Adds the current player points and the reward points to obtain the new player points and the points overflow bit


• Eight outputs are the new points of the current player ► The points is in Unsigned Binary

• One output is the points overflow output ► If the new player points exceeds (255)10, it is 1

OperationNPT = RWD + PT

Ptovf = 1 if RWD + PT > (255)10


Experiment 5 Lab 9

CS 2204 Spring 2007


We see that this is an 8-bit Unsigned Binary addition since the player points is an unsigned number

During the addition, we also generate the overflow bit• We know that there is an overflow if the carryout of the 8-bit

unsigned adder is 1

Operation

NPT = RWD + PT Ptovf = 1 if RDW + PT >

(255)10

Experiment 5 Lab 9

CS 2204 Spring 2007



need to search the Xilinx component library to see if there is such an 8-bit Unsigned Binary Adder and if there is not, determine how to implement it with smaller Adders

• Yes, there is an 8-bit Unsigned Binary Adder : ADD8

Draw the Adder on paper Draw and label the output wires to the outputs of the

Adder• This will help figure out what to connect to the Adder inputs

Draw the inputs of the 8-bit Adder Move the design from paper to the computer

• Connect buses as described on slide 120• Make sure the buses are type None

Label the components

Operation

NPT = RWD + PT Ptovf = 1 if RDW + PT >

(255)10

Experiment 5 Lab 9

CS 2204 Spring 2007

Block 5 Development The timetable for the rest of the semester

Students are suggested they complete the Experiment 5 project today (lab 9)

Students will submit the Experiment 6 project which will include the implementation of two blocks, Block 5 and Block 6

The deadline : Friday, April 27, 2007

You can complete Block 5 later,

but, complete it today to have

more time for th

e Machine Play

Block

Experiment 5 Lab 9

CS 2204 Spring 2007

Before Starting the Design of Block 5 Move circuits in Blocks 3, 4, 5 and 6 to

their appropriate placesAfter all circuits are in their proper places,

label the components Last Xilinx component label in Block 5 : U150

U150

Experiment 5 Lab 9

CS 2204 Spring 2007

After you determine components to use► Draw the components► Draw the output wires of the components► Draw the input wires of the components

Do not leave the lab before your partners finish► Help your partners complete today’s project

Read slides on the Ppm, Project Manager, Schematic design and other related topics

Continue reading the Term Project handout

Think about the machine player strategy

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Work We will develop (implement) the non-core

portion of Block 5 the term projectWe will replace the Select Player Points

Subsubblock , Macro M1 with our own circuitsWe will replace the Points Addition

Subsubblock , Macro M2 with our own circuits

Read slides on the Ppm, Project Manager, Schematic design and other related topics

Help your partners complete today’s project

Continue reading the Term Project handout

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work1. Copy the exp4 folder and paste it in the

cs2204 folder as the exp5 folder 2. Open the Ppm project in exp53. Look at the six Ppm schematics

If you copy a project completely as we did and then open its schematics, the schematics will be all Non-Project

Therefore, close all these schematics and close the schematics window

Then, open the schematics one by one on the Project Manager window, by double clicking on the schematic name on the upper left side

4. Place your team info on the schematics on schematic 1 : ppm1.sch

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work5. Save schematic 16. Switch to schematic 57. Zoom into the bottom area containing

the Points Subblock8. There are two user defined macros with

component labels M1 and M2 See ppm5.sch on the next slide

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work Ppm Schematic 5

M1

PointsSubblock

M2

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work9. Analyze Macro M1 by reading the slides of

this presentation and the term project handout

10.Perform functional simulations on Macro M1

Record your test vectors to use later

11.Search for the inputs and outputs of the Counter by clicking on the Query window button on top of the schematic sheet to confirm your findings in part (9)

12.Delete Macro M1 in schematic 5 Do not delete the wires Save schematic 5, ppm5.sch

See modified ppm5.sch on the next slide

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work Ppm Schematic 5

Macro M1deleted

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work13.Create space in the area by

moving the wires in schematic 514.Draw the circuit of Macro M1 in the

same area in schematic 5 First, do the design on paper Then, move the design to the

computer15.Perform an integrity test to check for

errors16.Perform functional simulations on your

circuit to verify that it is working Use the test vectors you recorded in step 10

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work17. Do a Xilinx IMPLEMENTATION

Make sure there are no errors Make sure the IMPLEMENTATION options are changed so

that a better IMPLEMENTATION is done Read the Implementation Log File to confirm that

The number of warnings 12• These warnings are OK, we can continue

The FPGA chip utilization is 89%• The Xilinx IMPLEMENTATION maps the design to 175 to 176

CLBs after an IMPLEMENTATION, a feature peculiar to FPGA testing The conversion of the schematic to the bit file is “randomized” to have a better mapping of the logic to CLBs, but it leads to this situation

That is why we fabricate the prototype chip before we mass produce it to test the design one more time to make sure the design is correct

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work18.Download the Ppm project to the FPGA

chip and play the game and to verify that the schematic works correctly

If it does not work, inspect your circuit in Block 5 and correct your circuit

19.Analyze Macro M2 by reading the slides of this presentation and the term project handout

20.Perform functional simulations on Macro M2

Record your test vectors to use later

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work21.Search for the inputs and outputs of the

Counter by clicking on the Query window button on top of the schematic sheet to confirm your findings in part (19)

22.Delete Macro M2 in schematic 5 Do not delete the wires Save schematic 5, ppm5.sch

23.Create space in the area by moving the wires in schematic 5

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work

24.Draw the circuit of Macro M2 in the same area in schematic 5 First, do the design on paper Then, move the design to the

computer25.Perform an integrity test to check for

errors26.Perform functional simulations on your

circuit to verify that it is working Use the test vectors you recorded in step 20

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work27. Do a Xilinx IMPLEMENTATION

Make sure there are no errors Make sure the IMPLEMENTATION options are changed so

that a better IMPLEMENTATION is done Read the Implementation Log File to confirm that

The number of warnings 12• These warnings are OK, we can continue

The FPGA chip utilization is 89%• The Xilinx IMPLEMENTATION maps the design to 175 to 176

CLBs after an IMPLEMENTATION, a feature peculiar to FPGA testing The conversion of the schematic to the bit file is “randomized” to have a better mapping of the logic to CLBs, but it leads to this situation

That is why we fabricate the prototype chip before we mass produce it to test the design one more time to make sure the design is correct

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work28.Download the Ppm project to the FPGA

chip and play the game and to verify that the schematic works correctly

If it does not work, inspect your circuit in Block 5 and correct your circuit

Experiment 5 Lab 9

CS 2204 Spring 2007

Today’s Individual Xilinx Lab Work29.Completing Block 5

Before moving to Block 6, the Machine Play Block make sure The label of the last component in this schematic is

U153 The subsubblocks and the subblocks are separated

by lines and labeled The circuit is beautified The schematic is saved again Functional simulations of the subblocks are done

again A Xilinx IMPLEMENTATION is done again Downloading to the FPGA board and testing are

done again

Experiment 5 Lab 9

CS 2204 Spring 2007

Understand Critical WiresRD : 4 bits

The random digit

DISP : 16 bits They represent the four position displays

In Hex DISP15-DISP12 : the leftmost position display, PD3 DISP11-DISP8 : position display PD2, etc

NDISP : 16 bits New DISP bits

In Hex

NPDISP : 16 bits Display digits plus RD

PDPRD : 4 bits Display overflow bits after addition

Experiment 5 Lab 9

CS 2204 Spring 2007

Understand Critical WiresSelplyr : 1 bit

The current player If it is 0, it is the human player, otherwise, it is the

machine player

P1SEL : 4 bits The position played by the human player

P2SEL : 4 bits The position played by the machine player

PSEL : 4 bits Position Select bits of current player

ENCPSEL : 2 bits The number of the position played

Experiment 5 Lab 9

CS 2204 Spring 2007

Understand Critical WiresBRWD : 4 bits

Basic reward In Hex

The digit played and minimum points earnedBrwdeqz : 1 bit

BRWD is zero when it is 1EQ : 4 bits

The equality of the four displays to the digit playedNSD : 2 bits

The number of similar digits, i.e. the adjacency information of the position played

REGRWD : 8 bits The regular reward points calculated by only using adjacencies

In Unsigned Binary

RDRWD : 8 bits The random reward points generated from a freely running counter

In Unsigned Binary RWD : 8 bits

The reward points earned by the play after adding REGRWD and RDRWD

In Unsigned Binary

Experiment 5 Lab 9

CS 2204 Spring 2007

Understand Critical WiresP1PT : 8 bits

Player 1 points In BCD

P2PT : 8 bits Player 2 points

In BCD

NPT : 8 bits New player points for the current player

In BCD

Ptovf : 1 bitThe points overflow

if it is 1, the new player points is above (255)10

Experiment 5 Lab 9

CS 2204 Spring 2007

Understand Critical WiresP1add : 1 bit

Player 1 adds when it is 1P1rdrwd : 1 bit

Player 1 requests a random reward when it is 1P2add : 1 bit

Player 2 adds when it is 1P2rdrwd : 1 bit

Player 2 requests a random reward when it is 1Add : 1 bit

The current player adds when it is 1P1skip : 1 bit

Player 1 skips when it is 1P2skip : 1 bit

Player 2 skips when it is 1P1played : 1 bit

Player 1 played when it is 1P2played : 1 bit

Player 2 played when it is 1

Experiment 5 Lab 9

CS 2204 Spring 2007

Understand Critical WiresClear : 1 bit

Clear FFs, registers, counters, etc. during reset in Block 2 and Block 4 so that it can play again

Clearp2ffs : 1 bit Clears Player 2 FFs, counters and registers

Clff : 1 bit Clears FFs in Block 2 so that the next player can play if there is no

overflowStp1pt : 1 bit

Store Player 1 pointsStp2pt : 1 bit

Store Player 2 pointsRdrwdsel : 1 bit

Current player has requested a random reward when it is 1Sysclk : 1 bit

System clock of the operation diagram at 6 Hz to the digit playedS1 : 1 bit

State 1 where when it is 1, the Ppm is in state 1S4 : 1 bit

State 4 where when it is 1, the Ppm is in state 4

Experiment 5 Lab 9

CS 2204 Spring 2007

Project Manager Actions and Reminders Make sure there is a CS2204 folder Make sure there is an experiment folder for

the current experimentYou can check the folder the current project is

in by selecting File -> Project Info Make sure the FPGA chip and its model are

correct when a new Xilinx project is createdYou can check the FPGA chip and its model by

selecting File -> Project Type… The selections must be as follows

• The chip : Spartan • The model : S10PC84• Speed : 3

Experiment 5 Lab 9

CS 2204 Spring 2007

Project Manager Actions and Reminders If you copy a project completely and paste it as a

new project, its schematic files cannot be worked on right away

After you open the schematics, they are all Non-Project schematics

Close all the schematics Close the schematics window Open the schematics one by one on the Project

Manager window Double click on the schematic name on the upper left side

for each schematic file

Experiment 5 Lab 9

CS 2204 Spring 2007

Project Manager Actions and Reminders When you do the first Xilinx

IMPLEMENTATION or after clearing the implementation data, you need to change implementation options before clicking on “Run” in the Implement Design Window

You can change the options by selecting Options… in the same window and then

Increase the Place & Route Level to the Highest Effort on the “Options” window

Click on the Edit Options… button for Implementation: in the Program Options area of the “Options” window

Click on Place and Route on the “Spartan Implementation Options: Default” window

Increase Router Options to 5 and 5 for both Routing Passes and Delay-Based Cleanup Passes

Experiment 5 Lab 9

CS 2204 Spring 2007

Project Manager Actions and Reminders After a successful IMPLEMENTATION

The schematic files have a check mark next to them The Design Entry button will have a check mark The IMPLEMENTATION button has a check mark (after a

delay of minutes sometimes) The PROGRAMMING button is highlighted

If not, just click in anywhere in the Flow tab area of the Project Manager window, it will be highlighted

If the IMPLEMENTATION is not successful due to errors, the IMPLEMENTATION button will have an “X” mark

The error can be because of wrong chip selection or schematic design errors

Correct them then !

Experiment 5 Lab 9

CS 2204 Spring 2007

Project Manager Actions and Reminders After a Xilinx IMPLEMENTATION, read the

Implementation Log File for errors, warnings and FPGA chip utilization

You can read the Implementation Log File by selecting Reports -> Implementation Log File

All No driver warnings must be corrected• No Driver means, the wire is not connected to any component

output All Multiple drivers warnings must be corrected

• Multiple Drivers means, a wire is connected to multiple component outputs

Most No Load warnings can be ignored• Because, the software warns that a component output is not

used, because you do not need the output• But, if a component output is needed, and not connected,

then it is an error, the output must be connected to the input of a component

Experiment 5 Lab 9

CS 2204 Spring 2007

Project Manager Actions and Reminders After performing several Xilinx IMPLEMENTATIONs, clear

the implementation data, by selecting Project -> Clear Implementation Data

Back to back Xilinx IMPLEMENTATIONs use previous implementation data that is unchanged to save time

Over time, this implementation data becomes corrupt and the bit file has errors

• Correct designs do not perform correctly on the FPGA board

Clearing the implementation data changes the implementation options to the default ones

The schematic files will keep their check marks The Design Entry button will keep its check mark But, the IMPLEMENTATION button will have a question mark The PROGRAMMING button will not be highlighted The implementation options must be changed to the required

ones again

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Place team info on schematics

You can enter the team info by selecting File -> Table Setup…

Place your name & a partner name on Line1: Place names of the other two partners on Line 2: On Line3: place CS2204 – Section A/B/C/D/E/F – Spring 2007

Press F2 to enter the Select & Drag Mode Only, in this mode components can be deleted, rotated,

copied and pasted You can press ESC to enter the Select & Drag Mode Press F3 to get component library on screen

VCC is logic 1 GND is logic 0 To quickly locate a component, enter the first few letters

of the component in the bottom area of the SC Symbols window

To locate XOR gates, just enter letter “X” and “O”

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Press F4 to draw wires Press F5 to draw buses Press F7 to search for wires and components

To search for wires, select the Signal/Bus mode If the wire does not have a name, the software assigns one

that starts with a “$” symbol and ends with a “_” symbol• Use the whole name to search for a wire

To search for a component, select the Instance mode If a component does not have a name, the software assigns

one that starts with “$I” symbols followed by a number• Use the whole name to search for the component

Press F8 to start simulation quickly Press F10 to refresh the screen

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Press ctrl-c to copy a wire or a component selected

When components are copied, their labels are not copied !

You can copy from a schematic that belongs to another project

To open the schematic of another project, click on button in the upper left corner, then select the schematic file which will be in another folder

Press ctrl-v to paste a wire or a component Press ctrl-r/ctrl-l to rotate components right/left

Wires cannot be rotated ! You can see how a Xilinx macro is designed (the

internal structure), do a Hierarchy Push, by selecting Hierarchy -> Hierarchy Push

You can close the macro internal design screen, by selecting Hierarchy -> Hierarchy Pop

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Unless otherwise stated, use Xilinx macros instead of

designing them to save time Use buffers to rename wires Do not use unnecessary input/output buffers Do not use unnecessary input/output pads If you copy and paste components, their labels are not

copied and pasted by the software You will need to “source” the schematic file to copy and paste

component labels as explained in the Advanced Xilinx and Digilent Features handout

Xilinx does not have high density ROM memory components

16x1-bit and 32x1-bit They may not be used at all

• If needed, its usage is described on page 9 of the Advanced Xilinx and Digilent Features handout

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Drawing buses by using Draw Buses button on

the left side : Ppm buses are type None Individual wires of a bus must have names the same as

the bus name The indices of individual wires start at 0 and are up to the

number of bus wires minus 1• Bus NPT has 8 wires : NPT7, NPT6, NPT5,…, NPT1, NPT0

If a component generates a bus, there is no need to draw the individual wires of the bus, unless a components needs those individual wires

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Beautify the schematic for documentation

purposes Place components of different sub/blocks separate from

each other to recognize them Write Comments, draw lines and rectangles and label

sub/blocks to identify them on the schematic for documentation purposes

• Use the Graphics Toolbox button on the left :

Label components appropriately Wire names follow application and block partitioning

naming requirements• Except for wires that are connected IBUFs, OBUFs, IPADs and OPADs

Component names start with a U• Except if it is a BUF, IBUF, OBUF, IPAD or OPAD

To label a component, right click on the component and select Symbol Properties…

• Give the name in the Reference: section of the Symbol Properties window

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Beautify the schematic for documentation

purposes Do not leave components unused Draw short wires and label them with the same name

To label wires double click on the wire and enter the name in the Net Name: area of the pop up window

Draw wires without unnecessary turn Draw wires without tangling Draw wires around components/labels/names Do not short circuit input lines Do not short circuit output lines Do not have labels/attributes/components overlap

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Perform integrity tests to catch simple

errorsYou can do an integrity test of the current

schematic sheet, by selecting Options -> Integrity Test for Current Sheet

After the completion, a window may tell you to look at the Project Manager window to read about warnings detected, even if it says the test passed successfully

• Look at the Project Manager window, you will see warnings in blue

• If the last line has the Schematic Contents OK line, there is no need to correct anything

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors

Press F8 to start simulation quickly You will see the SC Probes window :

To select the input wires to be simulated, click on the Stimulator tool button of the SC Probes windows :

Then click on the input wires by precisely clicking on their names to select them

• There will be a square gray box shown on the left side of the input wire name

• Wires that have no name cannot be simulated, therefore, they must be given names for simulation

• When selecting input bus wires, click on the bus wires in the increasing index order : ABUS0, ABUS1, ABUS2,…

Experiment 5 Lab 9

CS 2204 Spring 2007



To select the output wires to be simulated, click on the Probe tool button of the SC Probes windows :

Then click on the output wires by precisely clicking on their names to select them

• There will be a square gray box shown on the left side of the output wire name

• Wires that have no name cannot be simulated, therefore, they must be given names for simulation

• When selecting output bus wires, click on the bus wires in the increasing index order : OBUS0, OBUS1, OBUS2,…

Experiment 5 Lab 9

CS 2204 Spring 2007



To start the simulation, click on the Simulator button of the SC Probes window :

Once you have the simulation window on the screen You will see the input wires listed and then the output

wires on the left side of the Logic Simulator window

Experiment 5 Lab 9

CS 2204 Spring 2007


Separate the input rows from the output rows by placing a blank row between the input and output wires sets

Click on the top output wire Make selections Signal -> Empty Rows -> Insert

Combine bus bits to reduce the number of rows Click on the top bus wire which has the lowest index

(ABUS0) Press shift and simultaneously click on the highest order

bus wire (ABUS7) to select all the wires of the bus• A turquoise rectangle covers the bus wires

Right click on the turquoise rectangle and make the following selections Bus -> Combine

Experiment 5 Lab 9

CS 2204 Spring 2007


In order to simulate the circuit, the input wires must be first given new names

Click on the Select Stimulators button : • A keypad window will be shown

Select an input wire by clicking on it (it will be covered by a turquoise rectangle) and then click on any letter key on the keypad, such as “q”

• To the right of the input wire, the new name “q” is shown• To the right of “q”, the current value of the wire is shown

► If it is a single wire, the value is Hi-Z◊ This has to be changed to have correct simulations

► If it is a bus, the value is shown as capital letter “Z”◊ This has to be changed as well for correct simulations

Experiment 5 Lab 9

CS 2204 Spring 2007


To change the values of wires on the simulator window If it is a single wire, the value is Hi-Z :

• Just click on the Hi-Z line to make the value 0 ►The value is shown to the right of name “q” as 0• Click on the 0 value line again to make the value 1 ►The value is shown to the right of name “q” as 1

If it is a bus, the value is shown as capital letter “Z”• Click on Logical States to give a value to the bus :

►The Stimulator State Selection window will be shown• Click on the bus name, such as ABUS• Enter an appropriate Hex value in the Bus State area, such as “FA” ► Appropriate means the Hex value must fit the width of the

bus : “FA” implies, the bus has at least eight wires

• Click on the Bus button of the Stimulator State Selection window :

►The value assigned is shown to the right of name “q” as “FA”

Experiment 5 Lab 9

CS 2204 Spring 2007


To change the values of wires on the simulator window To have a clock signal as an input follow the steps below :

• Make sure the input signal is not renamed as “q”, “w” etc.• Click on the input signal to select it• Click on the Select Stimulators button : • Click on Formula… • Double click on C1: under Clocks• Enter the following in the Edit Formula area :• 100ns=H 100ns=L

► This means a periodic signal which is 100 ns 1 and 100 ns 0 is generated ► The periodic signal has a period of 200ns or a frequency of 5MHz

• Click Accept• Click Close• You will see the C1 button on the Select Stimulators window

highlighted• Click on C1 so that the input signal is renamed C1• Click on the Simulation Step button several times :• You will see the periodic signal automatically generated and the

output values in response to that

Experiment 5 Lab 9

CS 2204 Spring 2007


Start simulating the circuit for different input combinations

If the circuit has 4 or less inputs, then simulate the circuit for all input combinations (test vectors)

• 16 or less number of input combinations (test vectors) If the circuit has more than 4 inputs, select a number of

input combinations (test vectors) then simulate the circuit for these test vectors

• Which test vectors to choose is a very important task ! To simulate the circuit, click on the Simulation Step

button several times : Observe the outputs

If they are correct, try another input combination If wrong, return to the schematic and try to figure out why

it is wrong ! If an output value is Hi-Z or Unknown, there is an error,

correct it

Experiment 5 Lab 9

CS 2204 Spring 2007

Schematic Design Actions, Shortcuts & Reminders Printing schematics

1) Double click on the Printer227 icon on your desktop and wait about a minute to allow it to affect the printing option

2) Zoom into an area of the schematic to print the area

3) Select File -> Print on the schematic window4) Change the option to Current View Only on the Print

window5) Click on Setup on the Print Window6) Change the printer to HP Printer 8150 in Room 2277) Click on Options to select Landscape printing if

necessary8) Click OK as many times as needed to print the page9) Print one copy of each area and then make copies

of the printed schematics for your partners

Experiment 5 Lab 9

CS 2204 Spring 2007

What to do if the testing on the board gives wrong results even thought the design is correct ?

If the design is absolutely correct, here are the steps to follow in sequence :

1) The FPGA board is turned on ?2) SW9 is in the PROG position ?3) The Bitronics Data Switch selects your PC ?4) The FPGA type and model are correct ?5) The implementation options are changed ?6) There are not too many levels of folders to reach the project

on the PC ?7) Clear the implementation data, close the software, restart

the software and do a new Xilinx IMPLEMENTATION Does it work now ?

8) Save the schematic file worked on in a separate folder Delete the project, recreate the project, copy the schematic

design from the saved schematic file• Does it work ?

Download the zipped project from the course web site, unzip it, copy the schematic design from the saved schematic file• Does it work ?

Experiment 5 Lab 9

CS 2204 Spring 2007

What to do if the testing on the board gives wrong results even thought the design is correct ?

9) Repeat step 7, by using your partner’s working schematic

10) Login to another PC and try steps 5 - 811) Ask from the TA to help you

a) The TA will login to your original PC and try steps 5 – 8 by using your schematic design and his/her S drive

b) The TA will login to another PC and try steps 5 – 8 by using your schematic design and his/her S drive on the new PC

c) The TA will inform the professor

12) If the project works on the second PC, inform the lab supervisor, Mr. Keni Yip that the original PC has a problem

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Documents

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design checksif

design checksremember

design checksdo

design checksthe team

implementation optionscs

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