Effect of Placement on Effect of Placement on Computational Memory Computational Memory

InterfaceInterface

Richa PrasadRicha PrasadUMass, Distributed Mentoring Program, InternUMass, Distributed Mentoring Program, Intern

Professor Elaheh BozorgzadehProfessor Elaheh BozorgzadehUCI, Distributed Mentoring Program, MentorUCI, Distributed Mentoring Program, Mentor

OutlineOutline IntroductionIntroduction Project DescriptionProject Description

Statement of ProblemStatement of Problem Purpose of StudyPurpose of Study

MethodologyMethodology The Wrapper FileThe Wrapper File FPGA Chip Selection & DescriptionFPGA Chip Selection & Description The ProcessThe Process

Findings & DiscussionFindings & Discussion Description of FindingsDescription of Findings Possible Future WorkPossible Future Work SummarySummary

Recap

Previous + New

Recap…Recap…INTRODUCTION

ASIC

FPGA

Microprocessor

Flexibility

Chi

p P

erfo

rman

cePROJECT DESCRIPTION

DCM

Multiplier

CLB

BRAM

WRAPPER FILE PROCESS

Computational

BlockMemory

Block

ClockReset Enable Data

Read

Write

DataData

Wrapper File

Synplicity

Synthesis

Place & Routing

Timing Report

User Constraint File

Xil

inx

Pro

ject

Nav

igat

or

……RecapRecapFPGA DESCRIPTION WIRE TYPES

ChipChip Row x ColRow x Col BRAM ColBRAM Col SlicesSlices

V500V500 32 x 2432 x 24 44 3,0723,072

V2000V2000 56 x 4856 x 48 44 10,75210,752

V8000V8000 112 x 104112 x 104 66 46,59246,592

VP20VP20 -- 88 22,03222,032

VP100VP100 -- 1616 99,21699,216

CLB versus BRAM

• Farther locations – BRAM

• Closer locations – CLB

• CLB > BRAM as V500 to V8000

• CLB > BRAM as VP100 to VP20

• Frequency more for CLB

New Observations…New Observations…BRAM ACROSS CHIPS

1

3

2

4

5

6

7

8

OBSERVATIONS

• Doubled Frequency for V8000 & VP100

• Except V500, Frequency at 3 to 4

• VP100 Frequency > V8000 Frequency

• Location 6 = 8 for all, except V500

INFERENCES

• Positioning important

• V500 = small chip

• Location 6 = 8 distance wise

……New ObservationsNew ObservationsCLB ACROSS CHIPS

1

3

2

4

5

6

7

8

OBSERVATIONS

• Except at 7, V500, VP20, VP100 always

• Frequency change than BRAM

• V8000 & VP100 max change in frequency

• Location 6 = 8, for V2000, V8000 & VP20

INFERENCES

• Positioning important more for CLB

• More so for large chips

• Location 6 = 8 distance wise

Delay Distribution across signal bits…Delay Distribution across signal bits…LOCATION 1 – FARTHEST TOP

Fail

Pass

FAILED

• Big change in distribution

• High Standard Deviation

PASSED

• Low Deviation

• Most centered around mean

1

……Delay Distribution across signal bits…Delay Distribution across signal bits…LOCATION 3 – FARTHEST BOTTOM

Fail

Pass

FAILED

• High Deviation

• All small delays use Long

PASSED

• Low Deviation

• Delays centered around mean

•All small delays use Long3

……Delay Distribution across signal bits…Delay Distribution across signal bits…LOCATION 5 – MIDDLE MIDDLE

Low Deviation, regardless of whether timing constraint is met or not

Fail

Pass

5

……Delay Distribution across signal bitsDelay Distribution across signal bitsLOCATION 6 – MIDDLE BOTTOM

Fail

Pass

FAILED

• Low Deviation

• 2 Fullhex wires used

PASSED

• Low Deviation

• Unihex most widely used

6

Possible Future WorkPossible Future Work

1. Switches met on each wire path

2. Change in wire type along each path

3. Redo experiments along with 1 and 2 on other chips

SummarySummary1. BRAM versus CLB an issue for larger chips

2. Farther locations – BRAM

3. Closer locations – CLB

4. CLB better choice on all chips for locations 6 to 8

5. Positioning especially important for V8000 and VP100

6. Overall frequency of V8000 < Overall frequency of VP100

7. Memory block along farthest column of BRAM – Timing Failed – High delay distribution

8. Memory block along farthest column of BRAM – Timing Passed – Low delay distribution

9. Memory block along middle column of BRAM – Timing Passed/Failed - Low delay distribution