e5163 silibus 5 - pld

E5163 Rekabentuk Litar Bersepadu 21 May 2008

Mohd Sharif Zakaria, POLISAS 1

E5163 REKABENTUK LITAR

BERSEPADUMohd Sharif Zakaria

Jabatan Kejuruteraan Elektrik

Politeknik Sultan Hj. Ahmad Shah

SILIBUS : 5.0 PERANTI LOGIK BOLEH-

ATURCARA (PLD)

5.1 Peranti Logik Boleh-Aturcara (PLD)

1.Metakrifkan Peranti Logik Boleh-Aturcara.

2.Membincangkan kelebihan penggunaan Litar

Bersepadu jenis ini berbanding dengan litar

bersepadu piawai dan Litar Bersepadu

Langganan.

3.Menyatakan ciri-ciri am Litar Bersepadu jenis

ini.

4.Membincangkan contoh-contoh Litar Bersepadu

ROM dalam kategori ini.

5.Menyenaraikan Syarikat pengeluar utama Litar

Bersepadu ini.2

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Programmable Logic Device Definitions

PLD adalah tatasusunan get logik yang boleh di

aturcara oleh pengguna yg mana mengandungi

fungsi beberapa litar logik kecil didalam cip

tunggal. (PLD is a user programmable array of

logic gates which consolidated the function of a

number of smaller logic limit onto a single chip.)

Teknologi PLD TransistorTransistor Logic

(TTL), Emitter Coupled Logic (ECL), CMOS.


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Advantage of Programmable Logic Device

Cost Effective Total mfg. cost using PLD is less then std IC

Purchase IC is 25%-50% of the PCBA

Fast System Design Time needed to design and implement a system can be

reduced

Breadboards can be build to test new idea

Real Estate (Nilai Sebenar) One PLD typically implement the equivalent 4-12pcs SSI/MSI

package

Suitable for PCBA with limited space

Number of IC required is less

Design Flexibility Flexibility of any design required

Can design function which not ready available with standard component.

Engineer simply choose what he wants instate of taking what he




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Advantage of Programmable Logic Device

Easy Design Changes Simply reprogram a chip instate of re-designing hardware

and layout a new PCB when function change

High Speed Operate at high speed

Produce extremely fast devices

Easy Field Programming User programmable to minimize turnaround time

Programmed quickly and easily using standard PROM programmer

Conversion of logic function into PLD format can be done using variety of software tools

Re-usable chip

Small Inventory PLD can be used to replace many component

Lower inventory cost


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History Evaluation of PLD

Diode Matrix The first programmable Logic Device. Introduced in early

1960. Contain only diode logic OR matrix. Each cross point of which had a fusible link

Programmable Read Only Memory (PROM) It had an AND-OR logic element with fixed AND matrix

and programmable OR.

Field Programmable Logic Array (FPLA) It has an AND-OR logic element with fixed OR matrix and

programable AND

Generic Array Logic (GAL) Consist of

- Intact Fuse (fuse bersambungan)

- Blow Fuse (fuse putus)




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Generic Array Logic (GAL)

Introduction in the late 1980

Similar with PLD with one or two difference

GAL base on EEPROM technology

GAL has variable output architecture\

Characteristic of GAL devices are not fix during

of manuracturing. User may program on an out-

by-output basis, the function of the output.

Variable output architecture achieved by

additional block know as Output Logic Microcell-

OLM attached at the output.


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Generic Array Logic (GAL)

Each microcell contain 2 programmable switch (S1,S2) to control the output.

S1- Determines weather o/p will be register or combinational

S2-Determines the output polarity (high/low)

D

Q

Q

S1 S2

Input / Output

Output Logic Macrocell




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Types of programmable logic

Many types of programmable logic are available.

The current range of offerings includes

everything from small devices capable of

implementing only a handful of logic equations to

huge FPGAs that can hold an entire processor

core (plus peripherals!). In addition to this

incredible difference in size there is also much

variation in architecture.

Other names you might encounter for this class

of device are

Programmable Logic Array (PLA),

Programmable Array Logic (PAL),

Generic Array Logic (GAL).


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Checklist for programmable logic selection

Number of I/O Pins Are there adequate inputs and outputs for your design? This is often a more limiting constraint than gate count, and it very much affects the cost of the chip. As a result, many manufacturers offer the same part with different numbers of I/O pins.

Cost per Chip Obviously, cost is a factor if you'll be including a CPLD or FPGA in your production system. Would it be cheaper in the long run to develop a fixed ASIC design and produce a large quantity of them? If you stick with the programmable device, you'll want to use the smallest part with adequate resources for your design.

Available Tools The most popular Verilog and VHDL simulation and synthesis tools are sold by third party tool vendors. These tools generally have support for a laundry list of common FPGAs and CPLDs. This means that the tools understand the constraints of your particular chip and also understand the timing-relating information that comes out of the place and route tool.




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Performance Generally speaking, CPLDs are faster and introduce more predictable delays than FPGAs. However, that's because their internal structure is less flexible. So you have to give something up for the extra speed. What's typically lost is density. The larger your design, the more likely it is that you'll have to use a slower part. When using an FPGA, the actual performance of your design won't really be known until the final place and route process is complete, since the routing specifics will play a role.

Power Consumption Power consumption can be an important consideration in any system. EEPROM and Flash-based devices usually require more power than those based on PROM, EPROM, or SRAM technologies.

Packaging Programmable logic devices are available in all sorts of packages. Your choice of a package will most likely be driven by your need to reduce power consumption, heat dissipation, size, and/or cost.


ATURCARA (PLD)

5.2 Peranti Logik Boleh-Aturcara (PLD)

1.Melukis pelan lantai akitektur serpih.

2.Melabelkan bahagian seperti Salinghubung Boleh-

Aturcara dan Blok Logik Boleh-Aturcara.

3.Gambarajah Blok Logik Boleh-Aturcara

a.Melukis rajah blok akitektur bahagian ini.

b.Menerangkan kandungan blok logik boleh aturcara.

c.Melukis rajah akitektur serpih PROM, PAL dan

PLA.

d.Menyatakan perbezaan antara ketiga-tiga jenis

serpih dengan memberi contoh perlaksanaan fungsi

ungkapan logik. 12

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Programmable Array LogicThe term Programmable Array Logic (PAL) is used to describe a family of programmable logic device semiconductors used to implement logicfunctions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in mid 1978.PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.Using specialized machines, PAL devices were "field-programmable". Each PAL device was "one-time programmable" (OTP), meaning that it could not be updated and reused after its initial programming. (MMI also offered a similar family called HAL, or "hard array logic", which were like PAL devices except that they were mask-programmed at the factory.)Early PALs were 20-pin DIP components fabricated in silicon using bipolar transistor technology with one-time programmable (OTP) titanium-tungsten programming fuses.[1] Later devices were manufactured by Lattice Semiconductor and Advanced Micro Devices using CMOS technology.The original 20 and 24-pin PALs were described by MMI as medium-scale integration (MSI) devices.


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Programmable Array Logic PAL architectureThe PAL architecture consists of two main components: 1. Programmable Logic Plane 2. Output Logic Macrocells.




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Programmable logic planeThe programmable logic plane is a programmable read-only memory(PROM) array that allows the signals present on the devices pins (or the logical complements of those signals) to be routed to an output logic macrocell.PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "sum-of-products" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.


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Output logicThe early 20-pin PALs had 10 inputs and 8 outputs. The outputs were active low and could be registered or combinational. Members of the PAL family were available with various output structures called "output logic macrocells" or OLMCs. Prior to the introduction of the "V" (for "variable") series, the types of OLMCs available in each PAL were fixed at the time of manufacture. (The PAL16L8 had 8 combinational outputs and the PAL16R8 had 8 registered outputs. The PAL16R6 had 6 registered and 2 combinational while the PAL16R4 had 4 of each.) Each output could have up to 8 product terms (effectively AND gates), however the combinational outputs used one of the terms to control a bidirectional output buffer. There were other combinations that had fewer outputs with more product term per output and were available with active high outputs. The 16X8 family or registered devices had an XOR gate before the register. There were also similar 24-pin versions of these PALs.




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This fixed output structure often frustrated designers attempting to optimize the utility of PAL devices because output structures of different types were often required by their applications. (For example, one could not get 5 registered outputs with 3 active high combinational outputs.) So, in 1983 AMD (source needed) introduced the 22V10, a 24 pin device with 10 output logic macrocells. Each macrocell could be configured by the user to be combinational or registered, active high or active low. The number of product term allocated to an output varied from 8 to 16. This one device could replace all of the 24 pin fixed function PAL devices. Members of the PAL "V" ("variable") series included the PAL16V8, PAL20V8 and PAL22V10.


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ATURCARA (PLD)

Programmable Logic Array (PLA)

is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical forms.

One application of a PLA is to implement the control over a datapath. It defines various states in an instruction set, and produces the next state (by conditional branching). [eg. if the machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the actions of the control in state 2, will set the next state to be 4 if the instruction contains an immediate field, and will define the actions of the control in state 4]. Programmable Logic Arrays should correspond to a state diagram for the system.

Other commonly used programmable logic devices are PAL, CPLD and FPGA.

Note that the use of the word "Programmable" does not indicate that all PLAs are field-programmable; in fact many are mask-programmed during manufacture in the same manner as a ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPLA (Field-programmable PLA).

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ATURCARA (PLD)

PLA ( Programmable Logic Arrays )

Introduction :PLAs belong to a class of components called programmable logic devices or PLDs , a term applied to ICs containing many gates or other general - purpose cells whose interconnections can be configured or "programmed" to implement any desired combinational or sequential function. PLDs are relatively easy to design and inexpensive to manufacture. They constitute a key technology for building application-specific integrated circuits (ASICs).The programmable logic array ( PLA ) shown in the figure is intended to realise a set of combinational logic functions in minimal SOP form. It consists of an array of AND gates ( the AND plane ) , which realisea set of product terms , and a set of OR gates ( the OR plane ) , which form various logical sums of the product terms. The inputs to the AND gates are programmable and include all the input variables and their complements. Hence it is possible to program any desired product term into any row of the PLA.

PLA specification : n x k x m( n inputs , k product terms and m outputs )

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The above figure shows a ( 4 x 8 x 6 ) PLA. PLA consists of an AND plane and an OR plane.


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ATURCARA (PLD)

5.3 Kaedah-kaedah pengaturcaraan Peranti Logik

Boleh-Aturcara diaturcara.

1.Melukis rajah blok perkakasan-perkakasan yang

digunakan.

2.Kaedah-kaedah masukan aturcara bagi peranti ini.

a.Menghuraikan kaedah masukan dengan

menggunakan: Pengedit Skima, Persamaam Boolean

dan Jadual Kebenaran.

b.Menyatakan contoh-contoh bahasa rekabentuk

tahap rendah dan perisian komputer yg

menggunakannya.

c.Menyatakan contoh-contoh bahasa rekabentuk

tahap tinggi.23

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A description of the hardware's structure and

behavior is written in a high-level hardware

description language (usually VHDL or Verilog)

and that code is then compiled and downloaded

prior to execution. Of course, schematic capture is

also an option for design entry, but it has become

less popular as designs have become more complex

and the language-based tools have improved.




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Programming languagesThough some engineers programmed PAL devices by manually editing files containing the binary fuse pattern data, most opted to design their logic using a hardware description language (HDL) such as Data I/O's ABEL, Logical Devices' CUPL, or MMI's PALASM. These were computer-assisted design (CAD) (now referred to as "design automation") programs which translated (or "compiled") the designers' logic equations into binary fuse map files used to program (and often test) each device.

1. PALASMThe PALASM (from "PAL assembler") language was used to express boolean equations for the outputs pins in a text file which was then converted to the 'fuse map' file for the programming system using a vendor-supplied program; later the option of translation from schematics became common, and later still, 'fuse maps' could be 'synthesized' from an HDL (hardware description language,) such as Verilog.The PALASM compiler was written by MMI in FORTRAN IV on an IBM 370/168. MMI made the source code available to users at no cost. By 1983, MMI customers ran versions on the DECPDP/11, Data General NOVA, Hewlett-Packard HP2100, MDS800 and others.PALASM is an early hardware description language, used to translate Boolean functions and state transition tables into a fuse map for use with Programmable Array Logic (PAL) devices introduced by Monolithic Memories, Inc. The language was developed by John Birkner in the early 1980s. It is not case-sensitive.


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Programming languages

2. ABELData I/O Corporation released ABEL.The Advanced Boolean Expression Language (ABEL) is a Hardware description language and an associated set of design tools for programming PLDs. It was created in 1983 by Data I/O Corporation, in Redmond, Washington.ABEL includes both concurrent equation and truth table logic formats as well as a sequential state machine description format. A preprocessor with syntax loosely based on DEC's Macro-11 is also included.In addition to being used for logic descriptions, ABEL may also be used to describe test vectors (patterns of inputs and expected outputs) that may be downloaded to a hardware device programmer along with the compiled and fuse-mapped PLD programming data.Other PLD design languages originating in the same era include CUPL and PALASM. Since the advent of larger Field Programmable Gate Arrays (FPGAs), PLD languages have fallen out of favor as standard Hardware Description Languages (HDLs) such as VHDL and Verilog have gained in popularity. Nonetheless after two decades ABEL remains in use by thousands of PLD programmers worldwide.The original ABEL development team (led by Dr. Kyu Lee) included Mary Bailey, Bjorn Benson, Walter Bright, Michael Holley, Charles Olivier and David Pellerin.Through a series of acquisitions, ABEL is now owned by Xilinx Inc.




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Programming languages

3. CUPLLogical Devices, Inc. released the Universal Compiler for Programmable Logic (CUPL), which ran under MSDOS on the IBM PC.Device programmersPopular device programmers included Data I/O Corporation's Model 60A Logic Programmer and Model 2900.


ATURCARA (PLD)

5.4 Kaedah-kaedah penyimpan ingatan Peranti Logik Boleh-Aturcara.

1.Transistor FMOS (MOS Suntikan Runtuhan Get Terapung).

a.Melukis struktur binaan transistor ini.

b.Menghuraikan bagaimana transistor ini boleh berada dlm keadaanON atau OFF, seta cara menyimpan dan memadam ingatan.

c.Memberi contoh perlaksanaan fungsi logik menggunakan transistor ini pada matrik-matrik salinghubungan.

2.Kaedah mengaturcara penggunaan Fius.

a.Menghubungkaitkan penggunaan fius dgn 5.2.2

b.Membincangkan mengenai Peta Fius yg dijana oleh perisiankomputer dan kaitannya dgn fungsi serpih.

3.Kaedah mengaturcara menggunakan Anti-fius, Anti-Fius Logam-logam dan Ati-Fius Poli-Resapan.

a.Melukis rajah bagi kedua-dua kaedah.

b.Menyatakan perkara yg berlaku kepada kedua-dua jenis Anti-Fiussemasa PLD diaturcara.

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ATURCARA (PLD)

5.5 Peranti Logik-BolehAtrcara Skala Besar.

1.Menamakan peranti ini sebagai Litar Bersepadu

FPGA atau CPLD.

2.Membincangkan perbezaan antara peranti ini

berbanding Peranti Logik Boleh-Aturcara

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CPLDs

As chip densities increased, it was natural for the PLD manufacturers to evolve their products into larger (logically, but not necessarily physically) parts called Complex Programmable Logic Devices (CPLDs). For most practical purposes, CPLDs can be thought of as multiple PLDs (plus some programmable interconnect) in a single chip. The larger size of a CPLD allows you to implement either more logic equations or a more complicated design. In fact, these chips are large enough to replace dozens of those pesky 7400-series parts.




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Figure 1 contains a block diagram of a

hypothetical CPLD. Each of the four logic blocks

shown there is the equivalent of one PLD.

However, in an actual CPLD there may be more

(or less) than four logic blocks. I've just drawn it

that way for simplicity. Note also that these logic

blocks are themselves comprised of macrocells and

interconnect wiring, just like an ordinary PLD.

Figure 1. Internal

structure of a CPLD


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Unlike the programmable interconnect within a PLD, the switch matrix within a CPLD may or may not be fully connected. In other words, some of the theoretically possible connections between logic block outputs and inputs may not actually be supported within a given CPLD. The effect of this is most often to make 100% utilization of the macrocells very difficult to achieve. Some hardware designs simply won't fit within a given CPLD, even though there are sufficient logic gates and flip-flops available.

Because CPLDs can hold larger designs than PLDs, their potential uses are more varied. They are still sometimes used for simple applications like address decoding, but more often contain high-performance control-logic or complex finite state machines. At the high-end (in terms of numbers of gates), there is also a lot of overlap in potential applications with FPGAs. Traditionally, CPLDs have been chosen over FPGAs whenever high-performance logic is required. Because of its less flexible internal architecture, the delay through a CPLD (measured in nanoseconds) is more predictable and usually shorte




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FPGAs

Field Programmable Gate Arrays (FPGAs) can be used to implement just about any hardware design. One common use is to prototype a lump of hardware that will eventually find its way into an ASIC. However, there is nothing to say that the FPGA can't remain in the final product. Whether or not it does will depend on the relative weights of development cost and production cost for a particular project. (It costs significantly more to develop an ASIC, but the cost per chip may be lower in the long run. The cost tradeoff involves expected number of chips to be produced and the expected likelihood of hardware bugs and/or changes. This makes for a rather complicated cost analysis, to say the least.)


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The development of the FPGA was distinct from the PLD/CPLD evolution just described. This is apparent when you look at the structures inside. Figure 2 illustrates a typical FPGA architecture. There are three key parts of its structure: logic blocks, interconnect, and I/O blocks. The I/O blocks form a ring around the outer edge of the part. Each of these provides individually selectable input, output, or bi-directional access to one of the general-purpose I/O pins on the exterior of the FPGA package. Inside the ring of I/O blocks lies a rectangular array of logic blocks. And connecting logic blocks to logic blocks and I/O blocks to logic blocks is the programmable interconnect wiring.

Figure 2. Internal

structure of an FPGA




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The logic blocks within an FPGA can be as small and simple as the macrocells in a PLD (a so-called fine-grained architecture) or larger and more complex (coarse-grained). However, they are never as large as an entire PLD, as the logic blocks of a CPLD are. Remember that the logic blocks of a CPLD contain multiple macrocells. But the logic blocks in an FPGA are generally nothing more than a couple of logic gates or a look-up table and a flip-flop.

Because of all the extra flip-flops, the architecture of an FPGA is much more flexible than that of a CPLD. This makes FPGAs better in register-heavy and pipelined applications. They are also often used in place of a processor-plus-software solution, particularly where the processing of input data streams must be performed at a very fast pace. In addition, FPGAs are usually denser (more gates in a given area) and cost less than their CPLD cousins, so they are the de facto choice for larger logic designs


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008Reference Note on next slide




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Programmable Logic Device Definitions

Digital Signal - A digital signal is one whose key characteristic (e.g., voltage or current) fall into discrete ranges of values. The interpretation of an analog signal would correspond to a signal whose key characteristic would be a continuous signal. Most digital systems utilize two voltage levels. Systems with more than two levels include MIL-STD-1553 busses. There are three ranges defined (with several keep out zones). The newer flash memory devices utilize four levels for storage, doubling the bit density to two bits per cell.

Programmable Logic - a logic element whose function is not restricted to a particular function. It may be programmed at different points of the life cycle. At the earliest, it is programmed by the semiconductor vendor (standard cell, gate array), by the designer prior to assembly, or by the user, in circuit.

Gate Array - Transistors or gates are fabricated in a 2 dimensional array on a die to form the standard base of an application specific integrated circuit (ASIC). The devices is programmed by custom metal layers interconnecting nodes in the array. Some gate arrays have other features such as SRAM blocks, phase lock loops, delay locked loops, etc.

Standard Cell - This device differs from the gate array since each cell may be different and optimized for each "standard" function. There are no standard layers to the device and each layer of the chip is a unique design.

Field Programmable Logic Array (FPLA) - And/Or/Invert architecture with three level fusing.

Field Programmable Logic Sequencer (FPLS) - Full Mealy state machine. Programmable AND andOR planes.

Field Programmable Gate Array (FPGA) - This device is similar to the gate array, defined above, with the device shipped to the user with general-purpose metallization pre-fabricated, often with variable length segments or routing tracks. The device is programmed by turning on switches which make connections between circuit nodes and the metal routing tracks. The connection may be made by a transistor switch (which are controlled by a programmable memory element) or by an antifuse. The transistor switch may be controlled by an SRAM cell or an EPROM/EEPROM/Flash cell. Timing is generally not easily predictable. Some architectures employ dedicated logic and routing resources for optimizing high-speed functions such as carry chains, wide decodes, etc.


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The PROM, PAL, AND PLA are three related devices. They share an architecture that consists of AND and OR planes. Additional features such as programmable I/O blocks, storage registers, etc., may be included in these devices. Commercial, military, and space devices use a variety of programmable elements. A complete list is beyond the scope of this tutorial. Some aerospace examples are given below.

Programmable Read Only Memory (PROM) - This device has a fixed, fully decoded AND plane and a programmable OR plane. The programmable element for these devices include EPROM, EEPROM, fuses and antifuses. Fuse materials include nichrome and polysilicon elements. Antifuse structures may consist of Oxide-Nitride-Oxide (Lockheed-Martin) or amorphous silicon (UTMC) material. Other elements are possible and may be used in some devices.

Programmaed Array Logic (PAL) - This device has a programmable AND plane and a fixed OR plane. Many commercial/military devices use fuses - one device family uses EEPROM cells and logic (CoolRunner). The UTMC UT22VP10 device uses an amorphous silicon antifuse as the programmable element. These are often referred to as Simple Programmable Logic Devices (SPLDs).

Programmable Logic Array (PLA) - This device has both programmable AND and OR planes. The space-flight application that I am aware utilized the bipolar, fuse-based, 82S100 in the central processing units of the Magellan and Galileo attitude control computers. PLA structures may also appear as part of some CPLDs. The two layers of programmable structure add a fixed delay.

Complex Programmable Logic Device (CPLD) - A high density programmable device generally based on the PAL or SPLD architecture. The routing structure leads to more predictable timing than the FPGA.




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Programmable Elements

Fuse - This is a two-terminal device that is normally a low resistive element and is programmed or "blown" resulting in an open or high impedance. Typical materials are nichrome and polysilicon. This is element is inherently radiation-hard.

Antifuse - This is a two-terminal device that is normally a high resistive element and is programmed to a low impedance. Typical programmed impedances range from 25 to 500 ohms, depending on the specific antifuse material, technology, and programming. This element is generally inherently radiation-tolerant; certain versions can be made radiation-hard. The failure mode of these elements during irradiation is rupture from a heavy ion. For a memory application, a cell's programmed state may be sensed differentially, with one element programmed (closed) and the other unprogrammed (open). An example of this structure is the UTMC PROM family.

Switch - This device consists of a memory element (either volatile or non-volatile) which controls a switch. This generally has the highest impedance of the three classes of programmable elements. The volatile, SRAM-based memory elements in use today are considered radiation-soft. EPROM, EEPROM, or SONOS (Northrop-Grumman) non-volatile elements should be relatively radiation-hard to upset. EEPROM cells have been shown to be susceptible to rupture during write cycles (high voltage present) by heavy ions.

Volatile - The memory elements lose their contents when power is removed from the device. SRAM-based devices are volatile and require another device to store their configuration program.

Non-volatile - The memory elements keep their contents when power is removed from the device. The element may be one time programmable or "reprogrammable." Examples of the former include fuses and antifuses. Examples of the latter include EPROM, and EEPROM storage elements. Programmable devices can be both non-volatile and reprogrammable.

One Time Programmable - This device can be programmed only once; it's contents can not be changed. While typically these devices are fuse or antifuse based, they can also be low-cost EPROM devices. In this case, typically used for production devices, an inexpensive package is used without a window.

Reprogrammable - These devices can have their configuration loaded more than once. SRAM-based devices may be reloaded without restriction. Many other forms of reprogrammable elements have restrictions on the number of write cycles, although they are high enough not to be of practical concern for most applications. The FRAM (ferroelectric RAM) is a non-volatile memory element which a limit to the number of read cycles; the readout mechanism of this two-terminal element is destructive and requires a write cycle to restore the contents.

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