dynamic and pass- transistor logic prof. vojin g. oklobdzija references (used for creation of the...
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![Page 1: Dynamic and Pass- Transistor Logic Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): 1.Masaki, “Deep-Submicron CMOS](https://reader035.vdocuments.site/reader035/viewer/2022062217/56649dc85503460f94abd2a1/html5/thumbnails/1.jpg)
Dynamic and Pass-Transistor Logic
Prof. Vojin G. Oklobdzija
References (used for creation of the presentation material):1. Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE
Circuits and Devices Magazine, November 1992.
2. Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circuits with CMOS”, IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982.
3. V.G. Oklobdzija, R.K. Montoye, “Design-Performance Trade-Offs in CMOS-Domino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April 1986.
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 2
References:
4. Goncalves, H.J. DeMan, “NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures”, IEEE Journal of Solid-State Circuits, Vol. SC-18, No 3, June 1983.
5. L.G. Heller, et al, “Cascode Voltage Switch Logic: A Differential CMOS Logic Family”, in 1984 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1984.
6. L.C.M.G. Pfennings, et al, “Differential Split-Level CMOS Logic for Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits, Vol. SC-20, No 5, October 1985.
7. K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 3
References:
Pass-Transistor Logic:8. S. Whitaker, “Pass-transistor networks optimize n-MOS logic”, Electronics,
September 1983. 9. K. Yano, et al, “A 3.8-ns CMOS 16x16-b Multiplier Using Complementary
Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, Vol. 25, No 2, April 1990.
10. K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
11. M. Suzuki, et al, “A 1.5ns 32b CMOS ALU in Double Pass-Transistor Logic”, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993.
12. N. Ohkubo, et al, “A 4.4-ns CMOS 54x54-b Multiplier Using Pass-transistor Multiplexer”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 4
References:
13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value Logic For Low-Power CMOS,” Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.
14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems”, Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995
15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996.
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 5
Dynamic CMOS Logic
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 6
(a) Dynamic CMOS Latch (a), Dynamic CMOS Master-Slave Latch (b)
In
DynamicNode
Out
Store
In
Clock
Out
(a) (b)
CxCx Cy
X X YI1 I2 I1 I2 I3
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 7
Dynamic Manchester Carry Chain
+ Vdd + Vdd+ Vdd+ Vdd
ip 1ip 3ip2ip
iG 1iG 3iG2iG
iC 3iC
precharge
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 8
Radiation induced charge
“1”
“0”
+
-
+
+
++
+
-
--
-
-particle
Cin
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 9
Accidental charge caused by capacitive or inductive coupling between the signal lines Y and Z. (a) Prevention by inserting and inverter between the affected line and the pass-transistor switch (b)
charge
“1”
”0"
(a)
Line1
Line2
Z
X=0
(b)
v(Y)
v(Z)
MN1
MP1 (open)
ON
MP1
Cin+++
Y
Z
Insertedinvertor
CinMN1
MP1
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 10
CMOS Domino Logic
f
N
n-type transistornetwork
f
GND
+Vcc
Clk
f
fD
N
p-type transistornetwork
n-type transistornetwork
GND
f
+Vcc
(a) (b)
CMOS logic block (a), Domino Logic (b)
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 11
CMOS Domino Logic
f
N
Inputs
Clock
F+ +
+ + ++ +
1 0
fInputs
Clock
F
10
Discharge
OperationPrecharge phase
0OFF
ON
Evaluation phase
ON
N
00
0
11
1
ON
+Vcc +VccQ2Q1
Q3 Q4
GND GND
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 12
CMOS Domino Logic Operation
fInputs
Clock
N
11
1
+VccQ2
Q4
GND
fInputs
N1
1
+VccQ2
Q4
GND
fInputs
N
1
1
+VccQ2
Q4
GND
fInputs
N
0
1
1
+VccQ2
Q4
GND
0 1
0 1
0 1
0 1
1
1
1
1
01
Dominos
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 13
CMOS Domino Logic: Charge Re-Distribution
f
N
Inputs
Clock
F+ +
+ + +
+ +Charge
1 0
f
N
Inputs
Clock
F+ +
Charge
10
GND GND
Re-distribution1
1
00
0
0
Q1 Q2
Q4Q3
+Vcc+Vcc
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 14
Variations of CMOS Domino Logic:NORA Logic
Clock
GND1
p-typetransistornetwork
Clock
GND0
n-typetransistornetwork
F1
Clock
GND0
n-typetransistornetwork
F3F2
F1 F2+Vcc +Vcc +Vcc
Q1 Q2 Q3
Q4 Q5
Q6
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 15
CVS and DCVS LogicIBM
(Heller et al. 1984)
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 16
Cascode Voltage Switch Logic CVSIBM
f
N
n-type transistornetwork
f
GND
+Vcc
Clock
small keepertransistor
evaluation
Pre-charge
InputSignals
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 17
DCVS Logic (IBM)
FF
GND
Combinationallogic network
Diff.
n-MOSinputs
Diff.inputs
+Vcc
Q1 Q2
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 18
DCVS Logic (IBM)
differentialinputs
N1 N2
n-fettrees
Q Q
Vdd
N1 N2
differentialinputs n-fet
trees
Q QClock
Clock
Vdd
Differential Cascode Voltage Switch Logic: (a) Static DCVLS (b) Dynamic DCVSL
(a) (b)
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 19
DCVS Logic vs CMOS
differentialinputs
N2
VDD
ffN1
n-MOS transistorswitching
treesf f
VDD
f
f
finputs
SharedTransistors
DCVS Logic consisting of two shared nMOS transistor switching networks
CMOS consisting of two separate: nMOS and pMOS transistor switching networks
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 20
Transistor sharing in DCVS Logic: Implementation of 3-input XOR function
A A A A
B BB B
C C
Q Q
Q = a b c
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 21
Switching Asymmetry in DCVSLVDD
A
B
C
A B C
VDD
A
B
C
A B C
VDD
A
B
C
A B C
+ + + ++ + + +
+
+
+
ON
1
1
1
1
1
1
0 0 0 0 0 0
a
OFF
1
0
aOFFON
a
ON
++
+
+
+
+++
ON ON
OFF
a
b b
a
b ba
c
c
ON
OFF
OFF ON
10 ++++
++++
a
bca
c
Vdd
timeBoth paths ON
This asymmetry causes current spikes and increased power consumption !
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 22
Pass-Transistor Logic
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 23
Pass-Transistor Logic
0 10
1
0 1
B
A
1 0
A
A
B
B
F
F
B B
(a) XOR function implemented with pass-transistor circuit, (b) Karnaough map showing derivation of the XOR function
(a) (b)
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 24
Pass-Transistor Logic
A
A
X
Y
F
X Y F0 0 00 1 A1 01 1 10 B AB01 B1B 0B 1B 0 A+BB 1BB BBB B B
B
B
B
B
B
A
BA
BABA
BABA
BA
BA
BA
General topology of pass-transistor function generator
Karnaough map of 16 possible functions that can be realized
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 25
Pass-Transistor LogicA A B B
P0
P1
P2
P3
F(A,B)
Function generator implemented with pass-transistor logic
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 26
Pass-Transistor Logic
A
B=Vdd
B
Fmax = Vdd-Vth
A=Vdd
Vth+
-
Cout
Vdd
Vdd
Fmax = Vdd-Vth
Cout
Vth+
-Vth
+
-
Vdd
(a) (b)
Voltage drop does not exceed Vth when there are multiple transistors in the path
Threshold voltage drop at the output of the pass-transistor gate
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 27
Pass-Transistor Logic
A=0V
In=VddFmax= Vdd
A=Vdd
Vth+
-
Cout
Vdd
Vdd
Cin
Vth+
-
(a) (b)
+
-Vdd
ON
+Vdd
Elimination of the threshold voltage drop by: (a) pairing nMOS transistor with a pMOS (b) using a swing-restoring inverter
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 28
Complementary Pass-Transistor Logic (CPL)
f
Inputs
Pass Variables
ControlVariables
F F
f
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 29
Basic logic functions in CPL A ABB
B
B
A ABB
B
B
A B
A B
A A
B
B
A A
A ABB
C
C
A B
A C B C
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 30
CPL Logic
AA
S S
A A
B
B
C
C
SS(a) (b)
B
B
Q Qb
n1 n2
n4n3
CPL provides an efficient implementation of XOR function
XOR gate
Sum circuit
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 31
CPL Inverter
OutputInput
Feedback Inverter
Output Inverter
Level RestorationTransistor
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 32
Double Pass-Transistor Logic (DPL):
A
B
A B B A
VDD
B
A
OO
A B
A
B
A B BA
B
A
OO
B
A
B A B A
B
A
A B
XOR/XNOR
AND/NAND
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 33
Double Pass-Transistor Logic (DPL):
(a) (b)
B
B
A A
C
C
O
Q Qb
n1
p1 n2
p2 n1
p1 n2
p2
B
B
A A
SSO
XOR
One bit full-adder: Sum circuit
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 34
Double Pass-Transistor Logic (DPL):
A
A
B
B
Vcc
A
A
B
B
Vcc
C C
S
S
Vcc
BufferMultiplexer
OR/NOR
AND/NAND
The critical path traverses two transistors only (not counting the buffer)
DPL Full Adder
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 35
Formal Method for CPL Logic DerivationMarkovic et al. 2000
(a) Cover the Karnaugh-map with largest possible cubes (overlapping allowed)
(b) Express the value of the function in each cube in terms of input signals
(c) Assign one branch of transistor(s) to each of the cubes and connect all the branches to one common node, which is the output of NMOS pass-transistor network
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 36
Formal Method for P-T Logic Derivation
Complementary function can be implemented from the same circuit structure by applying complementarity principle:
Complementarity Principle: Using the same circuit topology, with pass signals inverted, complementary logic function is constructed in CPL.
By applying duality principle, a dual function is synthesized:
Duality Principle: Using the same circuit topology, with gate signals inverted, dual logic function is constructed.
Following pairs of basic functions are dual:AND-OR (and vice-versa)
NAND-NOR (and vice-versa)XOR and XNOR are self-dual (dual to itself)
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 37
Derivation of P-T Logic
0 0
0 1
0 1
0
1A
B
L 1 L 2
B
B
AND
A B
L 2 L 1
1 1
1 0
0 1
0
1A
B
L 1 L 2
1 1
1 0
0 1
0
1
A
B
L 1 L 2
B
B
NAND (OR)
A B
L 2 L 1
B
B
OR
A B
L 1 L 2
B
A A
B
A
B
A
B
AND NAND
OR OR
Copmplementarity: AND NAND; Duality: AND OR
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 38
Derivation of CPL Logic
Duality: AND ORNAND NOR
0 0
0 1
BA 0 1
0
1A
B
L 1 L 2
(a)
B
B
AND
A A
B
B
OR NOR
A A
(c)
NAND
(b)
B B BB
L 2 L 1
Complementarity: AND NAND
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 39
Derivation of CPL Logic
(a) XOR function Karnaugh map, (b) XOR/XNOR circuit
0 1
1 0
BA 0 1
0
1A
B
L 1 L 2
(a)
B
B
XOR
A A
XNOR
(b)
A A
L 2 L 1
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 40
Synthesis of three-input CPL logic
0 0
0 0
BC
A 00 01
0
1A
C
L 3
L 2
(a)
A
B
AND
C
(b)
11 10
0 0
1 0
L 1
NAND
C
A
B
B
A B A B
L 3L 2L 1
(a) AND function Karnaugh map, (b) AND/NAND circuit
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 41
Double Pass-Transistor Logic (DPL): Synthesis Rules
1. Two NMOS branches can not be overlapped covering logic 1s. Similarly, two PMOS branches can not be overlapped covering logic 0s.
2. Pass signals are expressed in terms of input signals or supply. Every input vector has to be covered with exactly two branches.
3. At any time, excluding transitions, exactly two transistor branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are possible), i.e. they both provide output current.
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 42
Double Pass-Transistor Logic (DPL): Synthesis Rules
Complementarity Principle: Complementary logic function in DPL is generated after the following modifications:
• Exchange PMOS and NMOS devices. Invert all pass and gate signals
Duality Principle: Dual logic function in DPL is generated
when:
• PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged.
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Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 43
DPL Synthesis:
0 0
0 1
BA 0 1
0
1A
B
L 1 L 2
(a)
A B
B A
(b)
L
L
3
4
BA
GND GND
AND
A B
B A
BA
NAND
+V DD +V DD
L 2L 4
L 1L 3
(a) AND function Karnaugh map (b) AND/NAND circuit
![Page 44: Dynamic and Pass- Transistor Logic Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): 1.Masaki, “Deep-Submicron CMOS](https://reader035.vdocuments.site/reader035/viewer/2022062217/56649dc85503460f94abd2a1/html5/thumbnails/44.jpg)
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 44
DPL Synthesis: OR/NOR circuit
A B
BA
B A
OR
A B
B A
BA
GND GND
NOR
+V DD +V DD
![Page 45: Dynamic and Pass- Transistor Logic Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): 1.Masaki, “Deep-Submicron CMOS](https://reader035.vdocuments.site/reader035/viewer/2022062217/56649dc85503460f94abd2a1/html5/thumbnails/45.jpg)
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 45
DPL Synthesis:
0 0
0 1
BA 0 1
0
1A
B
L 1 L 2
(a)
A B
B A
(b)
L
L
3
4
BA
GND GND
AND
A B
B A
BA
NAND
+V DD +V DD
L 2L 4
L 1L 3
AND function Karnaugh map AND/NAND circuit
A B
BA
B A
OR
A B
B A
BA
GND GND
NOR
+V DD +V DD Duality Principle: PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged:AND ORNAND NOR
Complementarity Principle: Exchange PMOS and NMOS devices. Invert all pass and gate signalsAND NAND