disruptive technologies: what to pic?

1 | © Infinera Corporation 2012 1 | © Infinera Corporation 2012

The 3 W Coherent Transponder

Dave Welch, Founder and EVP


Or… W/Gb needs to scale with bandwidth growth

3 | © Infinera Corporation 2012

To scale power in the network• Router bypass is required• Layer convergence is required• MPLS management is required• In addition, power has to be reduced in each layer• The “geometries” of the Long Haul network will not change

The Short Answer


Power consumed at all network layers

Power consumed to inter‐connect network layers

The more a service hops between layers, the more power consumed

Power Use: The NETWORK ProblemRouting (IP/MPLS)

Switching

Transport

Service

Highest impact to power savings: Convergence


Routing (IP/MPLS)

Transport

Power from WDM and OTN/Switching layersPlus…power to inter‐connect the two:Solution: converged switching + WDM

No more transponders

Network Power: WDM + Switching

Converged Optical Switching/Transport

PICEnabled

Reduced Boxes and Inter‐Connections

Switching


Converged WDM + Switching: The Result

Fewer boxes and inter‐connections save power

$0

$10,000

$20,000

$30,000

$40,000

$50,000

$60,000

$70,000

WDM + Stand‐alone OXC

Integrated WDM + Switchingw/discrete optics

Integrated WDM + Switching

w/PICs

Power OPEX ($'000)

Y10

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Source: Typical national/regional WDM + switch network with multi‐Terabit OXC and 100G WDM (Infinera study)


Converged Packet –Optical Transport

Reduce number of router hops and Router‐Optical interconnections

“Router bypass”

Optimize total network power

TOTAL Network Power

Routing (IP/MPLS)

Switching

TransportConverged Optical + MPLS Switching

(P‐OTN)


Modeling based on core nation‐wide IP/Optical network• spanning 18,000km • 96 city nodes

Power estimates based on Terabit scale routers & transport systems

MPLS Transport ‐ Power Savings

0

1

2

3

4

5

6

0.5 1 2 4 8

Normalize

d Po

wer

Normalized Network Load

Separate router andtransport

Packet Aware transport


Coherent is a network requirement• All fibers that require > 1Tb/s• QPSK is the coherent technology for Long Haul, • 16 QAM does not meet broad based network needs

Bandwidth per unit needs to scale with bandwidth consumption• OPEX requirement• Requires superchannels or will not keep pace

25‐30% of power consumption is for chassis cooling (i.e. fans)The optical engine needs to minimize cooling required• Optics Tj – 75oC; Electronics Tj – 125oC

Axioms to keep in mind


10 Lasers40 Modulators32 Gbaud; 64 GS/s Electr.~28nm SiliconTime to Market: ~2 years

375 GHz375 GHz2 Lasers8 modulators160 Gbaud; 320 GS/s Electr.~16nm SiliconTime to Market: ~7 years

1 Tb/s PM‐QPSK

375 GHz1 Laser4 modulators320 Gbaud; 640 GS/s Electr.~ 11 nm Silicon Time to Market: ~10 years

Implementing a 1Tbps Super‐channel for LH networksC Band

PICs are required


1 Tb/s in a single line card

1Tbps Super Channel Tx and Rx

PIC’s are the Only Practical Approach to Implementing Large Scale Coherent

1T RX PIC

1T TX PIC

10 channels of Tx

10 channels of Rx


5x100Gbps PICs in Production Today500G Super‐Channel Network Deployments Start in 2Q2012

500GTx PIC

500GRx PIC

Number of Channels 5 x 100GMonolithic InP Chips 2Optical Functions > 600

“Gold Box” Replacements > 100Fiber Jumper Replacements > 250

COST

SIZE

POWERCAPACITY RELIABILITY

5x100G Tx and Rx Modules are Roughly Same Size as 10x10G


Increasing Spectral Efficiency with Higher Order ModulationMod.Format Reach Fiber Capacity

PM‐BPSK 6000 km 6Tbps

PM‐QPSK 3000 km 12Tbps

PM‐16QAM 800 km 24Tbps

Photonic Integration Enables a Single Cost Efficient 1Tbps Line Module with SW Configurable Modulation Formats

BPSK QPSK 8QAM 16QAM


Sources of Power in Coherent DSPs

65nm

40nm

28nm

Relative Watt P

er 100

Gb/s56GS/s 64GS/s 128GS/s

Relative Power vs. ADC Speed

1.0

0.5

0.25

0.35

20nm

Coherent Power Use by Functional Blocks

25%

10%

30%

30%

5%

ADC/DACSERDESDSPSoft FECOther

Flex Coherent – also means Flex Power


FEC and Framer Integration

Framer FEC/DSP Tx/Rx

Framer/FEC/DSP Tx/Rx

• Integration required for SERDES power elimination• Optics will remain isolated as different cooling requirements

Phy

Phy

Today

Tomorrow


Moore’s Law: power gains from CMOS feature size reductionReduced “power per bit” using higher‐order modulation for metroUp to 50% reduced DSP power for metro

Power Savings for Coherent DSP/ASICsRe

lative Watt P

er 100

Gb/s

3000

CD Tolerance[ps/nm]

0.5

50,000 12,000

1.0

0.75


Network power driven first and foremost by network convergence and optimization Coherent is required; QPSK is the LH standardBandwidth scaling requires PICs and superchannelsPICs enable system level power reductionFlexible Coherent for ASIC/DSP application and power optimization

Conclusion


Thank You

disruptive technologies: what to pic?

Technology