detector daq status

MICE CM17 Feb 07 Jean-Sébastien Graulich Slide 1

Detector DAQ StatusDetector DAQ Status

o Since CM16

o Detector DAQ software

o Front End Electronics

o Schedule Milestones

o Summary

Jean-Sebastien Graulich, Geneva


Since CM16Since CM16

DAQ Software Training in CERN-ALICE group DAQ Software Training in CERN-ALICE group CompletedCompleted

We have been officially granted the right to use DATE

Test of Front End Electronics for TOF and Test of Front End Electronics for TOF and EMCalEMCal

Decision to use CAEN V1724, 100 MHz, 14 bit flash ADC

Successful tests of the Shaper/Amplifier coupled to the flash ADC

Decision to use Lecroy 4415A Discriminators available in Geneva for TOF in Phase 1.

Start working on a technical design for the Start working on a technical design for the Particle TriggerParticle Trigger


DATE VocabularyDATE Vocabulary

LDC : Local Data ConcentratorLDC : Local Data Concentrator The PC connected to the VME crate via the PC-VME

Interface GDC : Global Data CollectorGDC : Global Data Collector

Event Builder EventEvent

DATE Event = DAQ Event !!! It contains data for several Particle Events (~600)

Trigger ReceiverTrigger Receiver Input Register (with several inputs) receiving the

signal informing the LDCs that something has happened, e.g the spill is finished and the data should be readout (= DAQ Trigger)

Event TypeEvent Type Tag attached to the event depending on which trigger

receiver‘s input has been used.


DATE Readout DATE Readout ProcessProcess

Two processes running in each LDCTwo processes running in each LDC The readout process waits for a trigger, reads out the

front-end electronics, and fills a FIFO buffer with the sub-event data

The recorder process off-loads the FIFO and sends the sub-event data to one (or several) GDC over the network

Each LDC contains a set of EquipmentsEach LDC contains a set of Equipments Equipment =~ 1 Vme board (in MICE) Each equipment has its own set of routines for its

initialization and readout. Adding an equipment is done without recompiling all

DATE Equipment configuration data is saved in MYSQL

database (but not archived)


DATE Readout DATE Readout AlgorithmAlgorithm

5 user routines have to be 5 user routines have to be implementedimplemented

(XXX is the name of the equipment) ArmHwXXX

Executed at the beginning of the Run

Allows initialization of the board AsynchReadXXX

Executed constantly even when there is no trigger

Don’t use ! EventArrivedXXX

Used only if the equipment needs to trigger the readout ( Trigger Receiver)

ReadEventXXX That is the readout itself

DisArmHwXXX Executed at the end of the Run

General algorithm for equipment readout:General algorithm for equipment readout:


DATE Data FormatDATE Data Format The data sent by the equipment is just wrapped with a The data sent by the equipment is just wrapped with a

LDC header (+ a GDC header if used)LDC header (+ a GDC header if used)

The data format in the payload is defined by the The data format in the payload is defined by the manufacturer of the equipment ! (we will stick to 32 manufacturer of the equipment ! (we will stick to 32 bits words)bits words)

DATE Header format defined in a header file DATE Header format defined in a header file event.hevent.hThis file contains all the information the offline codes needs to know

about DATE

Data from the equipment -Data from the equipment ->>


FEE Tests with FEE Tests with cosmicscosmics

Testing the CAEN V1724, 14 bits, 100 MHz Flash Testing the CAEN V1724, 14 bits, 100 MHz Flash ADCADC

Test similar to the one presented at CM16 for the SIS3320

Improvement: each PMT now connected to a TDC a QDC and a FADC

Trigger CounterShaper

Discr.

FADC

QDC

TDC

Shaper

Discr.

TDC

QDC

FADC

Test done with TOF Scintillator bar and EMCal Test done with TOF Scintillator bar and EMCal PmtsPmtsEMCal Twisted pair Cable => new shaper EMCal Twisted pair Cable => new shaper prototype prototype


Shaper OutputShaper Output

V1724 - Seq

norm 264.6 2236 0.839 6.177 0.321 1.666t 0.33 27.48offset 7.1 8194

0 20 40 60 80 100

8200

8400

8600

8800

9000

9200

9400

Need for better tuning of baseline restorerUsed for individual

baseline evaluation

The signal shape is still very well understoodThe signal shape is still very well understoodTime (sample)


Charge and Time from Charge and Time from FADCFADC

The amplitude of the shaped signal is proportional to the original The amplitude of the shaped signal is proportional to the original chargecharge

Very simple algorithm => Save CPU for offline analysisVery simple algorithm => Save CPU for offline analysis Comparing MAX with INTEGRAL allows simple detection of pile upComparing MAX with INTEGRAL allows simple detection of pile up

In case of pile up => Need more sophisticate algorithm

25 5030 4035 45

Max ~ Q

Time (sample)

30%Max

T_th


Charge ResolutionCharge Resolution

80 90 100 110 120 1300

200

400

600

800

1000

1200

1400

1600

1800

Pedestal Charge (ADC channel)

Baseline offset (FADC channel)

Charge (ADC channel)

Counts

Counts

Counts

Counts

Landau Fit

2 / ndf 414/356

norm 946 +_ 11

MPV 174.3 +_ 0.4

Sigma 20.0 +_ 0.2

Gaussian Fit

2 / ndf 14/9

norm 1749 +_ 21

Mean 96.33 +_ 0.03

Sigma 2.38+_ 0.02

25 samples Average before the signal

2 / ndf 356/230

norm 1353 +_ 16

MPV 744.3 +_ 1.7

Sigma 85.1 +_ 1.0

Max amplitude (FADC channel)

Landau Fit

MPV/Sigma 8.71

MPV/Sigma 8.75

Double peak caused by 50 Hz structured noise

on the base line(observed on the scope,

also on the QDC line)


Charge ResolutionCharge Resolution

Very good linearityVery good linearity The few points off the line are

Out of QDC gate signal Noise in the line Pile up (rare)

Intrinsic Resolution of FADC = 1.8 QDC channels equivalentIntrinsic Resolution of FADC = 1.8 QDC channels equivalent Better than the QDC itself = 2.4 QDC channelsBetter than the QDC itself = 2.4 QDC channels


Time ResolutionTime Resolution

Looking at the Time difference between Left and Right Looking at the Time difference between Left and Right Pmts Pmts

TDC is sensitive to Time Walk (and to the track angle)TDC is sensitive to Time Walk (and to the track angle)=> Applying cuts on charge deposit in both PMTs makes the tail disappear


Time CorrelationTime Correlation

5 6 7 8 9 10 11 12 13 14-37

-36

-35

-34

-33

-32

-31

-30

-29

-28

-27

Time Difference FADC vs TDC

4 cm wide

trigger c

ounter

Slope = 1 Sigma = 455 ps

Time Difference in TDC (ns)

Tim

e D

iffe

ren

ce

in

FA

DC

(n

s)

Sigma = 490 ps

Resolution for time measurement in FADC : 210 ps Resolution for time measurement in FADC : 210 ps Starting from 10 ns Sampling Period !Assuming 100 ps resolution for the TDC measurement (including residual time walk)


LinearityLinearity

6 8 10 12 140

200

400

600

800

1000

-37 -36 -35 -34 -33 -32 -31 -30 -29 -280

100

200

300

400

500

600

700

800

900

Time difference in flash ADC (ns)Time difference in TDC (ns)

Trigger counter moved by + and - 10 cmTrigger counter moved by + and - 10 cm Peak shift: TDC not linear / FADC linear Refraction Index: TDCn = 2.2 / FADCn = 1.41 Sigma: Not constant / Constant

Time difference in TDC is sensitive to Time WalkTime difference in TDC is sensitive to Time Walk Moving the trigger detector changes the relative amplitudes in Left and Right

PMTs


Shaper designShaper design

2 stages2 stages vs vs 4 stages4 stages

Output is more symmetrical with 4 stagesOutput is more symmetrical with 4 stages Components can be adjusted to reduce the full width while Components can be adjusted to reduce the full width while

keeping the rise time > 4 sampleskeeping the rise time > 4 samples The aim is to keep the width <= 450 ps so that we can record 10 samples

before the signal (for the baseline measurement) and miss only one beam burst

It allows reducing the occupancy time It allows reducing the occupancy time => Reducing the level of segmentation in SW (less channels -> less $)

Same Charge resolution:Same Charge resolution:The 4 stages has more noiseThe 4 stages has more noiseBut also more gainBut also more gain

See Roumen’s talk


PID FEE for Stage 1PID FEE for Stage 1

SummarySummary

FADCFADC

V1724V1724ShaperShaper TDCTDC

V1290V1290DiscriDiscri

LS 4415ALS 4415A

TOF 0TOF 0 4040 4040 4040 4040

TOF1TOF1 2828 2828 2828 2828

TOF2TOF2 40?40? 40?40? 40?40? 40?40?

CKOVCKOV 88 88 -- --

KLKL 4242 4242 -- --

SWSW ???? ???? -- --

TOTALTOTAL 158 (+ SW)158 (+ SW)

= 20 boards= 20 boards158 (+ SW)158 (+ SW)

= 10 boards= 10 boards108 108

= 3 boards = 3 boards + 12 ch+ 12 ch

108 108

= 7 boards= 7 boards


FEE for Stage 1FEE for Stage 1

We have already 10 LS 4415A in handWe have already 10 LS 4415A in hand Ludovico has ordered 18 FADCs and 2 TDCsLudovico has ordered 18 FADCs and 2 TDCs Maurizio has ordered 1 TDCMaurizio has ordered 1 TDC Shaper production should start soonShaper production should start soon We should be ready to start with We should be ready to start with

EMCal(KL) / TOF0 / TOF1 / CKOVEMCal(KL) / TOF0 / TOF1 / CKOV For TOF2, we miss For TOF2, we miss

2 FADCs 1 TDC (actually, only 12 channels)

For EMCal(SW), we miss even the number of For EMCal(SW), we miss even the number of channels… channels…

The commercial agreement with CAEN is to buy 30 FADCs -> Min = 80 ch Original EMCal Design: 240 channels in total -> Max = 200 ch


Particle Trigger Technical Particle Trigger Technical DesignDesign

Work in ProgressWork in Progress The current plan is to use Lecroy Logic Unit The current plan is to use Lecroy Logic Unit

4516 (CAMAC)4516 (CAMAC) 2 in hand, 3 needed (one per TOF station) 9 available in CERN’s pool, (8 CHF/month, only

reduced support) VME – CAMAC interface available for programming

the logic (trivial programming) CAMAC crates available in Geneva

Time reference for the trigger is the Burst Time reference for the trigger is the Burst Gate Gate

Present in all trigger condition -> Time reference won’t change (same offline cuts)

Discussion ongoing on the availability of the Burst Gate..

TOF_0_U0

TOF_0_U9

TOF_0_L0

TOF_0_L9

TOF_0_L1

TOF_0_U5

. .

. .

. .

.

RG ; 45 mBNC FF

BNC - LEMO FF

RG ; 1 m

Splitter PCB16 ch

BNC FF

BNC - LEMO FF

BNC FF

BNC - LEMO FF

BNC FF

BNC - LEMO FF

. .

. .

. .

.

. .

. .

. .

.

TOF_0_U6

. .

. .

. .

.

. .

. .

Same picture for TOF_0_R and TOF_0_D

Same picture for TOF_2_R and TOF_2_D

Same picture for TOF_2_L and TOF_2_U

Dispatch Panel(in Hand)

These 4 channelsGoing to another

splitter

17 -Twisted PairsFlat cable, 96 OhmsSingle ended

RC shaper16 channels

Special Flat cable Only ten pairs connectedon a 17-pairs connector

TOF_0_L0

TOF_0_L9 TOF_0_U0

TOF_0_U5 Lecroy 4415Discriminator16 channels

17 -Twisted PairsFlat cable to Tdc

. .

. .

. .

. .

16 x ~6 ns special cablesto Flash ADC

17 -Twisted PairsFlat cable, 96 OhmsSingle ended

RC shaper16 channels

TOF_0_R0

TOF_0_R9 TOF_0_D0

TOF_0_D5

Lecroy 4415Discriminator16 channels

17 -Twisted PairsFlat cable to Tdc

. .

. .

.16 x ~6 ns special cablesto Flash ADC

Lecroy Logic unit

A

B

Same picture for TOF_2_L and TOF_2_R

ECL

ECL

Simplified picture for the 5th Splitter for the remaining channels of TOF0 and TOF2 (No Logic board)

Similar picture for TOF_1_L and TOF_1_R (only 14 channels used)

NIM logic from here

LEFT Pmts

RIGHT Pmts

2 by 2 coincidence

OR of 10 slabs

UP and DOWN Pmts are not used

for the trigger


Schedule MilestonesSchedule Milestones

Complete Flash ADC analysis: Complete Flash ADC analysis: Nov 2006Nov 2006 Actually assed in beginning of December BUT extended to test new shaper prototype with EMCal Pmts -> Feb

2007

DAQ Test bench including Event builder: DAQ Test bench including Event builder: Feb Feb 20072007

Delayed by ~ 1 month

Order Hardware for Stage 1: Order Hardware for Stage 1: March March 20072007

Critical item: Network Switches should be ordered at the end of March

Shaper production process will be launched Event builder will be ordered in April

Move DDAQ system to RAL: Move DDAQ system to RAL: July July 20072007

Still reachable


SummarySummary

DATE software training CompletedDATE software training Completed FE Electronics for PID has converged FE Electronics for PID has converged

to a valid solution achievable for to a valid solution achievable for Stage 1 Stage 1

DAQ test bench is lateDAQ test bench is late Particle Trigger technical design Particle Trigger technical design

progressingprogressing We still plan to install the DAQ We still plan to install the DAQ

system at RAL in Julysystem at RAL in July

detector daq status

Documents

equipment readout

daq event

rundate data formatthe

header file event

usedthe data format

miceeach equipment

ldcthe readout process

equipment fee tests