cleo-iii trigger & daq status
DESCRIPTION
CLEO-III Trigger & DAQ Status. Trigger Illinois (Cornell). DAQ OSU Caltech Cornell. 72 MHz. RF bucket. 24 MHz. Pipeline clk. Early DR. Late DR. Early CC. Late CC. look here for DR info. look here for CC info. Suppose event happens here. CLEO-III Trigger. Trigger Philosophy - PowerPoint PPT PresentationTRANSCRIPT
CLEO PAC 11/March/00 M. Selen, University of Illinois 1
CLEO-III Trigger & DAQ StatusCLEO-III Trigger & DAQ Status
TriggerIllinois
(Cornell)
DAQOSU
CaltechCornell
CLEO PAC 11/March/00 M. Selen, University of Illinois 2
Trigger Philosophy Make a sophisticated Level-1 trigger decision
(latency~2.5s) before invoking readout dead-time. Make trigger decision every 42ns (i.e. pipeline).
CLEO-III TriggerCLEO-III Trigger
(Tot)(nb)
(Barrel)(nb)
(Endcap)(nb)
e+e e+e 72 19 53
e+e 6.2 3.7 2.5
e+e + 0.72 0.60 0.12
e+e + 0.72 0.60 0.12
e+e hadrons 4
Total 84
At L = 3 x 1033 this corresponds to ~250 Hz.
Design CLEO-III trigger/DAQ for 1000 Hz max.
RF bucket
Pipeline clk
Early DR
Late DR
Early CC
Late CC
look here for CC info
72 MHz
24 MHz
look here for DR infoSuppose eventhappens here
CLEO PAC 11/March/00 M. Selen, University of Illinois 3
Mixer/ShaperBoards
AXTR(16) AXX(16)
DR3 Pre-amps
STTR(12)
TRCR
L1LUMI
G / CAL
DFC DAQ
CLEO
Ana
log
Gates
Con
tr.
Mixer/Shaper Crates (24)
TPRO(2)
TCTL
TIM
DM/CTL
TIM
DM/CTL
TIM
DM/CTL
TPRO(4)
TIM
DM/CTL
TIM
DM/CTL
AXPR
CCGL
SURF
SURF
Drift Chamber Crates
Axi
al tr
acke
rS
tere
o tr
acke
r
TILE (8)
QVME
Bar
rel C
CC
C D
igita
l
Leve
l 1 d
ecis
ion
Flo
w c
ontr
ol &
Gat
ing
L1DL1D
Patchpanel
TILE (8)
QVME
Bar
rel C
C
TILE (8)
QVME
End
cap
CC
CLEO-III Trigger: System InventoryCLEO-III Trigger: System Inventory
CLEO PAC 11/March/00 M. Selen, University of Illinois 4
Example (they all look similar):Level-1 Trigger Decision Board
VME/DAQ Interface
Trigger Logic Custom BP
Trigger Hardware ExampleTrigger Hardware Example
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FPGA based Logic
DAQ/VME
CircularBuffer
Inputs Outputs
TDITMSTCK
TDO JTAG
Common Trigger Board StructureCommon Trigger Board Structure
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Stereo (blocks)
Axial(all wires)
Tracking Trigger (Axial + Stereo)Tracking Trigger (Axial + Stereo)
CLEO PAC 11/March/00 M. Selen, University of Illinois 7
#tracks
ev-time time
2 trackEvents
Trigger Bucket
Finding the Event TimeFinding the Event Time
CLEO PAC 11/March/00 M. Selen, University of Illinois 8
Present summing = Tile summing =
Sim
ula
ted
E
ffic
ien
cy
containedshower
Threshold = 500 MeV
Energy sharing between boardscan result in a loss of efficiency:
CC TriggerCC Trigger
CLEO PAC 11/March/00 M. Selen, University of Illinois 9
Analog “TILE” BoardsAnalog “TILE” Boards
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Barrel(Crate 1 Card 13)
Endcap(Crate 21 Card 16)
Preliminary Peek at the CC Trigger DataPreliminary Peek at the CC Trigger Data
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1 m/s crate
CC Tile ProcessorCC Tile Processor
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LUT
8 FPGAs
Timing (3)
Info (185)
Timing (TR, CB or CE)
Info (valid at timing edge)
Route48 Prescale24 Bunch24
Scaler
L1-accept
Bac
kpla
ne
Level 1 DecisionLevel 1 Decision
CLEO PAC 11/March/00 M. Selen, University of Illinois 13
% Generic Hadron Line, Barrel Timing%SUBDESIGN line0(
in[117..0] : INPUT;out : OUTPUT;
)
Variable1cblow : SOFT;3tracks : SOFT;evtime : SOFT;
Begin-- trigger bit mappings:
tr_time[1..0] = in[1..0];cb_time[1..0] = in[3..2];ce_time[1..0] = in[5..4];cc_time[1..0] = in[7..6];
tr_n_hi[3..0] = in[11..8];tr_n_lo[3..0] = in[15..12];tr_n_ax[3..0] = in[19..16];tr_lowpos[1..0] = in[21..20];
cb_l_phi[7..0] = in[29..22];cb_h_phi[7..0] = in[37..30];
cb_low_old[1..0] = in[39..38];cb_med_old[1..0] = in[41..40];cb_high_old[1..0] = in[43..42];ce_low_old[1..0] = in[45..44];ce_med_old[1..0] = in[47..46];ce_high_old[1..0] = in[49..48];
cb_n_low[2..0] = in[52..50];cb_n_med[2..0] = in[55..53];cb_n_high[2..0] = in[58..56];ce_n_low[2..0] = in[61..59];ce_n_med[2..0] = in[64..62];ce_n_high[2..0] = in[67..65];
bha_theta[7..0] = in[75..68];
cc_spare[15..0] = in[91..76];
cpu_trig[1..0] = in[93..92];
control[23..0] = in[117..94];
------------------------------------------------ trigger line definition
1cblow = cb_n_low[] > 0;
3tracks = (tr_n_hi[]>2) # ((tr_n_hi[]>1)&(tr_n_lo[]>0)) #((tr_n_hi[]>0)&(tr_n_lo[]>1)) ;
evtime = cb_time[0];
out = 1cblow & 3tracks & evtime;
End;
Writing Trigger LinesWriting Trigger Lines
CLEO PAC 11/March/00 M. Selen, University of Illinois 14
All components (except STTR) boards installed and functioning.Used for collecting engineering run dataMany bugs shaken out (all readout related)Some minor readout bugs remain, and will be fixed.
Stereo tracking (STTR) boards will be installed by the end of March.8 of 12 needed boards tested (and working) as of today, the balance (4 + spares) will be shipped to LNS by the end of next week.
Majority of trigger groups effort turning to software development.Much already exists (readout, sparsification, board debugging & testing, expert online tools).More user friendly (GUI) code being developed.Monte Carlo ~90% finished.
Trigger StatusTrigger Status
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CLEO III DAQ ArchitectureCLEO III DAQ Architecture
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Readout ControllerReadout Controller
VMEPowerPC + VxWorks
FastbusVME-Fastbus Interface (FRITZ)
VME CPU
FastbusInterface
LUTs
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CLEO III Slow Control StructureCLEO III Slow Control Structure
CORBA
Crates
Gas
DatabaseHV
Magnet
Beam
Run Control
Event Builder Level 3
UserConsole(Java)
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All key components installed and functioning.True for both Data Path & Slow Control
32 PowerPC crate-based CPU’s used “simultaneously” during engineering run!8 VME crates reading out the 230000 RICH channels.3 VME crates reading out the trigger system.2 VME crates reading out the Silicon Vertex System.4 FASTBUS crates reading out the CC via FRITZ 8 FASTBUS crates reading out the DR via FRITZ.7 PowerPC’s performed slow control tasks.
Event Builder worked as expectedThis is a big deal !
The system will grow slightly for “complete CLEO-III” data-taking in April1 additional VME crate reading out the stereo trigger.3 additional VME crates for reading out the silicon.
Stability and “User Friendliness” improving every day.
DAQ StatusDAQ Status