copyright 1998 morgan kaufmann publishers, inc. all rights reserved. digital architectures1 machine...

Digital Architectures 1

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved.

Machine instructions execution steps

(1) FETCH = Read the instruction from memory using PC as the ptr

(2) DECODE = Decode the instruction (decide what to do next) and read the necessary registers (1 or 2)

(3) EXECUTE = Calculate the result or a memory address by the ALU

(4) MEMORY = Use the ALU result to access the memory if required (read data in load, write data in store)

(5) WRITE BACK = If required, write the result into the appropriate

register



We “read” during the entire CK cycleWe write at the end of the CK cycle

cycle time

rising edge

falling edge

The control lines: Those are produced by the CK. Every rising edge of

the CK causes the appropriate changes of the control lines.



A simplified MIPS CPU

ALUPCInstruction

Instructionmemory

#register

Registers

Data

#register

#register

address

Datamemory

Data

The connections shown above supports all phases of R-type and I-type instructions. Our design will support add, sub, or, xor, and, slt, lw, sw, beq, j instructions. We should be able to add more instructions, e.g., bne, addi, jal, jr.



The basic CPU parts needed for the Fetch phase:

InstructionAddress

Instruction

InstructionMemory

PC

Write

Add

Sum

It is clear that we need a PC register, a memory to store the instructions and an adder to increment the PC.



The Fetch phase

Add

PC Readaddress

Instruction

Instructionmemory

32

32

32



A CPU capable of R-type instructions only

5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

InstructionMemoryPC

Adder4

ck

6[31:26]

6[5:0]=funct

PC 0x400000 0x400004

Memory output New Memory output

fetch fetch

32



The general register file (GPR). This unit is required for the decode phase (and for the Write Back phase)

Readregister 1

Registers

Readregister 2

Write register

WriteData

Readdata 1

Readdata 2

The registers indices

Data

32

32

32

5

5

5



Arithmetic Logic operation

Readregister 1

Registers

Readregister 2

Write register

WriteData

Read

data 1

Readdata 2

ALU

Zero

ALU operation

ALUresult

Instruction

ALU

ALU

result

ALU operation

The basic operation we demonstrate is an R-type instruction

32

32

32 32

32

32

5

5

5




5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

Reg File

InstructionMemoryPC ALU

Adder4

ck

ck

6[31:26]

6[5:0]=funct

PC 0x400000 0x400004

Rs, Rt ALU inputs new ALU inputs


fetch decode fetch decode

32

32

32

32




5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

Reg File


Adder4

ck

ck

6[31:26]

6[5:0]=funct

PC 0x400000 0x400004

Rs, Rt ALU inputs new ALU inputs

ALU output


New ALU output

fetchWrite backdecode execute

32

32

32

32



The internal structure of the Register File

32

32

3232

32

32

32

32

32

32

32

Read data 2

write data

Read data 1

5

5

5

Rd reg 2 (= Rt)

Rd reg 1 (= Rs)

RegWrite

Wr reg (= Rd) 32

32

E

We read 2 different registers from the 2 outputs simultaneouslyWe write to one of the registers (in the next rising edge of the CK).




5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

Reg File


Adder4

ck

ck

6[31:26]

RegWrite

32

32

32

32




5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

Reg File

InstructionMemory

PC ALU

ck

ck

32

32

32




5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

Reg FileInstructionMemory

PCALU

ck

ck

4

32

32

32

32




5[25:21]=Rs

5[20:16]=Rt

5[15:11]=Rd

Reg File


Adder4

ck

ck

6[31:26]

RegWrite

6[5:0]=funct ALUcontrol

32

32

32

32



Building the Load and Store operations

Signextend

16 32

Readaddress

Datamemory

Writeaddress

Writedata

Readdata

Write

Read Here we need Data memory from which we read (and to which we write). We also need to perform sign extension to the 16 bit imm .

32

32

32

32



A CPU capable of lw instructions only

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite=1

16[15:0]

5

add

Sext16->32

DataMemory

Address

D. Out

32

32

32

32

32

32




5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite=1

16[15:0]

5

add

Sext16->32

DataMemory

AddressD. Out

PC 0x400000

Rs, Rt ALU inputs

ALU output(address)

Inst. Memory output

fetch Write back

decode execute

Memdata

memory

0x400004

new ALU inputs

New ALU output(new address)

new Instruction

fetch Write back

decode execute

Memdata

memory

D. Memdata

D.Mem adrs

I.Mem data

32

32

32

32

32




5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite=1

16[15:0]

5

add

Sext16->32

DataMemory

AddressD. Out

32

32

32

32

32



A CPU capable of lw & sw instructions only

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite=0

16[15:0]

5

add

Sext16->32

DataMemory

D.In

Address

MeWrite=1

32

32

32

32

32



A CPU capable of R-type & lw instructions (principle)

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite

16[15:0]

5

add

Sext16->32

DataMemory

5[25:21]=Rs


5[15:11]=Rd

Address

32

3232

32

32

32



A CPU capable of R-type & lw instructions

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite

16[15:0]

5

add

Sext16->32

DataMemory

5[25:21]=Rs


Rd

AddressD. Out

32

32

32

32

32

32

32



A CPU capable of R-type & lw/sw instructions

5[25:21]=Rs

5[20:16]=Rt

Reg File


Adder4

ck

ck

6[31:26]

RegWrite

16[15:0]

5

add

Sext16->32

DataMemory

5[25:21]=Rs


Rd

Address

D.In

D. Out

MemWrite

32

32

32

32

32

32

32

32



Elements needed for Branch instruction

ALU

Zero

Readregister 1

Registers

Readregister 2

Write register

WriteData

Readdata 1

Readdata 2

Instruction

AdderSum

Shiftleft 2

SighExtend

BranchTarget

The zero signalis transferred tothe control unitas the result of the comparison

16 32

PC+4 after Fetch

In addresses, we always shift left by two bits

32

32

32



Combining all of the instructions

Readregister 1

Registers

Readregister 2

Write register

WriteData

Readdata 1

Readdata 2

Zero

ALU

ALUresult

Data

Signextend 32

Readaddress

memory

Writeaddress

Writedata

Readdata

Write

Read

16

Add4

PC

Mux

Readaddress

Instruction

Instructionmemory

ADD

ALUresult

Shiftleft 2

Mux

Mux



Where is the CPU?

CPU

InstructionMemory

DataMemory

PC



Control lines

PC

Instructionmemory

Readaddress

Instruction

16 32

AddMux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

AddALU

resultShiftleft 2



Control

PC

Instructionmemory

Readaddress

Instruction]31– 0[

Instruction ]20– 16[


Add


MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc


4

16 32Instruction ]15– 0[

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1


ALUcontrol

ALUAddress



Instruction RegDst ALUSrcMemto-

RegReg

WriteMem Read

Mem Write Branch ALUOp1 ALUp0

R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1

R-format Iw sw beq

Op0

Op1

Op2

Op3

Op4

Op5

Inputs

Outputs

RegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOpO

Control



ALU control

ALUOp Funct fieldALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X0 1 X X X X X X1 0 X X 0 0 0 01 0 X X 0 0 1 01 0 X X 0 1 0 0

ALU control input

000 AND001 OR010 add110 subtract111 set-on-less-than

(sign of rs-rt -> rd)

00 = lw, sw (add)01 = beq (sub) 10 = arithmetic (see table)

ALUop:

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5– 0)

ALUOp0

ALUOp

ALU control block

0 1 01 1 00 1 01 1 0

0 0 0

Operation[2:0]

Digital Architectures


The Jump instruction

4 bits 26 bits 2 bits

Jump address in words:

Jump address in bytes:00

0101

101 … 101111011

101 … 101111011

101 … 101111011

00 101 … 1011110110101Final jump address in bytes:

Adding the 4 MSBs:

The instruction: J 101…101111011

means that the next instruction is in address 101…10111011

(actually in word 101…10111011)



Jump

Shiftleft 2

PC

Instructionmemory

Readaddress

Instruction]31– 0[

Datamemory

Readdata

Writedata

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2




Add

ALUresult

Zero


MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

JumpRegDst

ALUSrc

I nstruction ]31– 26[

4

Mux

Instruction ]25– 0[ Jump address ]31– 0[

PC+4 ]31– 28[

Signextend

16 32Instruction ]15– 0[

1

Mux

1

0

Mux

0

1

Mux

0

1

ALUcontrol

Contr ol

Add ALUresult

Mux

0

1 0

ALU

Shiftleft 2

26 28

Address



End of single cycle implementation

copyright 1998 morgan kaufmann publishers, inc. all rights reserved. digital architectures1 machine...

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