coa presentation by sunil

8/9/2019 Coa Presentation by Sunil

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C0A0A

PRESENTATIONRESENTATIONBy Sunil Kumar SharmaBy Sunil Kumar Sharma



Outlineutline

Bus And Memory Transfer Bus And Memory Transfer

§



RegisteregisterTransferransfer§ Data can move from register to register.Data can move from register to register.

§ Digital logic used to process dataDigital logic used to process data

for example:for example:

Register A Register B

Register C

Digital Logic

Circuits

C A + B



Building auilding a

Computeromputer

Needs:Needs:§ processingprocessing

§ storagestorage

§ communicationcommunication



Multiplexer-Based Transferultiplexer-Based Transfer

foror TWOTWO 4-bit registers4-bit registers

Use of Multiplexers to Select between Two Register

0

1



Bus Transferus Transfer

§ For register R0 to R3 in a 4 bit systemFor register R0 to R3 in a 4 bit system

*

S1 S0 Register selected0 0 A

0 1 B

1 0 C

1 1 D

S1

S0

4-line

common

bus

Register D Register C Register B Register A

Used for highest bit from eachregister

Used for lowest bit



Three-State Bushree-State Bus

Buffersuffersl A bus system can be constructed withA bus system can be constructed with three-statethree-state

gatesgates instead of instead of multiplexersmultiplexers

l Tri-State : 0, 1, High-impedance(Tri-State : 0, 1, High-impedance(Open circuit Open circuit ))

l

§ Buffer Buffer

§ A device designed to be inserted between other devicesA device designed to be inserted between other devicesto match impedance, to prevent mixed interactions,to match impedance, to prevent mixed interactions,

andand to supply additional drive or relay capability to supply additional drive or relay capability l

§



Tri-state buffer gateri-state buffer gate

§ Tri-state buffer gate : Fig. 4-4Tri-state buffer gate : Fig. 4-4

§ When control input =1 : The output isWhen control input =1 : The output is

enabled(output Y = input A)enabled(output Y = input A)

§ When control input =0 : The output isWhen control input =0 : The output isdisabled(output Y = high-impedance)disabled(output Y = high-impedance)

§

Normalinput A

Controlinput C

If C=1, Output Y = A

If C=0, Output = High-impedance



The construction of a busThe construction of a bus

system with tri-state buffer system with tri-state buffer

A0

B0

C0

D0

Select input

Enable input



Memory Transferemory Transfer

§ The transfer of information from aThe transfer of information from a

memory word to the outsidememory word to the outside

environment is called aenvironment is called a readread operationoperation§ The transfer of new information to beThe transfer of new information to be

stored into the memory is called astored into the memory is called a

writewrite operationoperation§



Memory Read andemory Read and

Writerite§ AR: address register AR: address register

§ DR: data register DR: data register

Read: DRRead: DR M[AR]M[AR]

Write: M[AR]Write: M[AR] R1R1



Arithmeticrithmetic

MicrooperationsicrooperationsSymbolic designation Description

R3 ← R1 + R2 Contents of R1 plus R2 transferred to R3

R3 ← R1 – R2 Contents of R1 minus R2 transferred to R3R2 ← R2 Complement the contents of R2 (1’s complement)

R2 ← R2 + 1 2’s Complement the contents of R2 (negate)

R3 ← R1 + R2 + 1 R1 plus the 2’s complement of R2 (subtract)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 – 1 Decrement the contents of R1 by one

Multiplication and division are not basic arithmetic operationsMultiplication : R0 = R1 * R2Division : R0 = R1 / R2



Arithmeticrithmetic

Microoperationsicrooperations§ A single circuit does both arithmetic additionA single circuit does both arithmetic addition

and subtraction depending on controland subtraction depending on control

signals.signals.§

§ •• Arithmetic additionArithmetic addition::

§ R3R3 R1 + R2 (Here + is not logical OR. ItR1 + R2 (Here + is not logical OR. Itdenotes addition)denotes addition)

§



Arithmeticrithmetic

Microoperationsicrooperations§ Arithmetic subtractionArithmetic subtraction::

§ R3R3 R1 + R2 + 1R1 + R2 + 1

§ where R2 is the 1where R2 is the 1’’s complement of R2.s complement of R2.

§ Adding 1 to the oneAdding 1 to the one’’s complement iss complement is

equivalent to taking the 2equivalent to taking the 2’’ss

complement of R2 and adding it to R1.complement of R2 and adding it to R1.

§



BINARY ADDERBINARY ADDER

§ Binary adder is constructed with full-Binary adder is constructed with full-

adder circuits connected in cascade.adder circuits connected in cascade.



BINARY ADDER-INARY ADDER-

SUBTRACTORUBTRACTOR•• The addition and subtraction operations cane beThe addition and subtraction operations cane be

combined into one common circuit by including ancombined into one common circuit by including anexclusive-OR gate with each full-adder.exclusive-OR gate with each full-adder.

§XORXOR

M bM b

0 0 00 0 0

0 1 10 1 11 0 11 0 1

1 1 01 1 0




SUBTRACTORUBTRACTOR§ •• M = 0: Note that B XOR 0 = B. This isM = 0: Note that B XOR 0 = B. This is

exactly the same as the binary adder exactly the same as the binary adder

with carry in C0 = 0.with carry in C0 = 0.§

§ M = 1: Note that B XOR 1 = B (flip all BM = 1: Note that B XOR 1 = B (flip all Bbits). The outputs of the XOR gates arebits). The outputs of the XOR gates are

thus the 1thus the 1’’s complement of B.s complement of B.§ M = 1 also provides a carry in 1. TheM = 1 also provides a carry in 1. The

entire operation is: A + B + 1.entire operation is: A + B + 1.




SUBTRACTORUBTRACTOR



4-bit Binary-bit Binary

Incrementerncrementer

x y

B3 B2 B1 B0 1

Always added

to 1

C4 S3 S2 S1 S0



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