chip-package codesign · pdf fileglobal clock distribution ... ibis models. franzon 32...

ChipChip--Package Package CoDesignCoDesign-- Challenges and DirectionsChallenges and Directions

Paul FranzonToby Schaffer, Alan Glaser, Andy Stanaski, Yusuf

Tekmen, Mouna NakkarNorth Carolina State University

[email protected]/erl

Funding:

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OutlineOutline

High Density Packaging Trends

Chip-Package Codesign Trends

CAD Tools for Codesign

Codesign CAD at NCSU

•High density•3-D•Embedded Passives

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Package Technology TrendsPackage Technology Trends> The trend to miniaturization

Wireless systems - COB, DCAHigh pin-count systemsHigh speed interfaces (400 MHz)

> Packaging adding value to the systemHigh density, low-cost packagingThree-D packagingEmbedded passivesIntegration of sensors (MEMS)

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High Density Packaging TrendsHigh Density Packaging Trends> Current technology:

250 µm solder bump pitch50 µm wire pitch50 µm via pitch

> SHOCC Program50 µm solder bump pitch30 µm wire pitch

> Georgia TechLarge panel processing

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33--D MCM DesignD MCM DesignNew IdeasNew Ideas•Low cost edge mounting technology

•Invented at MCNC•Based on solder bumps

•Applications:•Self-aligning 3-D “null-seeking radar”•High density DRAM ‘SIMM’ module•MEMS, Analog integration

ImpactImpact•Cost Reduction in low-weighthigh-density memories

•Self-aligning 3-D structures•Low cost

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Integration of SensorsIntegration of Sensors> Examples:

RF ComponentrySensor/IC MCM

◊ Accelerometers◊ LiDAR

> ChallengesPackaging cost > MEMS costTest cost > MEMS costCodesign of MEMS and analog/digital signal processing

birefringent substrate w/ two polarization selective CGH’s

1/4 wave rotator plate

polarizing beam-splitter

thinned MEMS mirror with vertical interconnect

silicon chip with an individually addressable driver circuit array

Prototype Reflective Beam Steerer

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OutlineOutline





•NCSU•Alpine•Lucent

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CoCo--Design for Flip Chip & thinDesign for Flip Chip & thin--filmfilmNew IdeasNew Ideas•Use low-R HDI copper for:

•on-chip power/ground distn•1-level clock distribution•RAM interfacing

•Build high BW memory systems•512-bit buses•800 Mbps I/O signalling ImpactImpact

•5% - 30% IC size reduction•150 ps clock skew reduction•25% clock power reduction•Improved noise management•High bandwidth memory for DSP

Toby Schaffer, Alan Glaser, Steve Lipa, Paul Franzon

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Optimizing the Interconnect MixOptimizing the Interconnect MixLow-cost, high-density interconnect technologies

+

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TripleTriple--DES ModuleDES ModuleData Encryption Standard Module - Encrypt, Decrypt, and Cracking

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IC ImplementationIC Implementation> CMOS three metal, 0.6µm technology> Test structures: full scan, PRNG, SAR> 123,104 transistors> 210 pads used

inputs: 18 clock, 15 control, 64 dataoutputs: 67power: 23, ground: 23

> 5.78mm X 3.67mm (21.2mm2)> Global P/G/C distribution is provided by MCM

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Implementation: The ChipImplementation: The Chip

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Area Array P/G/Clock DistributionArea Array P/G/Clock Distribution> eliminates large global rails

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Power Distribution ArchitecturePower Distribution Architecture

Integrated Decoupling Capacitors•MCM = 700 -10,000 pF/sq.cm.•IC = 2.5 - 5.0 pF/sq.mm.

(at 5% fill : 12.5 - 25 pF/sq.cm)

Would not work for MCM-C/L:- via inductance too high(0.05 nH vs. 0.5 nH)

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Power Distribution Power Distribution -- IR dropIR dropHigh density solder bumping releases on-chip wiring

resources.

Requirements tokeep IR drop to15 mV.

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Global Clock DistributionGlobal Clock Distribution> Distribute Global Clock on low-R MCM layers

Reduced clock skew (shallower clock tree)Reduced clock power (smaller crowbar current)Transmission line distribution schemes

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Global Clock DistributionGlobal Clock Distribution> i.e. For conventional clock trees:

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Laboratory Test Equipment SetupLaboratory Test Equipment Setup

PC and HFS 9009 Stimulus GeneratorPC and HFS 9009 Stimulus Generator

TLA 216 LogicTLA 216 Logic

scopescope

Logic AnalyzerLogic Analyzer

DPODPO

OscilloscopeOscilloscope

DUTDUT

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Probing the MCMProbing the MCM

• High-impedance active probe for measuring Vdd noise and clock skew

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> Results:110 MHz2.5 GBps encrypt/decrypt

Measured IC Performance Measured IC Performance (Speed)(Speed)

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DES MCM Power Plane NoiseDES MCM Power Plane Noise

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Clock Distribution Clock Distribution -- DES MCMDES MCM

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Clock Distribution Clock Distribution -- DES MCMDES MCM

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GCLK Distribution on MCMGCLK Distribution on MCM> 25% GCLK Power Reduction when GCLK

distributed on MCM

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SSN Measurement ICSSN Measurement IC> Addresses on-chip noise issues in flip-chip

environmentCore noise contribution significantGreater on-chip exposure to SSNIntend to produce suitable macromodels

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Alpine SystemsAlpine Systems> Achieving greatly decreased footprint with

careful codesign across multiple levels of interconnect

2,000 I/O pins in a 256-pin BGA

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Embedded PassivesEmbedded Passives> Frye, Lucent, Bell Labs

Passives

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OutlineOutline





•Current Status•Future Needs

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Packaging CAD StatusPackaging CAD Status> IC and package tools very separated:IC Physical Design Package Physical Design

Package Modeling/SimulationOn IC Modeling/Simulation

I/O LocationsIBIS Models

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Packaging CAD StatusPackaging CAD Status> Current points of integration concentrate on

single net SI and routability, mainly at the board level

e.g. Xinetix EDA Navigator or Cadence SpectraQuest

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> On-chip noise issues becoming criticalRequires co-modeling of chip and package

> Routing Resources becoming very tightFlip-chip breakout can be difficultOn-chip interconnect dominating on-chip delaysMiniaturization in RF systems leads to very constrained board designs

> Must seek codesign opportunitiesDigital - optimal interconnect allocationAnalog - embedded passivesMust include process variations of chip and package

Future Design IssuesFuture Design Issues

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Breakout IssuesBreakout Issues> To breakout a large number of pads with a river

route requires intensive routing resources:

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Possible Future FlowPossible Future FlowIC Physical Design•Floorplanner•Net planner

Package Physical Tools•Preliminary Layout•Net plannerPad locations

Circuit (driver) Models•process variationsOn-chip delay rangeNoise susceptibility

Routability•BreakoutPackage delay

Automatic I/O placment tool

Back-Annotation

Back-Annotation

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•SSN Macromodels•On-chip Noise Margin

Requirements

...Possible Future Flow...Possible Future Flow

IC Extractionand AnalysisTools

Packaging ExtractionTools

Signal Integrityand PerformanceAnalysis

•Package parasitics•Inter-chip Noise Margin

Requirements

•On-chip SI•Off-chip SI•Performance verification(across process and temp)Back-Annotation

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OutlineOutline




Codesign CAD at NCSUConcentratingon on-chip blockand I/O placement

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Performance Driven ICPerformance Driven IC--placementplacement> Goals:

Place on-IC blocks and I/O to ◊ minimize longest delay◊ ensure routability

> ApproachSimulated annealing placementWeighted Trunk Tree length estimatorDelay mean and standard deviation used in objective function Routing Resource Metric used in objective function

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Yusuf Tekmen, Real Pommerleau, Paul Franzon, Grif Bilbro

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Weighted Trunk Tree LengthWeighted Trunk Tree LengthResults lengths within 1% of Cadence silicon ensemble actual lengths. (Other methods typically 5% accurate.)

TXX

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Routability Routability EstimationEstimation> Routing Resource Metric

pitch wireEffective:(WTT) lengthct interconne EstimatedTotal:L

routingfor modules offactor nUtilizatio:Kmodulesby occupiedArea :

area routing Total:

T

M

W

M

T

TW

MMT

AA

LAKARRM

λ

λ−=


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ResultsResults> Placed and routed ten experiments (routing

using Cadence Silicon Ensemble)Designs 1.3x faster on average than with conventional methodsFaster convergence on correct design - One iteration in each case

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path−del (ns)

num

ber

of o

ccur

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Conventional Method

Proposed Method

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ConclusionsConclusions> The relationship between electronic packaging

design and IC design is becoming strong:Package adding value to ICPackage noise affecting IC designHigh pin count systems

> New design approaches and tools are neededCodesign across disciplinesIntegrated tool flows to solve important problems

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PerformancePerformance--drive IC placementdrive IC placement

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Impact:

Sample Designs are 1.3x faster

No timing violations after first iteration between placement and detailed routing

New Ideas:Estimators

Weighted Trunk Tree (WTT)

Pre-characterized Delay Models

Routing Resource Metric (RRM)

Dynamic Path-Delay Minimization

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path−del (ns)

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ber

of o

ccur

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Conventional Method

Proposed Method


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High Density Packaging TrendsHigh Density Packaging Trends> Short Term

Increased penetration of Direct Chip Attach (DCA) (solder balls) and Chip-On-Board (COB)

◊ Increased scope for package-induced SSN noise impacting on-chip design and functionality

◊ Layout difficulties in high pin count systems

High speed interfaces require careful codesign of chip and package

◊ 400 MHz buses becoming common

> Long TermPackage technology adding value to the system

◊ High density, low-cost packaging◊ Embedded passives

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Clock DistributionClock Distribution> On-MCM H-tree removes level of clock tree, eliminating up to

150ps of process-induced skew

MCM-D substrate

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High Density Packaging TrendsHigh Density Packaging Trends> Reduced Chip Test Cost for High I/O Chips

2,000 I/OMembrane tester

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Examples of Emerging Design Examples of Emerging Design StylesStyles> Integrated IC-package functionality

NCSU workAlpine SystemsLucent RF Module (above)

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Future Design OpportunitiesFuture Design Opportunities> Mixed Signal

First-pass design success very difficult, and even more difficult with embedded passivesIssues:

◊ System Modeling◊ Co-simulation◊ Independent Process Variations

> Mixed TechnologyMEMS Sensors in general

◊ System Modeling Problem

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Solution PathsSolution Paths> Take Lead from IC World:

> Flows - tightly integrated tool sets to solve particular problems

> e.g. Possible I/O Planner Flow for flip-chip, thin-film packages

Problems being addressed:◊ Signal integrity due to on-chip and on-package noise◊ I/O placement to satisfy performance and routability

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DiscussionDiscussion> Why will a flow like this be important?

On-chip noise dominated by package issuesEnsure first time success in:

◊ High pin count designs◊ Mixed-signal Systems

> A flow like this is difficultTightly integrated hetergenous tool setDifferent vendorsPoint tools not designed with flows in mind

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High bandwidth MEMSHigh bandwidth MEMS--switchesswitchesNew IdeasNew Ideas•Low Impedance MEMS programmable capacitor ‘switches’

•Pulse signaling through programmable capacitor array

•Each MEMS switch individually controllable via row and column addressing only

ImpactImpact•1 Gbps crossbar

•32x32 to 196x196•Suitable as RF switches also:

•Phased array for low costradars and directional wireless communications

Bruce Duewer, Umet Eksi, John Wilson, Dr. Wentai Lui

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MEMSMEMS--based laser radarbased laser radar

birefringent substrate w/ two polarization selective CGH’s

1/4 wave rotator plate

polarizing beam-splitter

thinned MEMS mirror with vertical interconnect

silicon chip with an individually addressable driver circuit array

Prototype Reflective Beam Steerer

New IdeasNew Ideas•Programmable hologram based on MEMS array

•6 degrees of steering•Organized as >400 8x8 subarrays•Each subarray requires 8 address lines only

ImpactImpact•Makes laser radar feasible

•‘fine’ steering capability•adaptive optics

•Potential for•3D machine vision•optical interconnect

Jeremy Palmer, David Winick

chip-package codesign · pdf fileglobal clock distribution ... ibis models. franzon 32...

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