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Slide - 1 Electronic Packaging for Wearable ElectronicsSavanSys Solutions LLC

Electronic Packaging for Wearable ElectronicsSavanSys Solutions LLC

Slide - 1

Chip Packaging for WearablesChoosing the Lowest Cost Package

Alan PaleskoSavanSys Solutions [email protected]

(512) 402-9943www.savansys.com

mailto:[email protected]


Agenda

Introduction

Wearable Requirements

Packaging Technologies and Cost Drivers

Technology Cost Comparisons

Summary


About SavanSys Solutions LLC

Timeline• 1995: Founded as a spin-off of Microelectronics and Computer Consortium

(MCC) in Austin, TX.

Began with cost modeling for PCB and MCM fabrication and assembly.

• 2005: Partnered with TechSearch International to expand line-up of cost models to include electronics packaging.

Wire bond, flip chip, fan-in WLP, fan-out WLP, embedded die, etc.

• 2012: Initiated development of TSV, 2.5D and 3D fabrication and assembly modeling.

Customers• We have modeled suppliers in: Japan, Malaysia, Taiwan, China, Korea,

Finland, and the US.

• Customers include: semiconductor giants, fabless semiconductor companies, OEMS, system design houses, and more.

• Our customer base is worldwide, with customers in Asia, Europe and the US.


Cost Modeling For. . .

Cost Reduction/Optimization• Size, Yield, and Cost Design Planning

• New Technology Adoption Cost Analysis

• Technology Platform and Process Comparison

Supply Chain Collaboration• Characterize Supplier Capabilities

• Consistent and Predictable Behavior


In Search of the Optimal Packaging Choice

Cost

Technology options

OPTIMALPRODUCT

Optimal Product The lowest cost technology choice that meets product requirements


Components of Total Cost / Price

Labor Cost

Capital/Depreciation Cost

Material Cost (Consumables and Permanent)

Tooling/NRE Cost

Scrap / Rework Cost

Indirect Labor Cost

Factory Overhead Cost

Corporate Overhead Cost

Profit Margin

Risk Factor

DirectCost

IndirectCost

Margin

UsuallyApplied

as aPercentageOn Direct

Cost


Example Wearables

SMS Audio BioSport In-Ear Headphones

* Teardown photos by Chipworks

Huawei Talkband B2


Market Requirements for Wearables

Data Collection – Sensors• Low Cost

• Small

• Flexible / Washable / Invisible

• Water proof / Sweat proof

Data Processing and Communication• Bluetooth, WIFI, Cellular?

• Small, but may be rigid

• Water proof / Sweat proof

• Shock Resistant

• Low power

• Light

• Bio compatible


Wearables are not Smart Phones

Size constraints in all dimensions• Not just thin

Less data processing requirements• Minimal local data processing. Collect data and send off to smart phone, fog,

or cloud

No access to a battery as large as a cell phone

Much tougher physical requirements• Flexible, washable, sweat-proof, drop-proof, etc


Total Cost Relationship to Test/Scrap Opportunities

Traditional Packaging• Three opportunities to scrap at three different factories

Advanced Packaging• Possibly less than three opportunities to scrap

Scrap Die & Package

DiceTest

Wafer Probe

Fabricate

Package

Scrap Bad Substrates

Package

AssemblyTest

Test Complete Product

Fabricate

Semiconduc

tor Wafer

Scrap Bad Die

Scrap

Test


Yield Loss Example

TechnologyTest/scrapdie before assembly?

Test/scrapsubstrate

before assembly?

Test/scrap after

assembly ?

Cumulative Yield

Wire Bond Yes Yes Yes 90%

Flip Chip Yes Yes Yes 90%

Fan-out WLP Yes No Yes 81%

Embedded Die Yes No Yes 81%

Fan-in WLP No No Yes 73%

Assume following yields for all packages:90% Die Yield90% Fabrication Yield90% Assembly Yield


Wire Bond Technology

Process Flow1. Fabricate substrate or leadframe

2. Die bond chip to package (pads face up)

3. Wire bond die pads to substrate/leadframe pads

4. Mold

Cost Drivers• Wire cost (if gold)

• Number of wire bonds

• Package size

Summary• Almost always the lowest cost option if product requirements (size,

performance, etc.) can be met


Flip Chip Technology

Process Flow1. Fabricate substrate

2. Wafer bump die

3. Die bond chip to package (pads face down)

4. Underfill

5. Mold / Lid

Cost Drivers• Wafer bumping cost

• Underfill process

• Substrate cost

Summary• Good choice for high IO count dies with challenging size requirements


WLP, FOWLP, Embedded Die Technology

Process Flow1. Start with either wafer (fan-in WLP) or die (fan-out WLP, embedded)

2. Place die on tape or partially completed organic substrate

3. Add RDL for interconnect to die

Cost Drivers• Compound yield loss

• RDL process

Summary• Best option to meet difficult miniaturization requirements

• Suitable for small die


Activity Based Cost Modeling

Cost Components of each Activity• The time required to complete the activity

• The amount of labor dedicated to the activity

• The cost of material required to perform that activity – both consumable and permanent material

• Any tooling cost

• The depreciation cost of the equipment required to perform the activity

• The yield loss associated with the activity

Sample Output

Substrate Labor Material Capital Tooling Yield Macro Running Total

2-[IL-Core] $0.0007 $0.2000 $0.0007 $0.0000 $0.0000 $0.0000 $0.2014

3-[IL-Photoresist] $0.0007 $0.0120 $0.0011 $0.0000 $0.0000 $0.0000 $0.2152

4-[IL - Image] $0.0007 $0.0144 $0.0045 $0.0000 $0.0000 $0.0000 $0.2349

5-[IL-DES] $0.0009 $0.0072 $0.0088 $0.0000 $0.0000 $0.0000 $0.2517

6-[IL - Oxide] $0.0010 $0.0001 $0.0026 $0.0000 $0.0000 $0.0000 $0.2554

7-[IL-AOI]-[Setup] $0.0001 $0.0000 $0.0006 $0.0000 $0.0000 $0.0000 $0.2561

7-[IL-AOI]-[Test] $0.0025 $0.0000 $0.0099 $0.0000 $0.0000 $0.0000 $0.2686


Trade Off Scenario 1 – Packaging Technology vs. Package Size

3.5mmx3.5mmPackage - WLP

4mmx4mm Package- FOWLP, FC

5mmx5mm Package- WB

100 IO



7mmx7mm Package- WB

225 IO



9mmx9mm Package- WB

400 IO

9.5mmx9.5mmPackage - WLP10mmx10mm

Package - FOWLP, FC11mmx11mmPackage - WB

625 IO



900 IO



1225 IO

WLP $0.09 $0.23 $0.46

FOWLP $0.12 $0.25 $0.44 $0.69 $1.02 $1.44

FC PBGA $0.22 $0.40 $0.68 $1.06 $1.48 $2.08

WB PBGA $0.17 $0.29 $0.44 $0.65 $0.94 $1.24

$0.00

$0.50

$1.00

$1.50

$2.00

$2.50

Tota

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Cost Comparison.2 defects/sq.cm DD

Key Takeaways• WLP has largest slope due to increasing yield fallout• FC high because wafer bumping is required


Trade Off Scenario 2 – Effect of Die Size on Package Cost

Key Takeaways• WB relatively flat since package size and number of WBs drives cost• FC very dependent due to wafer bumping costs• FOWLP decreases due to less mold (larger die displaces more mold).

Also assumes only 1 RDL required.


Summary

Wire bond technology is almost always lowest cost

WLP and Embedded die are smallest package but limited to small die

Package Technology Sensitivity• Wire Bond Not particularly sensitive to die or package size

• FOWLP Sensitive to package size but not die size

• Flip Chip Sensitive to both die size (wafer bumping) and package size

(expensive substrate)


BACKUP



3.5mmx3.5mm Package- WLP

4mmx4mm Package -FOWLP, FC

5mmx5mm Package -WB

100 IO



7mmx7mm Package -WB

225 IO



9mmx9mm Package -WB

400 IO



11mmx11mm Package -WB

625 IO




900 IO




1225 IO

WLP $0.10 $0.25 $0.55

FOWLP $0.13 $0.25 $0.44 $0.69 $1.02 $1.44

FC PBGA $0.22 $0.41 $0.70 $1.10 $1.57 $2.25

WB PBGA $0.17 $0.29 $0.44 $0.65 $0.96 $1.27

$0.00

$0.50

$1.00

$1.50

$2.00

$2.50

Tota

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st






5mmx5mm Package -WB

100 IO



7mmx7mm Package -WB

225 IO



9mmx9mm Package -WB

400 IO




625 IO




900 IO




1225 IO

WLP $0.09 $0.21 $0.41

FOWLP $0.12 $0.25 $0.44 0.6902 1.0162 1.4316

FC PBGA $0.21 $0.40 $0.67 $1.03 $1.41 $1.95

WB PBGA $0.17 $0.29 $0.44 $0.64 $0.93 $1.21

$0.00

$0.50

$1.00

$1.50

$2.00

$2.50

Tota

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3.5mmx3.5mm Package -WLP


5mmx5mm Package - WB100 IO










625 IO




900 IO




1225 IO

WLP $0.09 $0.22 $0.42

FOWLP $0.12 $0.25 $0.44 $0.69 $1.02 $1.43

FC PBGA $0.22 $0.40 $0.67 $1.03 $1.43 $1.98

WB PBGA $0.17 $0.29 $0.44 $0.64 $0.93 $1.22

$0.00

$0.50

$1.00

$1.50

$2.00

$2.50

Tota

l Pac

kage

Co

st


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