freescales redistributed chip packaging (rcp) ready for

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-ENT-F0812

Freescales Redistributed Chip Packaging (RCP) Ready for Production

June, 2010

Navjot ChhabraRCP Operations Manager

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 2

Introduction

As Dan Hutcheson, CEO of VLSI Research Inc. recently wrote, “Not far away in Tempe, at Freescale’s Packaging Systems Laboratory, an even more revolutionary packaging technology has been developed. Freescale calls it RCP for Redistributed Chip Package. I think they should rename it to Revolutionary Chip Package because what I’ve seen has led me to believe it will upend the entire way electronics are made in the future.”


► Understand and apply the RCP package technology toward the following attributes:

• Package size• Package performance• Multi-die in package solutions• Integrated stacked packages• 3D Integrated packaging• System in package• Convergence of 3D IC and RCP technology

Objective


► Redistributed Chip Packaging (RCP) overview

► RCP roadmap

► Reliability and technology certification

► Development activities underway

► Providing solutions to customers

► Summary

Agenda


13x13mmMBGA

9x9mmRCP

280-I/O• On average - 30% area reduction• Eliminates wirebonds & substrate• Maintain same ball pitch or smaller• 30% thinner than standard BGA

Three Key Benefits of RCP

►Miniaturization

►Integration

►Elimination

• Multiple die - any device technology• Die PLUS peripherals in package• PoP any packaging technology• SMT components on top• Replace motherboard - PCB

45x90mm

440 peripheral components10 layer PCB

30x30mm

86 Embedded peripheral components36 SMT peripheral components122 total peripheral componentsDoes not include PA or power FETS3-4 layer PCB required for HIF

3G-UMTSRadio

~75% reduction in area~70% peripheral components eliminated!

(animated slide)


RCP Industry Thrust

►System in package – Addresses a potentially large need in the market and is being recognized as the next industry thrust• Heterogeneous integration

• System miniaturization

• System performance

• System cost

• High speed in package computing

• System flexibility (Chip sourcing, integration)

• Block testability

• Path to integrating with 3D IC


QFP

Freescale Packaging Technology Landscape

RCP3D Packaging

QFN

Flip Chip BGA

Wire bond BGAs

RF Module-HDI

PQFNMPC8370QAC0703

Com

plex

ity

Integration

TEPBGA II

TBGA

RCP SiP

Stacked DieTSV

PoPRCP

Single Die


Convergence of 3D IC with RCP Integrated Systems

Substrate Based Module

WL-CSP

Fan out 1LM small pkg. (≤ 8x8)

RCP Multi-die/Modules

3D IC TSV. Integrated with

RCP

3D ICTSV.Differentiated

die

3D IC face-to-face

PoP

Stacked die

3D IC TSV. Stacked memory

RCP (1LM – 6 LM, 3x3 to 40x40mm pkg.)

RCP Stacked multi-die modules (2-5 layers).

RCP Integrated Systems (Sensors,

MEMS, Analog, Digital, Image,

Memory, RF, optical)

Highly integrated,

performance app’s. (3D +

RCP Systems)

RCP Die to Die Integrated Package

-Courtesy of 3D Plus

*

*

*


Freescale’s Redistributed Chip Package►Cost competitive, high productivity,

large area batch processEliminates package substrateEliminates gold wire bonds / C4 bumps

►High performance packageReduced electrical parasiticsHigher frequency response

►Ultra Low-k Compatible (<90 nm MLM)Compliant with advance Si technology

►Pb-free, Halogen free, ROHS compliant

►Single chip, multiple chip and embedded component capability

►3D IC Enabling with System Integration roadmap

►Certified to JEDEC/FSL Commercial and Industrial Level Reliability

300 mm round panel9 x 9 mm packages

258 IO, 0.5 mm pitch716 packages/panel

2 layer build-up


►Process steps• Die placed face down on tape

mounted carrier• Non-compression encapsulant

applied over die• Low temperature cure of

encapsulant and de-tape• Panel buildup with dielectric and Cu

redistribution• Panel bumped after final dielectric

layer applied

Pre-tested dieMold frame

Carrier

Die place onto carrier tape face down prior to encapsulation.

Panel encapsulation

CarrierTape

Mold frame removed, panel separated from carrier, ready to de-tape

Solder bumpCu interconnect

Encapsulant Die

Cu via

Panel cross-section after build up process and bump applied Animated Build-up Process

RCP Process







layer applied


Carrier


Panel encapsulation

CarrierTape



Encapsulant Die

Cu via


RCP Process







layer applied


Carrier


Panel encapsulation

CarrierTape



Encapsulant Die

Cu via

Panel cross-section after build up process and bump applied

Animated Build-up Process

RCP Process







layer applied


Carrier


Panel encapsulation

CarrierTape



Encapsulant Die

Cu via


RCP Process

Rotate 180 Degrees







layer applied


Carrier


Panel encapsulation

CarrierTape



Encapsulant Die

Cu via


RCP Process


Metal 1 layer

RCP Build-Up Process

Metal 2 layer

BGA


3030

►Multiple redistribution layers• Allows for higher routing complexities, greater I/O

►Package Shrink• Improved via/line/spacing over HDI substrate

►Performance• Low contact resistance via structure (Rvia<25mOhm)

►Die shrink• Design for RCP

►Decrease in iterative design cycle• RCP build up pizza mask

►Integration• Multi-Die SiP • 3D Double sided build up• Stacked• Integrated passives

Attributes of the RCP Technology

RCP-LTE29x9mm-I.275BB

Single die versionI/O = 280

LTE213x13mm

Pad Compatible with BGA version

2ML

3ML

4ML

1ML


RCP and HDI Design Rule Comparison

*Current released rules (12MPK10001G-ENG01) 70um min. Expect to revise min via size in a next release pending additional reliability data received, from 70um to 65um (after built: 65um top with 60um bottom). For actual “built” bias dimension, see RCP standard notes).

**Widen line width to as much as possible for low line resistance nets.

Label FeatureRCPStd/Min

FC-HDI Substrate Std/Prem

A Via hole diameter 75um/65um* 200um/80um

B Via pad diameter 100um/95um 350um/150um

C Line width* 25um/25um** 50um/45um

D Line to line space 25um/25um 50um/45um

E Line to via pad space 25um/25um 50um/45um

FVia pad to via pad space 25um/25um 50um/45um

GVia pad to package edge space -/300um 250um/150um

HLine to package edge space -/300um 250um/150um


Die Design for RCP

•Design for RCP allows full array die I/O•Die size can be reduced, fewer power and ground connections

Potential Die Pad Configurations

Die Pad Design Rules

Potential for Die Shrink


RCP Thermal Improvements

Thermal Performance

Package Type

Junction-to-air Thermal Resistance, Rja (°C/W)

Natural Convection

Forced Convection at 1 m/s

(200 ft/min)

RCP, 4 layers, Die Size: 8.5 x 9.9 mm, no lid on die backside 21.4 14.5

FC-PBGA, 6-layer HDIDie Size: 7 x 9 mm, no lid on die backside 24.2 20.4

FC-CBGA, 6 layersDie Size: 6.8 x 7.9 mm, no lid on die backside 14.0 11.0

RCP with 0.5 mm thick 25x25 mm Cu lid on die/encapsulant backside 15.8 10.2

RCP with 1.0 mm thick 25x25 mm Cu lid on die/encapsulant backside 15.5 10.1

RCP with 1.0 mm thick 25x25 mm Cu lid on die/encapsulant backside, along with a plate-fin

heatsink5.6 2.33

360 I/O, 25x25 mm, 1.27 mm pitch on a 4-layer PCB

•Exposed Si Backside•Attach of heat spreader•Improved thermal performance

RCP With Exposed Die and Attached Heat Spreader


RF Test Vehicle

PA Test Vehicle

TV1 TV2 TV3

3G Baseband

2G Baseband

XTR

PowerQuicc-3

Power Management i.275 RiP

i.300 RiP

PTV-C65

NetworkProcessor

19

RCP Test Vehicles & Assembled Products


Certification Vehicles9mm x 9mm 0.5mm P 12mm x 12mm 0.4mm P

6mm x 6mm 0.5mm P

12mm x 12mm 0.4mm PVertical probe125um pad pitch


RCP Reliability – M2 Technology Certification 300mmTest Item JEDEC/FSL

CommercialJEDEC/FSL Industrial

Customer Requirement

Extended Stress

Pre-con: Customer-F* NA NA Pass Pre-con: Customer-B** NA NA Pass Pre-con: MSL3/260ºC Pass Pass Pass Temp Cycle (-55 to 125ºC) w/Customer-F* Pre-con

NA NA Pass 100cyc

Temp Cycle (-55 to 125ºC) w/Customer-B** Pre-con

NA NA Pass 100cyc

Temp Cycle (-55 to 125ºC) w/MSL3/260ºC Pre-con

Pass 400cyc

Pass 700cyc

NA Pass 1000cyc

HTOL 125ºC Pass 504hrs

Pass 1008hrs

Pass 1008hrs

HTB 150ºC Pass 504hrs

Pass 1008hrs

Pass 1008hrs

THB 85ºC/85% w/Customer-F* Pre-con

NA NA Pass 1008hrs

THB 85ºC/85% w/Customer-B** Pre-con

NA NA Pass 1008hrs

THB 85ºC/85% w/MSL3/260ºC Pre-con

Pass 504hrs

Pass 1008hrs

NA

PCT 121ºC/100%RH 29.7psia w/Customer-F* Pre-con

NA NA Pass 96hrs

PCT 121ºC/100%RH 29.7psia w/Customer-B** Pre-con

NA NA Pass 96hrs

Board Level SJR Temp Cycle (-55 to 125ºC) w/Customer-F* Pre-con

NA NA Pass 480cyc

JEDEC Drop Test 30 Drops, 1500G

Pass

Pass NA

* F Precon consists of 3 cycles of moisture load (30ºC/70%RH for 96hrs) and reflow at 260ºC** B Precon consists of 2 cycles of moisture load (30ºC/70%RH for 96hrs) and reflow at 260ºC

M2 Tech Cert Achieved using

Spirytus-S(6x6mm, 105 I/O, 2ML 0.5mm pitch)

JEDEC and customer specific reliability requirements met


RCP Reliability – LTE2 300mm

RCP – LTE2 Demonstrated Reliability(9x9mm, 2ML, 258 I/O, 0.5mm pitch)


A Few Applications Targeted for RCP

Package 2

Package 1


39

U1

U2

Multiple Redistribution LayersFan-Out Packaging

Multi-Die, Embedded Passives, Integrated Structures

2ML

4ML

1ML

M1M2M3M4

Inductors in Build-up

Module with two die and 8 embedded passives

Inductor Coils with Shielding Structure for Isolation

Robust RCP 2D Dimensional Packages –Building a Foundation for 3D


PCB

Die A

Die/Package B

Stacked Fan-Out with side metal interconnect

Stacked Chip-to-Chip

Multiple Laminated Package Layers

RCP 3D Building Blocks – Multi Layer Fan-Out Packages

-Courtesy of 3D Plus RCP Module with Sensor

RCP multi-die layer

10 die, multi-layer package built for Medtronic (Pacemaker application)


Die 2

Die 1

Package A

Package B

Package C

Package D

Embedded in Base PackageAssembled on Top

Package B

Die 1 Die 2

Package A

Package A

BasePackage

Through Package Vias

2D Fan-outSMD

Stacked TSV

Double-Sided Build up

Back-to-Back Die

Single dieE-Plane

Through ViasBlind Via

Common Power/Ground

RCP 3D Building Blocks –Through Package Via-Double Sided Buildup


New RCP Potential

G-Cell

Back-to-Back Die

Single die E-Plane

Wirebond to RCP

►Allows system integration of mixed technologies:

• MEMS• WB Die

►Wirebond on Cu RCP pad possible over:

• Die Region• EGP• Encapsulation


Footed HS

Underfill

RCP on Interposer Requiring ≥ 0.8mm BGA Pitch

► Devised as low cost alternative to low-mid range FC packages► Combines smaller RCP packaged device stacked on low cost substrate to

accommodate 1mm and larger pitch► Key Attributes of Concept

• Allows for smaller RCP package size• Low cost Interposer substrate provided by vendor

RCPInterposer

Interposer routing out to 1.0mm (29mm x 29mm)

8156 die mapped into a 0.4mm RCP Package (17mm x17mm)


Summary: Borrow Architecture from Nature – Adapt it for RCP

To main computer

BOX

BOXInGaAs

BOX

Metal1Metal2

Metal3

Visible IR

Imager layer

Cones (day/color)Rods (night vision)

Ganglion cells(multi-pixel processing)

Bipolar cellsAmacrine cellsHorizontal cells

Light inputTo optic nerve

(output)

Smart processing

Electrical output

Parallel Vertical Imager/Processor Stack

Retina

►RCP provides a diverse set of solutions for heterogeneous integration.

►Interest in mounting within the industry to utilize this capability for integrated, compact systems


Technology Development

Proposed Model

JDA Activity with Nepes

Multi-Die3D Integrated Packages

High I/O, High performance packagesIntegrated Sensors

Prototyping Freescale NPI’s

Freescale initiated external customer support

Prototyping Nepes initiated non-Freescale product support

Internal Freescale Non JDA related opportunities(ex Sensors)

Nepes Manufacturing

Site

External Freescale System level or package level opportunity

(i.e. Medical, Robotics, Imaging, Smart Card, etc.)

External Freescale Test hardware development

Develop Freescale integrated system level package solution using Freescale resources (design, modeling,

package development, manufacturing)

Use established opportunities to integrate Freescale IP/ Chips as well as build a comprehensive solution

Nepes Manufacturing

Site

Partner Manufacturing

Site

Freescale Manufacturing

Site

Tempe RCP Development

and Prototyping

Lab

Freescale Development Activities Outside of Nepes framework


Foundry Technology Offerings Across Markets

CMOS Technology (Low Power, RF CMOS, SOI, NVM and Cores)180nm, 130nm and 90nm

NetworkingInfrastructure

WirelessHandsetsConsumerIndustrialAutomotive

Silicon Germanium RF BiCMOS0.35um and 0.18um

MEMs, Backend and Post Process Modules (Cu Ind, Power Cu and Bump)150mm and 200mm Wafer Services

SmartMOS (BCD Smart Power Technology0.35um, 0.25um and 0.13um (voltage tiers up to 105v)

RCP – Advanced Redistributed 3-D Packaging TechnologyMulti Die, Multi Technology Systems in a Package

freescales redistributed chip packaging (rcp) ready for

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