chapter 4 design of logical structures using qca...

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CHAPTER 4

DESIGN OF LOGICAL STRUCTURES USING QCA GATES

4.1 INTRODUCTION

QCA is a novel emerging technology in which logic states are not

stored as voltage levels, but rather the position of individual electrons.

Conceptually, QCA represents binary information by utilizing a bistable

charge configuration rather than a current switch. Unlike conventional logic

circuits in which information is transferred by electrical current, QCA

operates by the Coulombic interaction that connects the state of one cell to the

state of its neighbours. Hence the information transfer (interconnection) is the

same as information transformation (logic manipulation) in the QCA

technology.

The existing literature on QCA design mostly uses a gate-based

methodology. Walus et al (2003) and Zhang et al (2004) have worked on this

methodology. In a gate-based design, much like a CMOS design process, first

the desired logic function of the circuit is determined and then a logic

synthesis process is performed to obtain a netlist.

A logic gate is an electronic circuit that performs a logic function

on number of input binary signals. The logic gate is the building block from

which many different kinds of logic circuit can be constructed. The basic

logic gates are OR, AND, NOT, NAND and NOR. The NAND and NOR

gates are called as the universal gates. The exclusive OR (XOR) is another

logic gate which can be constructed using the basic gates.

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The logic gates have two or more inputs and only one output except

for the NOT gate, which has only one input. The output signal appears only

for certain combinations of the input signals. The manipulation of binary

information is done by the gates. Each gate has a distinct logic symbol and its

operation can be described by means of an algebraic function. The

relationship between input and output variables of each gate can be

represented in a tabular form called a truth table.

In this thesis different types of logical structures are designed using

three different QCA gates such as Majority gate, Nand-Nor-Inverter and And-

Or-Inverter. Then the designed structures are implemented by QCA cells

using cell minimization techniques. The designed structures are simulated by

QCADesigner. The simulation based performance analysis of these structures

are tabulated and compared with existing majority gate method.

4.2 CELL MINIMIZATION TECHNIQUES

The area and complexity are important key issues in circuit designs.

In QCA technology, the area and complexity can be minimized by reducing

the number of cells. Hence the following cell minimization techniques are

proposed in this thesis.

1) Two cell inverter

The different types of inverters are used in QCA design. Basically

the inverter which consists of 13 cells is used to design the circuits. But in this

thesis two cell inverter is used for circuit implementations.

QCA computation proceeds by orientation of cells based on

polarization of neighbouring cells. QCA inverter can be implemented by

positioning and rotation of cells. In our implementation, positioning of QCA

cell is used to invert the output from input logic level. In the two cell inverter,

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first cell is placed normally and the second cell is placed adjacent to the first

cell, but 10nm vertically below from the cell as shown in Figure 4.1. Here the

electrostatic interaction is inverted because the quantum dots of different

polarizations are misaligned between the cells.

Figure 4.1 QCA two cell inverter

2) Proper Alignment of cells

This is the second technique used to minimize the number of cells

in the QCA circuits. The following rules are used to minimize the number of

cells.

Rules:

1. The minimum distance between the adjacent rows of cells is

the width of two cells.

2. The minimum distance between the adjacent columns of cells

is the width of two cells.

3. The number of cells in the rows need not be equal.

4. The number of cells in the columns need not be equal.

5. At least one extra cell is used to carry input or catch the

output.

6. The designed circuits are implemented with suitable

arrangement of cells without overlapping of neighbouring

cells.

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For example consider the 4 input AND gate implemented with

QCA cells is shown in Figure 4.2 and Figure 4.3. Here two different

arrangements of 4 input AND gates are given. In the arrangement of 4 input

(A, B, C, and D) AND gate in Figure 4.2, the number of cells required is 28

with an area of 34540 nm2. But the total number of cells required for Figure

4.3 is only 23, with an area of 21200 nm2.

In this way the total number of cells

has been reduced by proper arrangement of cells.

Figure 4.2 Layout (1) of 4 Input AND gate

Figure 4.3 Layout (2) of 4 Input AND gate

The arithmetic and logical structures are implemented by QCA

cells with the help of cell minimization techniques. The resulting circuits

having less number of cells. Hence the proposed method is used to address the

key two issues.

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4.3 DESIGN OF LOGICAL STRUCTURES USING MAJORITY

GATE

Various types of QCA devices can be constructed using different

physical cell arrangements. One of the basic logic gates in QCA is the

majority voter (MV) and the inverter (INV) is the other basic gate in QCA.

The other logical structures are designed using these two gates. Logic

operations are performed by means of the interactions between adjacent cells.

4.3.1 Design and QCA Implementation

In this implementation a careful consideration is taken into account,

to increase the device stability. This implementation also reduces the number

of cells. It has been reduced by suitable arrangement of cells without

overlapping of neighbouring cells and by using 2 cells inverter .Hence this

implementation further reduces the area and complexity.

4.3.1.1 AND and OR gates

The cells can then be aligned in rows and columns to form the logic

structures. Consider the majority gate which is designed to perform the logic

function A+B. The electrons in each cell repel each other, but the repulsion

propagates to adjacent cells. Therefore, inputs A, B, and C are affecting the

configuration of the center and out cells. In this case, the majority of the

inputs are set to ‘1’, so the center and Out cells are forced into the ‘1’

position, which is the proper result of A+B. If A were set to ‘0’, the majority

of inputs would force Out to ‘0’. Similarly, if C were set to ‘0’ (making the

cross structure an AND gate), Out would be forced to ‘0’. The AND and OR

gates are realized by fixing the polarization to one of the inputs of the

majority gate to either P = −1 (logic “0”) or P = 1(logic “1”).

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Figure 4.4 AND gate schematic Figure 4.5 Layout of AND gate

Figure 4.6 OR gate schematic Figure 4.7 Layout of OR gate

The function of QCA AND and OR gates as shown in Figure 4.5

and Figure 4.7 are verified according to the Table 4.1 and Table 4.2.

Table 4.1 Truth table of AND gate

Inputs Output

A B A.B

0

0

1

1

0

1

0

1

0

0

0

1

Table 4.2 Truth table of OR gate

Inputs Output

A B A+B

0

0

1

1

0

1

0

1

0

1

1

1

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The layouts of 4 input AND and OR gates are given below. These

implementations required 23 cells, with an area of 21200 nm2.

Figure 4.8 Layout of 4 Input AND

gate

Figure 4.9 Layout of 4 Input OR

gate

4.3.1.2 NAND and NOR gates

QCA computation proceeds by orientation of cells based on

polarization of neighbouring cells. QCA inverter can be implemented by

positioning and rotation of cells. In our implementation, positioning of QCA

cell is used to invert the output from input logic level. In the two cell inverter,

the first cell is placed normally and the second cell is placed adjacent to the

first cell, but 10nm vertically below from the cell. Here the electrostatic

interaction is inverted because the quantum dots of different polarizations are

misaligned between the cells.

The NAND function is the complement of AND functions. It is

realized by connecting AND gate (MG) followed by an inverter. Similarly the

NOR gate is realized by connecting OR gate (MG) followed by an inverter. If

the last two cells are arranged, as shown in the Figure 4.11 then it acts as an

inverter. By using this 2 cell inverter, the area required and complexity can be

minimized.

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Figure 4.10 NAND gate schematic Figure 4.11 Layout of NAND gate

Figure 4.12 NAND gate schematic Figure 4.13 Layout of NOR gate

The function of QCA NAND and NOR gates as shown in Figure 4.11


Table 4.3 Truth table of NAND gate

Inputs Output

A B (A.B)'

0

0

1

1

0

1

0

1

1

1

1

0

Table 4.4 Truth table of NOR gate

Inputs Output

A B (A+B)'

0

0

1

1

0

1

0

1

1

0

0

0

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4.3.1.3 XOR and Ex-NOR gates

The XOR is a logical operation on two operands that results in a

logical value of true if and only if one of the operands, but not both, has a

value of true. This forms a fundamental logic gate in many operations to

follow. The Ex-NOR function is the complement of XOR function. It is

realized by connecting XOR gate followed by an inverter. The logic function

for XOR is,

A B = A'B+B'A (4.1)

The realization is done making use of majority gates (MGs) as

A B = M (M (A', B, 0) M (A, B', 0), 1) (4.2)

The logic function for EX-NOR is,

(A B) ' = AB+A'B' (4.3)

The majority gate expression for above equation as,

(A B)' = M (M (A, B, 0), M (A', B', 0), 1) (4.4)

The logical structure XOR is designed with 3 majority gates and 2

inverters as shown in Figure 4.14. The corresponding QCA implementation is

shown in Figure 4.15. In this implementation the total number of cells

required is 64, with an area of 64000 nm2. This is much lesser than the

previous QCA implementation. The previous implementation has 87 cells

with an area of 75400 nm2. Similarly the Ex-NOR structure is designed and

implemented using QCA cells as shown in Figure 4.16 and Figure .4.17.

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Figure 4.14 XOR schematic

Figure 4.15 Layout of XOR gate

Figure 4.16 Ex-NOR schematic

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Figure 4.17 Layout of XNOR gate

The function of QCA AND and OR gates as shown in Figure 4.5


Table 4.5 Truth table of XOR gate

Inputs Output

A B A B

0

0

1

1

0

1

0

1

0

0

0

1

Table 4.6 Truth table of XNOR gate

Inputs Output

A B (A B)'

0

0

1

1

0

1

0

1

0

1

1

1

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The performance analysis of various proposed logical structures

using majority gates are shown in Table 4.7. The performance analyses of

those circuits are compared according to the complexity, area, and number of

clock cycles and the proposed designs are compared with existing majority

gate method.

Table 4.7 Performance Analysis of Logical Structures using Majority gate

Logical

structures

Previous structures New structures Number of

Clock cyclesComplexity Area Complexity Area

Inverter 7 cells 80nm x 58nm 2 cells 44nm x 30nm Clock zone0

NAND 13 cells 139nm x 58nm 7 cells 63nm x 103nm Clock zone0

NOR 13 cells 139nm x 58nm 7cells 63nm x 103nm Clock zone0

XOR 87 cells 290nm x 260nm 64 cells 300nmx220nm 1

XNOR 93 cells 290nm x 350nm 65 cells 327nmx220nm 1

4.4 DESIGN OF LOGICAL STRUCTURES USING NNI

Logical gates are the basic elements that make up a digital system.

The gate is a circuit that is able to operate on a number of binary inputs in

order to perform a particular logical function. Here different logical structures

like AND, OR, NOT, NAND, NOR, EX-OR and EX-NOR are designed using

NNI. The NNI gate consists of two inverted inputs. Hence the design rules are

proposed in this section for easy to realize or design all functions using NNI

gates.

4.4.1 Design Rules for NNI

Rule1: If the first two inputs A and B are set to zero then the NNI gate acts

as an inverter.

Rule2: Also if the last two inputs B and C are set to zero then the NNI gate

acts as an inverter.

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Rule3: If A=C=0 and B=1or 0 then output of NNI gate is always 1.

Rule4: If B=1 and there is no change in other two inputs then NNI gate act

as a NAND gate.

Rule5: If B=0 and there is no change in other two inputs then NNI gate act

as a NOR gate.

The above said inverter rules are defined by the following table.

Table 4.8 NNI rules table for implementation of inverter

Rules Input Output

A B C F

R1 A 0 0 A'

R2 0 0 C C'

R3 0 B 0 1

Rules R1 and R2 indicates how inverter is obtained and R3

indicates irrespective of B, if A and C are set to zero, output is always 1.The

operations in Table 4.8 is achieved by only one NNI gate. The table also

defines the function of NNI gate, when any of two inputs are set to zero.

Hence the gate is now said to be a single input NNI gate.

4.4.2 Inverter Design

The majority gate suffers from the disadvantage that it cannot offer

the inverting function. This motivated to build a QCA gate NNI with

embedded AND, OR and INV functions. The design of inverter using' NNI is

defined below.

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The NNI gate is defined by,

NNI (A, B, C) = M (A', B, C') = A'B+BC'+C'A' (4.1)

If we set B=C=0 to above equation then,

NNI (A, 0, 0) = A'. (4.2)

The corresponding NNI gate implementation is show in Figure 4.18.

Figure 4.18 Inverter using NNI

4.4.3 AND and OR Design

In AND gate design, If we set B=1 then Equation (4.1) becomes,

NNI1 (A, 1, C) = A'+C'+C'A' (4.3)

= A'+C'(1+A')

= A'+C'

= (AC)' (4.4)

Then the output of NNI1 is given as one of input to NNI2.Next we

set the other two inputs of NN2 to zero, which acts as an inverter. Hence it

gives the function of AND gate. The NNI - AND gate implementation is

shown in Figure 4.19.

Therefore, NNI2 (NNI1, 0, 0) = NNI2 ((AC) ', 0, 0) = AC. (4.5)

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Figure 4.19 AND gate using NNI

In the case of OR gate design, If we set B=0 then Equation (4.1) becomes,

NNI1 (A, 0, C) = C'A'= (A+C)'. (4.6)

Then the output of NNI1 is given as one of input to NNI2.Next we set

the other two inputs of NN2 to zero, which acts as an inverter. Hence it gives

the function of OR gate. The NNI - OR gate implementation is shown

in Figure 4.20.

Therefore, NNI2 (NNI1, 0, 0) = NNI2 ((A+C) ', 0, 0) = A+C. (4.7)

Figure 4.20 OR gate using NNI

4.4.4 NAND and NOR Design


realized by connecting AND gate followed by an inverter. Similarly the NOR

gate is realized by connecting OR gate followed by an inverter. But in NNI

gate there is no need of separate inverter because it is an universal gate.

Hence a single gate is used to implement NAND and NOR gates. By using

the NNI, the area required and complexity can be minimized.

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The Equation (4.3) and Equation (4.6) give the NAND and NOR

operations respectively. The NAND gate is realized by fixing the NNI gate

input B=1 and B=0 for NOR gate. The NNI - NAND and NOR gate

implementations are as shown in Figure 4.21and Figure 4.22.

Figure 4.21 NAND gate using NNI Figure 4.22 NOR gate using NNI

4.4.5 XOR and XNOR Design


logical value of true if and only if one of the operands has a value of true.

This forms a fundamental logic gate in many operations. The Ex-NOR

function is the complement of XOR function. It is realized by connecting

XOR gate followed by an inverter. The logic function for XOR is,

A B = A'B+B'A (4.8)

XOR algorithm using NNI

The NNI gate expression for Equation (4.8) is obtained by the

following procedure,

1. If we set C=1 then NNI1 (A, B, 1) = A'B

2. If we set C=1and interchange variables A and B then NNI2

(B, A, 1) = B'A

3. The outputs of NNI1 and NNI2 are given as input to NNI3

and third input of NNI3 is set to zero. Then NNI3=NNI (NNI1,

NNI2, 0) = (A'B+B'A) '.

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4. The outputs of NNI3 is given as input to NNI4 and second and

third inputs of

NNI3 is set to zero. Then NNI4=NNI (NNI3, 0, 0) = A'B+B'A.

Therefore the complete NNI gate expression for A B is,

A B =NNI4((NNI3(NNI1(A,B,1),NNI2(B,A,1),0),0,0) (4.9)


(A B)' = AB+A'B' (4.10)

The NNI gate realization of EX-NOR is similar to XOR gate. The third step is

used to give the EX-NOR output. Therefore the complete NNI gate

expression for (A B)' is given by,

(A B)' = (NNI3 (NNI1 (A, B, 1), NNI2 (B, A, 1), 0) (4.11)

The logical structure XOR is designed with 4 NNI gates as shown

in Figure 4.23.

Figure 4.23 XOR gate using NNI

4.4.6 QCA Implementation

In this implementation a careful consideration is taken into account,

to increase the device stability. This implementation also reduces the number

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of cells. It has been reduced by suitable arrangement of cells without

overlapping of neighbouring cells and by using NNI gate. Hence the proposed

implementation further reduces the area and complexity.

4.4.6.1 NAND and NOR implementation

The NAND and NOR gates are designed by only one NNI gate.

The NAND gate is realized by fixing the polarization to one of the inputs (B)

of the NNI gate to P = 1 (logic “1”) and P = -1 (logic “0”) for NOR gate and

the corresponding QCA implementation is shown in Figure 4.24 and Figure

4.25. In this implementation the total number of cells required is 5, with an

area of 4800 nm2. The previous majority gate implementation has 9 cells with

an area of 6000nm2.Hence the area required and complexity can be minimized

in NNI gate design.

Figure 4.24 Layout of NAND gate. Figure 4.25 Layout of NOR gate

4.4.6.2 AND and OR implementation

The cells can then be aligned in rows and columns to form logic

structures. Consider the NNI gate which is designed to perform the logic

function AB and A+B. The electrons in each cell repel each other, but the

repulsion propagates to adjacent cells. Therefore, inputs A, B, and C are

affecting the configuration of the cells.

The AND and OR gates are not obtained directly from the NNI

gate. The AND gate is realized by fixing the polarization to one of the inputs

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(B) of the NNI gate to P = 1(logic “1”) then the output of first gate is given as

input to second gate. The other two inputs of second gate is set to zero. The

output of second gate gives the AND output.

Similarly the OR gate is realized by fixing the polarization to one

of the inputs (B) of the NNI gate to P = -1(logic “0”) then the output of first

gate is given as input to second gate. The other two inputs of second gate is

set to zero. The output of second gate gives the OR output. The QCA cell

implementation for AND and OR gates are shown in Figure 4.26 and

Figure 4.27. The total number of cells required for the implementation is 11,

with an area of 14000 nm2.

Figure 4.26 Layout of AND gate Figure 4.27 Layout of OR gate

4.4.6.3 XOR and XNOR implementation

The logical structure XOR is designed with 4 NNI gates as shown

in Figure 4.28 and separate inverters are not used here. In this implementation

the total number of cells required is 68 which is much lesser than the previous

QCA implementation and with an area of 91000 nm2. Similarly the Ex-NOR

structure is designed with 3 NNI gates and the corresponding QCA

implementation as shown in Figure 4.29 requires 65 cells ,with an area of

72800 nm2.

The previous majority gate implementation has 93 cells with an

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area of 105000nm2 .

Hence the area required and complexity of the circuit can

be minimized in NNI gate design.

Figure 4.28 Layout of XOR gate Figure 4.29Layout of XNOR gate

The simulation based analyses of proposed logical structures using

NNI gates are given in Table 4.9 and is also compared with existing majority

gate logical structures.

Table 4.9 Performance Analysis of Logical Structures using NNI

Logical

structures

Previous structures

using MG

Proposed structures using

NNI Clocking

Complexity Area Complexity Area

Inverter 7 cells 80nmx58nm 4 cells 80nm x 60nm Simple

AND 5 cells 80nm x 60nm 11 cells 140nm x 100nm Simple

OR 5 cells 80nm x 60nm 11 cells 140nmx 100nm Simple

NAND 13 cells 139nm x 58nm 5 cells 80nm x 60nm Simple

NOR 13 cells 139nmx58nm 5cells 80nm x 60nm Simple

XOR 87 cells 300nmx260nm 68 cells 350nm x 260nm 1

Ex-NOR 93 cells 290nmx350nm 63 cells 280nm x 260nm 1

4.4.7 Characteristics of NNI

The logic function of NNI gate is realized by the Equation (3.6).

Based on the equation the logical characteristics of NNI are defined. The

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standard logical AND and OR operation can be obtained by two NNI gates, is

defined by the following Table 4.10.

Table 4.10 Characteristics table (1)

Input Output 1 Applying

rulesFinal output 2

A 1 C (AC)' R1 AC

A 0 C (A+C)' R1 A+C

The first NNI gate output is obtained as below

1) If we set B=1, then output 1 is OR of two inverted inputs or

inversion of AND of two inputs.

2) If we set B=0, then output 1 is AND of two separate inverted

inputs or inversion of OR of two inputs.

Then applying inverter rule R1, the AND and OR operation can be

obtained at the output of second NNI gate.

With any input A and BC =00 or 11 then the output of AOI gate is

A’. Similarly, if B=01 or 10 then the output of AOI gate is equivalent to SR

latch. The characteristic is defined by the following table the same is

applicable for input C also.


Input Output

A B C F

A

0 0 A'

0 1 0

1 0 1

1 1 A'

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The rules R1 and R2 have already defined how inverter function is

obtained from NNI gate. From the above Table 4.11 know that there is

another possibility of getting inverter function using NNI. Here the selection

of inputs A, B and C are important. Based on these inputs we have to obtain

different functions from single NNI gate.

With any input B and AC =00 then the output of NNI gate is 1 and

if AC =11 then the output of AOI gate is 0. Similarly, when AC=01 or 10

then the output of NNI gate is B. The characteristic is defined by the

following Table 4.12.


Input Output

A B C F

0

B

0 1

0 1 B

1 0 B

1 1 0

The efficient NNI expression for any given three-variable Boolean function

which is amenable to QCA implementation is obtained by using the above

mentioned rules and characteristics. The simplified NNI expressions for some

functions are given in the Table 4.13.

Table 4.13 NNI gate functions

Input Terms in NNI equation Output

A B C A'B BC' A'C' Y

1 B C 0 BC' 0 BC'

0 B C B BC' C’ B+C'

A B 1 A'B 0 0 A'B

A B 0 A'B B A' A'+B

A 1 C A' C' A'C' (AC)'

A 0 C 0 0 A' (A+C)'

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4.4.8 Standard Functions using NNI

The three variables A, B and C are used to facilitate the conversion

of a sum-of-products expression to minimized NNI logic. Based on that to

obtain the efficient NNI expression for any given three-variable Boolean

function. All Boolean functions which can be constituted within thirteen

numbers of universal Boolean functions (Walus 2004) are realized either by

combination of MV and NNI gates or by NNI gates alone.

In this section the simplified NNI expressions for some standard

functions and the corresponding gate representations are given below.

1. F=B

F=NNI (0, B, 0)

Figure 4.30 F=B

2. F=ABC

F= NNI 2(NNI1 (A, 1, C), 0, B')

Figure 4.31 F=ABC

3. F=A+B+C

F= NNI 2(NNI1 (A, 0, C), 1, B')

Figure 4.32 F=A+B+C

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4. F=AB'C

F= NNI 2(NNI1 (A, 1, C), 1, B)

Figure 4.33 F=AB'C

5. F=AB+BC

F= NNI 2(NNI1 (A, 0, C), 0, B')

Figure 4.34 F=AB+BC

6. F=A'B+BC'

F= NNI4 (NNI3 (NNI 2(NNI1 (A, B, 1), NNI2 (1, B, C), 0), 0, 0)

Figure 4.35 F=A'B+BC'

6. F=AB+BC+CA

F= NNI6 (NNI5 (NNI 2(NNI1 (A, 0, C), 0, B'), NNI4 (NNI3 (A, 1, C),

0, 0), 0), 0,0)

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Figure 4.36 F=AB+BC+CA

4.5 DESIGN OF LOGICAL STRUCTURES USING AOI GATE

All Boolean functions cannot be realized by majority gates alone,

but majority gate with NOT gates is used to complete the design. Therefore,

the designers have to use separate QCA cell arrangement for realization of the

logical NOT. Thus to implement majority gate with NOT functions, a new

gate called And-Or-Inverter (AOI) (Momenzadeh et al 2005) is constructed.

Here, the different logical structures are designed by using AOI gate. The

AOI is a complex QCA gate. Hence, the functional rules for AOI gates are

introduced in this thesis. These rules help in easy implementation of AOI

gates for different functions and logical characteristics of AOI is defined here.

The designed logical structures using the AOI gates are compared with the

conventional CMOS and majority gate based QCA methodology.

4.5.1 Design Rules for AOI

The AOI gate is a 5 input gate. Hence to simplify the design

complexity, the two inputs D and E were set to constant values. Based on the

assumption or constant values the rules are proposed and characteristics are

defined.

The logic function of AOI gate is realized by,

F = DE + (D + E) (A' C' + A'B + BC') (4.12)

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The AOI gate rules are proposed here for the fast and easy

implementation of complex circuits. The rules are defined as follows.

If we set inputs DE =01 or 10 in the equation (4.12) then,

Rule1: If the first two inputs A and B are set to zero then the AOI gate acts

as an inverter.

Rule2: Also if the last two inputs B and C are set to zero then the AOI gate

act as an inverter.

Rule3: If A=C=0 and B=1or 0 then output of AOI gate is always 1.

Rule4: If B=1 and there is no change in other two inputs then AOI gate act

as a NAND gate.

Rule5: If B=0 and there is no change in other two inputs then AOI gate act

as a NOR gate.

The above said inverter rules are defined by the following

Table 4.14.

Table 4.14 AOI rules table for implementation of inverter

Rules Input Output

A B C F

R1 A 0 0 A'

R2 0 0 C C'

R3 0 B 0 1

Rules R1 and R2 indicates how inverter is obtained and R3

indicates irrespective of B, if A and C are set to zero, output is always 1. The

operations in Table 4.14 are achieved by only one AOI gate. The table also

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defines the function of AOI gate, when any of two inputs are set to zero.

Hence the gate is now said to be a single input AOI gate.

Logical gates are the basic elements that built the digital system. The

gate is a circuit that is able to operate on a number of binary inputs in order to

perform a particular logical function. Here different logical structures such as

AND, OR, NOT, NAND, NOR, EX-OR and EX-NOR are designed using

AOI.

4.5.1.1 Inverter Design

The majority gate suffers from the disadvantage that it cannot offer

the inverting function. This motivated to build a QCA gate AOI with

embedded AND, OR and INV functions. The design of inverter function

using AOI is define below.

We know that, F = AOI (A, B, C, D) = DE + (D + E) (A' C' + A'B + BC')

= DE + (D + E) (NNI (A, B, C)) (4.13)

Where NNI (A, B, C) = M (A', B, C') = A'B+BC'+C'A'

If we set DE=01 or 10 in Equation (4.13) then the resulting equation is

F=AOI (0, 1, A, B, C) = NNI (A, B, C) = M (A', B, C') = A'B+BC'+C'A'

(4.14)

If we set any B=C=0 to above equation then,

F = AOI (0, 1, A, 0, 0) = A'.

The corresponding AOI gate implementation is show in Figure 4.36.

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4.5.1.2 AND and OR Design

In AND gate design, If we set B=1 then Equation (4.15) becomes,

F= AOI1 (A, 1, C) = A'+C'+C'A'

= A'+C'(1+A')

= A'+C'

= (AC) ' (4.16)

Then the output of AOI1 is given as one of input to AOI 2. The

other two inputs of AOI2 are set to zero, which acts as an inverter. Hence it

gives the function of AND gate. The AOI - AND gate implementation is

shown in Figure 4.37.

Therefore, AOI2 (AOI1, 0, 0) = AOI2 ((AC) ', 0, 0) = AC. (4.17)

Figure 4.37 Inverter using AOI Figure 4.38 AND gate using AOI

In the case of OR gate design, If we set B=0 then Equation (4.13) becomes,

AOI1 (A, 0, C) = C'A'= (A+C) '. (4.18)

Then the output of AOI1 is given as one of input to AOI2. The other two

inputs of AOI2 are set to zero, which acts as an inverter. Hence it gives the

function of OR gate as shown in Figure 4.38.

Therefore, AOI2 (AOI1, 0, 0) = AOI2 ((A+C) ', 0, 0) = A+C. (4.19)

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Figure 4.39 OR gate using AOI

4.5.1.3 NAND and NOR Design


realized by connecting AND gate followed by an inverter. Similarly the NOR

gate is realized by connecting OR gate followed by an inverter. But in AOI

gate there is no need of separate inverter because it is an universal gate.

Hence a single AOI gate is used to implement NAND and NOR gates.

Therefore the complexity of a circuit can be minimized.

The Equation (4.16) and Equation (4.18) gives the NAND and

NOR operations respectively. The NAND gate is realized by fixing the AOI

gate input B=1 and B=0 for NOR gate. The AOI- NAND and NOR gate

implementations are as shown in Figure 4.39 and Figure 4.40.

Figure 4.40 NAND gate using AOI Figure 4.41 NOR gate using AOI

4.5.1.4 XOR and Ex-NOR Design


logical value of true, if and only if one of the operands has a value of true.

This forms a fundamental logic gate in many operations to follow. The Ex-

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NOR function is the complement of XOR function. It is realized by

connecting XOR gate followed by an inverter. The logic function for XOR is,

A B = A'B+B'A (4.20)

AOI Algorithm

The AOI gate expression for Equation 4.20 is obtained by the

following algorithm,

1. If we set C=1 then, AOI1 (A, B, 1) = A'B

2. If we set C=1and interchange variables A and B then AOI2

(B, A, 1) = B'A

3. The outputs of AOI1 and AOI2 are given as input to AOI3

and third input of AOI3 is set to zero. Then AOI3=AOI

(AOI1, AOII2, 0) = (A'B+B'A)’

4. The output of AOI3 is given as input to AOI4 and a second

and third input of AOI3 is set to zero. Then AOII4=AOI

(AOI3, 0, 0) = A'B+B'A

Therefore the complete NNI gate expression for A B is,

A B =AOII4((AOI3(AOI1(A,B,1),AOI2(B,A,1),0),0,0) (4.21)


(A B)’ = AB+A'B' (4.22)

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The NNI gate realization of EX-NOR is similar to XOR gate. The

third step is used to give the EX-NOR output. Therefore the complete AOI

gate expression for (A B) ' is given by,

(A B) ‘= (AOI3 (AOI1 (A, B, 1), AOI2 (B, A, 1), 0) (4.23)

The logical structure XOR is designed with 4 AOI gates as shown

in Figure 4.42. The XNOR-AOI gate implementation is as shown in

Figure 4.43.

Figure 4.42 XOR gate using AOI

Figure 4.43 XNOR gate using AOI

The design analysis of various logical structures using AOI gates

are shown in Table 4.15. The number of gates required to design the basic

logical structures using CMOS, MG, NNI and AOI gates are given below.

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Table 4.15 Comparison of Logical Structures

Type of

Design

Total Number of Gates Required for the Design of Logical structures

Inverter AND OR NAND NOR XOR Ex-NOR

CMOS

Design

2 4 4 4 4 8 8

Majority

gate (MG)

Design

Separatedevice

1 MG 1 MG 1 MG1 Inverter

1 MG1 Inverter

3 MG2 Inverters

3 MG3 Inverters

NNI Gate

Design

1 NNIgate

2 NNIgates

2 NNIGates

1 NNIGate

1 NNIgate

4 NNIgates

3 NNIgates

AOI Gate

Design

1 AOI

Gate

2 AOI

gates

2 AOI

gates

1 AOI

gate

1 AOI

gate

4 AOI

gates

3 AOI

gates

4.5.2 Characteristics of AOI

The logic function of AOI gate is realized by the Equation (4.12).

Based on the equation we have to define the logical characteristics of AOI.

1. If inputs D and E are equal to zero, the corresponding output

is zero.

2. If inputs DE=11 then the corresponding output is one.

3. If DE=01 or 10 then the corresponding output is M (A’, B,

C'). Therefore, the logical expressions are available only in

these combinations of D and E as shown in Table 4.16.


Input Output

A B C D E F

A B C 0 0 0

A B C 0 1 M(A',B,C') or NNI(A,B,C)

A B C 1 0 M(A',B,C') or NNI(A,B,C)

A B C 1 1 1

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With DE=01 or 10, the output of AOI gate becomes M ( A’, B, C’)

or NNI (A, B, C). Hence, the AOI gate not only offers the inverter function. It

can be also used to build Majority gate as well as NNI gate. Thus, keeping

DE=01 or 10, all following operations are applicable for both NNI and AOI.

The logic function of AOI gate is realized by the (3).Based on the

equation we have to define the logical characteristics of NNI. The standard

logical AND and OR operation can be obtained by two AOI gates, is defined

by the following table.


Input Output 1 Applying rules Final output2

A 1 C (AC)' R1 AC

A 0 C (A+C)' R1 A+C

The first AOI gate output is obtained as below

1. If we set B=1, then output 1 is OR of two inverted inputs or

inversion of AND of two inputs.

2. If we set B=0, then output 1 is AND of two separate inverted

inputs or inversion of OR of two inputs.

Then applying inverter rule R1, the AND and OR operation can be

obtained at the output of second AOI gate.

With any input A and BC =00 or 11 then the output of AOI gate is

A'. Similarly, if B=01 or 10 then the output of AOI gate is equivalent to SR

latch. The characteristic is defined by the following table. The same is

applicable for input C also.

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Input Output

A B C F

A 0 0 A'

0 1 0

1 0 1

1 1 A'

The rules R1 and R2 have already defined how inverter function is

obtained from AOI gate. From the above table we know that there is another

possibility of getting inverter function using AOI. Here the selection of inputs

A, B and C are important. Based on these inputs we have to obtain different

functions from single AOI gate.

With any input B and AC =00 then the output of AOI gate is 1 and

if AC =11 then the output of AOI gate is 0. Similarly, when AC=01 or 10

then the output of AOI gate is B. The characteristic is defined by the

following Table 4.19.


Input Output

A B C F

0

B

0 1

0 1 B

1 0 B

1 1 0

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Table 4.20 AOI gate functions

Input Terms in AOI

equation Output

A B C A'B BC' A'C' Y

1 B C 0 BC' 0 BC'

0 B C B BC' C’ B+C'

A B 1 A'B 0 0 A'B

A B 0 A'B B A' A'+B

A 1 C A' C' A'C' (AC)'

A 0 C 0 0 A' (A+C)'

Based on the above mentioned rules and characteristics of AOI gate

we have to obtain the efficient AOI expression for any given three-variable

Boolean function amenable to QCA implementation. The simplified AOI

expressions for some functions are given in the Table 4.20.

4.5.3 Standard functions using AOI

The AOI gate is a 5-input (A, B, C, D and E) and by setting the

two inputs D and E are equal to 01 or 10, then the three variables A, B and C

are used to facilitate the conversion of a sum-of-products expression to

minimized AOI logic. Based on that to obtain the efficient AOI expression for

any given three-variable Boolean function amenable to QCA implementation.

The simplified AOI expressions for some standard functions and the

corresponding gate representations are given below.

1. F=B

F=AOI (0, B, 0)

Figure 4.44 F=B

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2. F=ABC

F= AOI2 (AOI1 (A, 1, C), 0, B')

Figure 4.45 F=ABC

3. F=A+B+C

F= AOI 2(AOI1 (A, 0, C), 1, B')

Figure 4.46 F=A+B+C

4. F=AB'C

F= NNI 2(NNI1 (A, 1, C), 1, B)

Figure 4.47 F=AB'C

5. F=AB+BC

F= AOI 2(AOI1(A, 0, C), 0, B')

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Figure 4.48 F=AB+BC

6. F=A’B+BC’

F= AOI4 (AOI3 (AOI 2(AOI1 (A, B, 1), AOI2 (1, B, C), 0), 0, 0)

Figure 4.49 F=A'B+BC'

7. F=AB+BC+CA

F= AOI6 (AOI5 (AOI 2(AOI1 (A, 0, C), 0, B'), AOI4 (AOI3 (A, 1, C),

0, 0), 0), 0, 0)

Figure 4.50 F=AB+BC+CA

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4.6 RESULTS AND DISCUSSION

With QCADesigner ver.2.0.3, the functionality of logical gates are

verified. The simulated waveform of AND, OR, NAND, NOR, XNOR and

XNOR gates are shown below. The simulation result of QCA cell

implementation of AND, OR, NAND and NOR gates are shown in Figure

4.50 to Figure 4.53 required clock zone 0 only.

The QCA cell implementation of XOR and XNOR gates as shown

in Figure 4.15 and Figure 4.17. The simulated output of XOR and XNOR is

shown in Figure 4.54 and Figure 4.55. These circuits have four clocking

zones. Initially clock 0 is used to get the inputs A and B, clock 1 is used to

route inputs for majority gate logic, clock 2 is used for finding majority logic

and clock 3 is used to compute output. The output is available at clock 0

again. Clock 1 to 3 considered here is a sequence of setup for hold, relax and

release phase, to control the flow of information in QCA circuits.

Table 4.21 Simulation Analysis based on simulation engine type

(Logical Structures using MG)

Simulation

Engine

Simulation

Type

Simulation

time of XOR

(sec)

Simulation

time of

EXNOR(sec)

Bistable

Approximation

Exhaustive 3 2

Vector table 3 3

Coherence

vector

Exhaustive 85 69

Vector table 93 for 6 input 67

The result analysis of proposed XOR and XNOR gates, based on

simulation engine and simulation type is given below. There are two

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integrated simulation engines available with QCADesigner: the Coherence

Vector Simulation Engine, which is slower, but provides more accurate

results, than the Bistable Simulation Engine. Simulation results are presented

as waveforms, optionally grouped in buses as shown in Figure 4.54 and

Figure 4.55.

Figure 4.51 Simulation result of AND

Figure 4.52 Simulation result of OR gate

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Figure 4.53 Simulation result of NAND gate

Figure 4.54 Simulation result of NOR gate

Figure 4.55 Simulation result of XOR gate

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Figure 4.56 Simulation result of XNOR gate

4.7 CONCLUSION

The logical structures using QCA have been designed and tested

using QCADesigner software. The operation of the structures using majority

gates has been verified according to the truth table. The design and detailed

characteristics analysis of NNI and AOI gates are described in this chapter.

The standard logic functions have been designed with a help of proposed rules

and algorithms using these two gates are presented here. The proposed layouts

are significantly smaller than the circuits using CMOS technology and it

reduces the area as well as complexity required for the circuit than the previous

QCA circuits. The design works satisfactorily and produces required results.

The implementation of this design may lead to the efficient use of a logical

unit in various applications.

chapter 4 design of logical structures using qca...

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