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[email protected] 19-11-2007

http://www.vlsi.wpi.edu/cds/flow.html

This site contains a complete on-line tutorial for a typical bottom-up design flow usingCADENCE Custom IC Design Tools (version 97A). The examples were generated using

the HP 0.6 um CMOS14TB process technology files, prepared at North Carolina State

University (NCSU) and made available through MOSIS.
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0- Login and Running Cadence

1. To run Cadence, type in a terminal :

cds /usr/local/tools

icfb &

It will take a while, until Cadence setup is finished.

2. Two windows will appear on the screen :

Command Interpreter Window

Command Interpreter Window (CIW) is the main window of the Cadence software

environment, which enables you to have control over every part of Cadence.

You can perform many tasks using CIW :

Open new windows

Start tools and quit design sessions

View warnings, errors and other informational messages Change the configuration of your working environment

Use theInput Line for typing commands

Library Manager
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The Library Manager is a tool that you can use to organize your libraries and cells in a

design. It has three main boxes (columns) which correspond to Library, Cell, and View,

respectively.

The following is a list of operations you can do on the libraries and cells using the

Library Manager:

Create

Delete

Move

Copy

Rename

Edit properties

Import/export data

For more information refer to Cadence Design Framework II Help.

Cadence Design Framework II Help

The Cadence Design Framework II (DFII) Help manual is a comprehensive document onusing Cadence DFII tools that can be accessed from within the Cadence environment.

You can access the manual in two ways :

Type the following at the command prompt in any shell to open the stand-alone

manual. remote> openbook &

The main menu of the manual will pop up as seen below.
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Click on theHelp button on any Cadence application

For example, if you click onHelp in a schematic editor, the following help pageshows up.

NOTE: If you encounter any problems with accessing the main menu of the manual, trytyping

openbook -quit

at the command prompt.
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1- Design Specifications

The bottom-up design flow for a transistor-level circuit layout always starts with a set of

design specifications. The "specs" typically describe the expected functionality (Boolean

operations) of the designed block, as well as the maximum allowable delay times, the

silicon area and other properties such as power dissipation. Usually, the designspecifications allow considerable freedom to the circuit designer on issues concerning the

choice of a specific circuit topology, individual placement of the devices, the locations ofinput and output pins, and the overall aspect ratio (width-to-height ratio) of the final

design. Note that the limitations spelled out in the initial design specs typically require

certain design trade-offs, such as increasing the dimensions of the transistors in order to

reduce the delay times.

In a large-scale design, the initial design specifications may also evolve duringthe design

process to accomodate other specs or limitations.

This implies that the designer(s) of individual blocks or modules must communicateclearly and frequently about the spec updates, in order to avoid later inconsistencies.

As an example, the initial design specs of a one-bit binary full adder circuit are listedbelow:

Technology: 0.8 um twin-well CMOS

Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case)

Transition times of "sum" and "carry_out" signals


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2- Schematic Capture

The traditional method for capturing (i.e. describing) your transistor-level or gate-level

design is via the schematic editor. Schematic editors provide simple, intuitive means to

draw, to place and to connect individual components that make up your design. The

resulting schematic drawing must accurately describe the main electrical properties of allcomponents and their interconnections. Also included in the schematic are the power

supply and ground connections, as well as all "pins" for the input and output signals ofyour circuit. This information is crucial for generating the corresponding netlist, which is

used in later stages of the design. The generation of a complete circuit schematic is

therefore the first important step of the transistor-level design flow. Usually, some

properties of the components (e.g. transistor dimensions) and/or the interconnectionsbetween the devices are subsequently modified as a result of iterative optimization steps.

These later modifications and improvements on the circuit structure must also be

accurately reflected in the most current version of the corresponding schematic.
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A detailed example description of "Schematic Capture"

The basic steps to capture a schematic are the following:

Open a new schematic design

Select and place components Pick up supply voltages

Wire components

Edit component properties

Place pins

Check&Save

Example : Schematic Capture (CMOS Inverter)

Step 1 : Open a new schematic window

Note : Before you begin with going through this example, be sure that you have the

Library Manageropen.

1. ClickFile on the menu banner in theLibrary Managerand hold the left mouse

button until you chooseNew and then Cellview.

A small new window called "Create New File" appears.

2. There are four main fields in the Create New File window :

Library Name

You have to choose your working directory by clicking and holding the leftmouse button on theLibrary field. Since our library name is "tutorial" in this

example, we choose the corresponding label, "tutorial".
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Cell Name

Enter the name of your cell for which you will draw the schematic. In our

example, we will draw the schematic of an inverter, so we type "inverter" in the

Cell Name field.

View Name

The View Name indicates the level of the design hierarchy. You can determine

that you are going to draw either a symbol or a schematic or a layout in this fieldjust by typing the corresponding view name. Since we will draw the schematic of

an inverter, the correct view name choice is "schematic" for our example.

Tool

Here, you have to select the design editing tool that you will use to enter your

design. The tool depends on the hierarchy level of your design. If you click andhold the left mouse button on the tool field, you will see the available tools. Only

three of these tools will be used for all the examples.

Composer Schematic : Schematic editor

Composer Symbol : Symbol editor

Virtuoso Layout : Layout editor
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Since we will draw a schematic, we choose "Composer Schematic". Choosing

Composer Schematic automatically converts the View Name to schematic.

Actually, the selected tool converts the View Name to the corresponding one.

3. Now, click on "OK" to close this window and open the new schematic editor

window chosen in the "Create New File" window.

Step 2 : Add components

Note : At this point, you should have an empty schematic editor window open.

1. The first thing to do is to add and place components which will be used in the

schematic.

The components we need for a schematic of an inverter are the following :

PMOS : p-type MOSFET NMOS : n-type MOSFET

VDD : Power supply voltage

GND : Ground line

To add components, click onAddin the menu banner of the schematic entry window and

choose Component, as shown below.

( Add --> Component )

2. Two new pop-up windows appear.

One of them is "Add Component Window", where you can enter theLibrary Name, Cell

Name and the View Name of the component to be added to the schematic.
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The other window is the "Component Browser", which enables the designer to browseeasily through the available libraries and select the desired components.

Component Browserpops up every time theBrowse button on theAdd Componentwindow is clicked.

3. We begin picking up the components by selecting the MOS transistors from the

Component Browserwindow.

You must be careful to pick up the components from the correct library. You can changethe component library simply by clicking and holding the left mouse button on the library

field.

The correct library is "NCSU_Analog_Parts", so, select this library if it is not selected

when you opened the Component Browser. After all, the window should appear likeshown above.

There are many folders under this library. Each of them is named depending on the

components they include. So, to pick up an n-type MOSFET, you have open the

"N_Transistors" folder by clicking once on it. The new folder contains many symbolswhich are also shown in the picture below. Pick up the NMOS transistor by clicking once

on "nmos", which is a model for a three terminal n-type MOSFET.


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If you move the mouse cursor on the schematic window, you will see a bright NMOS

transistor symbol moving with the mouse pointer showing the gate terminal of the

transistor. At this point, you decide where to put this transistor. Click on a location in the

schematic window, where you want to put the transistor. Please refer to the images belowto see the difference between a "to be placed" transistor (left image) and "a placed

transistor" (right image).

The same procedure can be applied to select and to place the PMOS transistor. The only

difference is to pick "pmos" from the "P-Transistors" folder in the Component Browser.The "select-and-place" procedure for PMOS is summarized below.
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Note : Always make sure that you are not confusing a PMOS transistor with an NMOS

transistor. The differences between the PMOS symbol and the NMOS symbol are:

There is a tiny circle at the gate terminal of PMOS transistors.

The direction of the arrow which always marks thesource terminal of the

transistor is different. The arrow points from thesource terminal towards the

transistor in the PMOS symbol, while it points out towards thesource terminal in

the NMOS symbol.

Step 3 : Placing supply voltage components

1. Picking up the supply voltage components involves the same steps as in addingtransistors to the schematic.

ChooseAddand then Componenton the menu banner if you somehow closed the

Component Browserwindow.

Click on the folder "Supply_Nets", so that you will access the components in this

folder.


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We will put the components "vdd" and "gnd" in our schematic. You can pick up

one of them simply by clicking on the corresponding one. Let's assume that we

take "vdd" first, so, click on "vdd", move the mouse on the schematic window andplace the component by clicking a location in that window. The individual steps

of this procedure are described in the images below.

2. You can follow similar steps for placing the "gnd" component.
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3. At this point, we are finished with selecting and placing the necessary

components.

Press "ESCAPE" (ESC) key on the keyboard to close the Component BrowserandAddComponentwindows.

1. After all the components are placed, they should be connected according to the

function they realize.

To connect the components in a schematic, we use wires by choosingAddand then Wire

(narrow) on the menu banner.( Add --> Wire (narrow) )

This command initiates the wiring mode.

2. A new window calledAdd Wire will pop-up.

In this window you can change the routing method and the draw mode.

3. We begin to wire the components by connecting VDD and the source terminal of

the PMOS transistor.

Every component has tiny red squares on its terminals where you can do the wiring.

Connecting any two nets in the schematic is done by first clicking at one of the nets and

then at the other one.


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During these steps, you will always be prompted by the schematic window. The message

appears in the bottom most field of the schematic window. If you follow the instructions

prompted in that field, you can easily complete your job. In this step, the followingphrase will be prompted :

Point at the starting point for the router

Since we begin with wiring the VDD and the source of PMOS, we click first at the center

of the red square which corresponds to the VDD net.

One end of the wire is now fixed, and you will realize that the other end floats and movesaccording to the mouse pointer. You will also see that the nearest net to the floating end

of the wire is automatically highlighted. The new prompt is the following :

Point at ending point for the router


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3. Click on the target net which is the source terminal of the PMOS transistor .

This was the final step of connecting the two nodes. The same procedure can be applied

for the rest of the nodes; first choose any two nodes which should be connected. Then,wire them together just by clicking first one of them and then the other.

As long as you are in the wiring mode, you will be prompted about the next step you

have to do, as described above. PressESCon the keyboard, to leave the wiring mode.

You will be in this mode, as long as you don't press ESC or choose another commandfrom the menu.

4. The remaining steps are summarized below.

In the wiring mode,

Click on the drain terminal of PMOS.

Click on the drain terminal of NMOS.

Click on the gate terminal of PMOS.

Click on the gate terminal of NMOS.


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Click on the GND node.

Click on the source terminal of NMOS.

5. Your schematic should look like the schematic shown in the image below.

Press ESC key to leave the wiring mode.


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Step 5 : Edit properties of components

The components you select and place from the library always come with a set of defaultparameters or properties. You can (and usually should) modify component properties

according to your design specifications. Here are the steps to edit component propertiesin the schematic window.

1. Select the PMOS transistor by clicking on it .

The selected component should be highlighted by a bright rectangle (box) around it.

2. ChooseProperties and then Objectfrom theEditmenu.

A larger window with many editable fields appears which is called theEdit ObjectProperties window.

3. Edit the properties by clicking on the corresponding field.

You may change the values forWidth orLength depending on your design specifications.

Usually, you will change only the Width value, which stands for the channel width, W.The default values for these properties are the smallest available values which are

determined by the current technology.


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To edit the channel width of the transistor, click on the Width field. Then enter a new

value which is either a result of your calculations or just an initial value to see how theperformance changes depending on this variable. While changing a parameter, you have

pay attention to the unit you use (click here for the list of units). The channel width is

changed to 1200 nm (nanometers) which is equal to 1.2 um (micrometers).

4. Click OK after editing the properties in theEdit Object Properties Window.

The most important parameters (type, dimensions) always appear in the schematic

window. You can easily observe the changes of these properties that are listed near thecorresponding transistor in the schematic.
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Step 6 : Placing the pins

You must place I/O pins in your schematic to identify the inputs and the outputs. A pin

can be an input or an output or an input-output (bi-directional) or a switch pin. We willonly use an input pin and an output pin in our inverter schematic.

1. ClickAddon the menu and then selectPin on the pull-down menu.

2. TheAdd Pins window appears.

3. Enter the name of your input pin in thePin Names field.

The input name in this example is "Inp" (note that the pin names can be completely

arbitrary). Also, note that theDirection option is set toInputindicating that the current

pin is an input pin. As long as you enter pins of the same direction, you can enter pin

names one after the other in thePin Names field, only putting space between them. In thiscase, each time you place a pin, the next one will appear until all your pins are placed in

the schematic.


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4. Move the mouse cursor on the schematic window to place pin.

Now, you have your input pin with the name "Inp" floating in the schematic window.

Point to a location to place the input pin. Since the input is the gate terminals of bothtransistors, it is more convenient to put this pin in front of the common node of these

terminals.

4. Go back to theAdd Pin window to pick up an output pin.

First, you have to change the pin direction to Output. To do this, click the left mousebutton on theDirection field and select Outputin the pop-up menu. Enter the output pin

name, which is "Outp" in our example.

5. Place the output pin by clicking on a lcoation in the schematic window.

The procedure is completely analogous to the placement of input pins. Now it is better toput the output pin near the common drain node which is the output of the inverter circuit.


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At this point, you are finished placing the pins. Press ESC on the keyboard to close the

Add Pin window.

6. Connect the pins to the corresponding nodes using wires.

The wiring procedure is the same as described in the previous steps. Wiring the pins issummarized below :

Click onAddon the menu and then select Wire (narrow). You are now in the wiring

mode again.

Click on the input pin. => The other end of the wire is floating.

Click on a point on the common wire which connects the gate terminals of both

transistors, PMOS and NMOS.

Click on the output pin. => The other end of the wire is floating.

Click on a point on the common wire which connects the drain terminals of both

transistors, PMOS and NMOS.


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Press ESC to close the wiring mode.

At the end of this step, your schematic should look like the following:

Step 7 : Check and Save

1. ClickDesign on the menu banner and then select Check and Save.


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During this tutorial, you may save your design selecting Save on theDesign menu. It is

also strongly advised that you save your designs frequently, every time after you make

significant changes, so that you don't loose your data because of a computer crash orbecause of a mistake that can happen in a complicated design environment such as this

one.

2. Check the message field in the CIW window to see the error and the warning

messages.

You can see the message in the screen-shot above indicating that there is no error in our

schematic. If this wasn't the case, the errors would have been listed in this window.Check the message field every time you save a design.
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3- Symbol Creation

If a certain circuit design consists of smaller hierarchical components (or modules), it is

usually very beneficial to identify such modules early in the design process and to assign

each such module a corresponding symbol (or icon) to represent that circuit module. This

step largely simplifies the schematic representation of the overall system. The "symbol"view of a circuit module is an icon that stands for the collection of all components within

the module.

A symbol view of the circuit is also required for some of the subsequent simulation steps,thus, the schematic capture of the circuit topology is usually followed by the creation of a

symbol to represent the entire circuit. The shape of the icon to be used for the symbol

may suggest the function of the module (e.g. logic gates - AND, OR, NAND, NOR), butthe default symbol icon is a simple rectangular box with input and output pins. Note that

this icon can now be used as the building block of another module, and so on, allowing

the circuit designer to create a system-level design consisting of multiple hierarchy

levels.
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A detailed example description of "Symbol creation"

The basic steps to create a symbol are the following:

Open the schematic design Create the cellview

Locate the pins

Edit shape of the symbol

Check&Save

Example : Creating a Symbol

Step 1: Opening an existing schematic

Note : You can skip this step if you have your schematic window open.

1. Select your library by clicking on it in the library column of theLibrary Manager.

The cells in the library will appear in the cell column.

2. Select your cell by clicking on it in the cell column of theLibrary Manager.

The existing cellviews of your cell will appear in the view section. At this point, there

should be only the "schematic" view appearing in the "view" column.

3. Select your cellview by clicking on it in the view column of theLibrary Manager.
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The name of the selected view will appear in the small cell window.

4. In the Library Manager Window, select Open from the File menu:

( File --> Open )

The schematic of the design will pop-up.

Step 2 : Creating cellview

1. From theDesign menu, select Create Cellview and then From Cellview :

( Design --> Create Cellview --> From Cellview )

The following window will pop up.

2. Check the view names and clickOK

Before clicking OK, you have to ensure that the target view name issymbol, which isindicated with "To View Name" in the bottom-right corner of the pop-up window. If not,

then you can change the target view name to "symbol" by clicking and holding the left

mouse button on the corresponding box.

Step 3 : Locating the pins

1. After clicking OK in the Cellview From Cellview, window the following window

pops up :
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In this window (Symbol Generation Options) you can edit your pin attributes and

locations. In the default case, you will have your input(s) on the left and your output(s) on

the right of the symbol.

You can change your pin locations simply by putting the pin name in the correspondingpin location field.

2. If you don't want to change anything or you are finished with editing the pinspecifications, then press OKto continue.

A new window will appear, showing your new symbol. This is the "black box" or symbolrepresentation of your schematic.

Step 4 : Editing the shape of the symbol icon

1. In the new window, the automatically generated symbol is shown.

As seen in the window, the default shape of the symbol icon is a rectangle, with the pinslocated as defined during the previous step in Symbol Generation Options pop-up

window. The small red squares indicate the connection points for each corresponding pin.

The red rectangle surrounding the whole symbol determines the clickable area to select

the symbol when used in a schematic.

2. If you are not satisfied with the symbol properties, then you can create a new

symbol simply by editing the existing one.


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You can do the following operations on your symbol :

Deleting/replacing some existing parts

Adding new geometric shapes

Changing the locations for pins and instance name

Adding new labels

The following is an example for a manually created inverter symbol, which was obtained

by editing the symbol above.

Step 5 : Check and Save

1. To check and save the symbol, choose Check and Save from theDesign menu :

( Design --> Check and Save )

While editing the symbol, you can use only Save, which does not check anything. At this

point, checkinga symbol means comparing the symbol view with the corresponding

schematic view, by matching all of the pin names. This occurs only when you click onCheck and Save.


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4- Simulation

After the transistor-level description of a circuit is completed using the Schematic Editor,

the electrical performance and the functionality of the circuit must be verified using a

Simulation tool. The detailed transistor-level simulation of your design will be the first

in-depth validation of its operation, hence, it is extremely important to complete this stepbefore proceeding with the subsequent design optimization steps. Based on simulation

results, the designer usually modifies some of the device properties (such as transistorwidth-to-length ratio) in order to optimize the performance.

The initial simulation phase also serves to detect some of the design errors that may have

been created during the schematic entry step. It is quite common to discover errors such

as a missing connection or an unintended crossing of two signals in the schematic.

The second simulation phase follows the "extraction" of a mask layout (post-layoutsimulation), to accurately assess the electrical performance of the completed design.
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A detailed description of "Simulation".

The basic steps to simulate a design are the following:

Open a new schematic design

Select and place components (circuit symbol to be simulated) Select and place components (test-bench elements)

Wire components

Define the voltage sources

Determine the output load

Open the simulator window

Edit your simulation parameters

Run the simulation

Re-run the simulation

Step 1 : Open a new schematic design

Note : You should first create thesymbolof the circuit schematic which you want to

simulate.

If you did not have the symbol for the schematic, refer to the "Create Symbol" example.

1. Open a new schematic.

Follow the same procedure described in "Open a New Schematic" to create a new

schematic where you will put your simulation schematic for the inverter. Give a name toyour new schematic which makes it clear that the new schematic is to simulate the

inverter. The new schematic is called "invTest" in this example.

Step 2 : Select and place components

Note : At this point, you should have an empty schematic editor window open.

1. The first step is to add and to place the components which will be used to simulate

the inverter.

The components we need for the simulation of the inverter are the following :

* inverterSymbol created

for the inverter

* VDD Power supply
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voltage

* GND Ground line

* vdcDC voltage

source

* vpulsePulsewaveformgenerator

* C Capacitor

Adding and placing components in a schematic was explained previously [click here for

the corresponding example]. Here you will see how to pick up asymbolyou created fromyour library, and to place it in your schematic.

2. ClickAddand select Component.

Two new pop-up windows appear, Component BrowserandAdd Component.

ClickBrowse in theAdd Componentwindow to activate the Component Browser.
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3. You should pay attention to the library from which you take the components.

The point where you have to take care of is picking up the components from the correct

library. You can change the component library simply by clicking and holding the leftmouse button on the library field. In this step, we have two source libraries, one is the

given component library "NCSU_Analog_Parts", and the other is our design librarywhich contains the components that we designed stored previously. This library's name in

our example is "tutorial". This means, to pick up the inverter symbol, we have to changethe library of the Component Browserto our library, "tutorial". This can be done, as

explained in previous steps [click here for the corresponding example], by clicking and

holding the left mouse button until you select the corresponding library in the pop-uplibrary list.

After the library "tutorial" is selected, there will be a new list of components which are

included in this library. Every symbol that you created within this library will show up

here. So, by clicking on "inverter" in the component list in the Component Browser, youcan pick up the symbol you created for the inverter.

You can always check the corresponding fields in theAdd Componentwindow to make

sure that you selected the desired component. This can be easily seen in the image below.
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You can go to the schematic window and place the symbol of the inverter to a point by

clicking on it. These two images below show the symbol before placement and after

placement.

We are now finished placing the symbol of the inverter. Placement of the other

components will be explained in the next step.

Step 3 : Select and place components

Note : You do not have to place the components exactly the same way as seen in the

example images. As long as you connect them correctly, you can always move a

component to some other location in the same schematic.

1. Pick up and place the rest of the components required for the simulation.

The remaining components are in the "NCSU_Analog_Parts" library. Change yourlibrary from "tutorial" to "NCSU_Analog_Parts". Refer to theprevious example (step

3 :"Changing the library in the Component Browserwindow") to see how you can change

the source library.

Place the supply nets, "vdd" and "gnd".
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Open the folder "Supply_Nets", select "vdd" and "gnd" and place them anywhere

in the schematic window. Your original circuit schematic already does have these

supply nets attached to its appropriate nodes, but now you have to define thevoltages in the new schematic window.

Place the voltage sources, "vdc" and "vpulse".

Go up one folder to the main content folder. Open the folder "Voltage Sources",select "vdc" and "vpulse" and place them in the schematic window.

Place the capacitance which will be the output load, "cap".
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Go up one folder to the main content folder. Open the folder "R_L_C", select

"cap" and place it in the schematic window.

We placed all the necessary components for this schematic.

2. Why did we put these components into this schematic ?

You can think of this procedure (creating a new schematic and placing these components

into the new schematic) as being analogous to building a "test-bench" for the circuit you

designed. As in the real test-bench case, you must build a simple test set-up (consisting ofvoltage sources, load devices, etc.) around your original circuit to measure its operation

and its characteristics.

Step 4 : Wire components

Note : Always save your designs if you make any changes on it. If you make a mistake,you can use the undo command under the editmenu.

1. Connect the DC-voltage source "vdc" to "vdd" and "gnd".

A DC-voltage source called "vdd" is required as the power supply voltage in all digitalcircuits. The value of this voltage usually depends on the technology used. The

technology we use for this example is HP 0.6u AMOS14TB [click here for furtherinformation], which is low-voltage process meaning that the typical VDD voltage value

is 3.3 V.

N.B.: HP AMOS14TB is no longer available from MOSIS
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http://www.mosis.com/Technical/Processes/proc-hp-amos14tb.html

Available Fabrication Processes http://www.mosis.com/Technical/Processes/

To supply the VDD voltage to the circuit, we will use a DC-voltage source with a

constant voltage value of 3.3 V. How to configure the voltage value of the source will beexplained in the next steps. The connections of the voltage source are shown in the imagebelow. Simply wire the "vdd" with the positive terminal of the DC-voltage source and the

"gnd" with the negative terminal of the voltage source.

2. Connect the pulse wavefrom generator "vpulse" to the input of the inverter"Inp".

The pulse generator is a voltage source which can produce pulses of any duration, period

and voltage levels. This source will be used to generate the input data (stimuli), so that

we can observe the output of the inverter and see if the inverter operates correctly.

Wire the positive terminal of the pulse generator to the input pin of the inverter "Inp" and

then the negative terminal of the pulse generator to "gnd".
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For the sake of simplicity, you can also pick up more "gnd" components and put them

into your schematic where it is needed. All nodes connected to the "gnd" symbol will beshort circuited throughout the schematic, i.e., all of them will stay at the reference voltage

level which is O V (zero volts).

The following is an example to describe the case explained in the last paragraph. The

connections in the schematic below describe the same circuit as in the schematic shownabove.

To add a new component, you can either use theAdd Componentand the Component

Browserwindow, or copy the component if it exists in the current schematic. For


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example, you may prefer to copy the existing "gnd" instance which is the one we

connected with the DC-voltage source, rather than browsing through the libraries and the

components.

3. Connect the load capacitance "cap" to the output of the inverter "Outp".

In CMOS digital circuits, the output nodes are typically loaded by purely capacitive

loads. One of the important specifications of a circuit would usually be its driving

capability for a given capacitive load. The larger the capacitive load at the output, thelarger the delays to drive this load.

Wire the positive node of the capacitance to the output pin of the inverter "Outp" and

then the negative node of the capacitance to "gnd".

4. At the end of these steps, your entire schematic looks like the following.
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Step 5 : Define the voltage sources

In this step, we will enter the necessary parameters for the voltage source components.

1. Edit the properties of the DC-voltage source.

Select the DC-voltage source by clicking on it. The selected component is highlighted bya bright box (rectangle) around it.


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ClickEditon the menu bar and selectProperties and Object, respectively.

TheEdit Object Properties window appears.

Edit theDC voltage field in theEdit Object Properties window and type the VDD value

which is 3.3V in our examples.

Click the "OK" button on theEdit Object Properties window. You can observe the new

value entered for theDC-voltage near the DC-voltage source.
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2. Edit the properties of the pulse generator

Select the pulse generator instance in the schematic.

TheEdit Object Properties window for the pulse generator appears.


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The parameters which are listed in the image above are used to define a pulse which willbe repeated periodically. How to use these parameters to define the input pulse waveform

is explained in the figure below.

The following image shows the values for the pulse generator parameters which are used

to define the input waveform. Click on OK to apply these changes and close theEditObject Properties window.


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Finally, the new values for the important parameters of the pulse generator appear near

the its instance.

Step 6 : Determine the output load

1. Edit the properties of the capacitor which is the output load of the inverter.

Select the capacitor by clicking on it.


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Clickediton the menu and selectProperties and Object, respectively. TheEdit Object

Properties window appears. This time, the listed parameters are valid for the selected

capacitor.

The only parameter we change is the capacitance. As shown in the previous image above,

the default value for the capacitance is 1 pF (picofarads). This value may be too high for

a typical inverter load in this technology. Refer to the "Commonly Used Prefixes forUnits in Cadence". By editing the corresponding field in theEdit Object Propertieswindow, we change the capacitor value to 25 fF (femtofarads).
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Click on OK in theEdit Object Properties window. The capacitance will be updated to

the new value which is 25 fF.

2. Add labels to the nodes you want to observe after the simulation.

In Cadence, labeling a node corresponds to adding certain names to the wires. In our

example, there are two important nodes (or wires) which we want to observe during oursimulations. These are the input and the output nodes of the inverter. You may think that

you labeled these nets before while you were drawing the schematic for the inverter byadding the pins. But, those labels are only valid in that schematic which is now in the

lower level of hierarchy. So, every time you create a symbol and use this symbol in a new

schematic, you have give new labels to the nodes you want to specify.

Select Wire Name in theAddcommand list, as shown below.


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TheAdd Wire Name window appears. Now, you can type all the label names one after theother in theNames field. You will see that there isn't any information related to the

direction of the nodes, because only the pins are defined with a direction.

In the example, we will label the two wires as "in" and "out".

After all the labels are typed, move the mouse cursor on the schematic. Now you will seethe first label floating with the mouse cursor. Click on the corresponding net to name the

net with this label. As soon as you put the first label, the second label will appear on the

mouse cursor. This procedure is repeated until you are finished putting all label names

you entered in theAdd Labelwindow.


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The schematic with the wires ("in" and "out") labeled is shown in the image below.

Close theAdd Labelwindow either by clicking on OK in the window or pressing ESC onkeyboard.

Save your design by using Check and Save in theDesign command list. Be sure that the

CIW doesn't report any errors or any warnings.

Step 7 : Open the simulator window

Now, we are ready to simulate our design. We will useAnalog Artistas the simulator.


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1. Open theAnalog Artistwindow.

Click on Tools in the menu banner of the schematic entry window and chooseAnalog

Artist.

TheAnalog Artistmain window will appears, as shown below. As you can see, there are

four main fields in this window.

Design

Analyses Design Variables

Outputs

Note that the library, the cell and the view names are listed in theDesign field, so thatyou can check that you are simulating the desired cell using the correct view.

Step 9 : Run the Simulation

Now, we have to select the nodes that we want to observe as simulation results.

1. Click on Outputs in the menu banner, select To Be Plottedand thenSelect on

Schematic.


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The schematic window becomes active, so that you can select the nodes to be observed in

that window.

2. Click on the nets which you want to observe in the schematic window.

The selected nodes are the input of the inverter, "in", and the output of the inverter "out"which drives the capacitive load. Each time you select a node, the corresponding wire

name appears in the Outputs list.

3. Press ESC to finish your selections.

4. Start the simulation by clickingSimulation and then selectingRun.


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The waveform window appears after the simulation is completed. It includes the

waveforms of the selected nodes plotted between t=0 and the determined Stop Time

which is 30 ns in our example.

You will see the two waveforms together, plotted on the same time axis. To separate the

waveforms, from the menuAxes select option To Strip. Once seperated you can select the

waveforms by clicking on them and draging them on top of each other to group. To

return to the initial composite waveforms, from the menuAxes select option ToComposite. Notice that this option has replaced the formerTo Strip option.

Step 10 : Re-run the Simulation


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If you are not satisfied with the simulation results, there are two different aspects that can

be modified :

The simulation environment is not satisfactory.

This means that the setup to simulate your design should be modified. You canbasically change two things, the properties of the input signal you feed to the

circuit and the amount of output load which is capacitive. Also, make sure that the

power supply voltages are connected properly.

Refer to the step "Define the voltage sources" to setup your input sources.

Refer to the step "Determine the output load" to change the capacitance value of

the capacitor.

Refer to the step "Define the voltage sources" to check the connections of your

power supply voltages.

These changes are made without descending to a lower level of hierarchy in thedesign.

You have to modify your circuit design.

Usually, you will need to change the W/L ratios (the ratio between the channel

width and channel length) of the transistors to meet your design specifications.

Therefore, you have to edit your design which consists only of a CMOS inverterin our example.

The procedure describing how to re-run the simulation after editing the design is

summarized below.

1. Go back to the schematic window and select the symbol of your design. The

symbol for the inverter should be selected in this example.
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2. Click onDesign in the menu banner, selectHierarchy and thenDescend Edit.

3. Click on OK in theDescendwindow which asks the designer which view of the

design is to be edited.

The existing schematic window now displays the schematic view for the inverter, by

going one level down through the design hierarchy.

4. Make the appropriate changes in the editable schematic of the design.

To change the existing W/L ratio for a specific transistor, you have to edit its objectproperties. Refer to the "Edit Object Properties" step in the schematic example.

5. Check and save your new schematic.

6. Click onDesign in the menu banner, selectHierarchy and thenReturn.
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Never forget that you are editing the design at a lower level of the hierarchy - you alwaysmust return to the original level from which you have descended.

7. Go to theAnalog Artistwindow and run the simulation again, as described in

"Run the Simulation" step.

As the simulation runs, you can switch to the waveform window, because the waveformswill be updated after the simulation is finished.

You can iterate on your design as described in this section of the tutorial. When you want

to end the simulation, quit theAnalog Artistsimulator. This will automatically close the

Waveform window, too.

Note: Quitting a tool does not mean closing the corresponding window. Please alwaysuse the "close" or "quit" commands located in the menu bar of the tool.
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5- Mask Layout

The creation of the mask layout is one of the most important steps in the full-custom

(bottom-up) design flow, where the designer describes the detailed geometries and the

relative positioning of each mask layer to be used in actual fabrication, using a Layout

Editor. Physical layout design is very tightly linked to overall circuit performance (area,speed and power dissipation) since the physical structure determines the

transconductances of the transistors, the parasitic capacitances and resistances, andobviously, the silicon area which is used to realize a certain function. On the other hand,

the detailed mask layout of logic gates requires a very intensive and time-consuming

design effort.

The physical (mask layout) design of CMOS logic gates is an iterative process whichstarts with the circuit topology and the initial sizing of the transistors. It is extremely

imporant that the layout design must not violate any of theLayout Design Rules (shown

on the last pages of this tutorial), in order to ensure a high probability of defect-free

fabrication of all features described in the mask layout.

Another alternative of generating the mask layout (other than manually design) is to

make use of automated tools for generating a layout from a schematic using the device

level placer.
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Note: Two detailed examples description are shown bellow the first is the main

procedures in "Mask Layout Manual Design" and the second is a description of

generating a layout from a schematic using the device level placer.

1- A detailed example description of the main procedures in "Mask Layout

Manual Design".

Example: CMOS Inverter Layout

In this tutorial, a simple CMOS inverter layout will be drawn step by step. We will start

with a simple design idea and will complete the mask layout using different techniques.

Steps of Layout Design

Starting up

o Design Idea

o Create Layout Cellview

o Virtuoso and LSW

NMOS

o Drawing the N-Diffusion (Active)

o The Gate Poly

o Making Active Contacts

o Covering Contacts with Metal-1
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o The N-Select Layer

PMOS

o Drawing the P-Diffusion (Active)

o Transistor Features

o The P-Select Layero Drawing the N-Well

Connecting both transistors

o Placing the PMOS and NMOS

o Connecting the Output

o Connecting the Input

o Making a Metal-1 connection for the Input

o Power Rails

o P Substrate contact

o N Substrate contact

o Enclosing the Substrate Contact DRC and Finalizing

o Design Rule Checking

o Final Layout

Design Idea

To draw the mask layout of a circuit, two main items are necessary at the beginning:

1. A circuit schematic

2. A signal flow diagram

1. Circuit schematic

Any physical layout will actually correspond to a circuit schematic. It is important thatthe schematic of a functionally correct circuit is present and the layout is drawn according

to the schematic (and not the other way around).

The schematic will the contain exact connection diagram and individual device

properties. Two example inverter schematics can be seen below. While both schematicsare identical, the one on the right is drawn in a way to resemble the final layout.
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In this example the NMOS transistor and the PMOS transistor have identical dimensions

W=1.2u and L=0.6u

2. Signal flow diagram (I think this is the same as stick diagrame)

A layout can be drawn in a number of different ways. The most important factordetermining the actual layout is the signal flow. The layout will almost in all cases be a

part of a larger structure or the basic building element of an array of identical blocks.

In modern fabrication technologies, more than one physical layer can be used to transfer

signals. For example with the fabrication technology used throughout this manual, a totalof 4 layers (poly, Metal-1, Metal-2, Metal-3) can be used. The general flow of the signal

connections as well as their layers need to be pre-determined. The following is an sample

flow diagram used for the example layout:

In this flow diagram, it has been decided that all signals are on the same layer (blue,

Metal-1) and that all signals will travel horizontally. Note that the signal flow diagram is

just a concept that you can visualize for a particular circuit, or a simple scetch that you

can scribble on the back of an envelope. The actual mask layout will roughly follow thisconcept.
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Create Layout Cellview

We will assume, that you have logged on and started Cadence Design Tools, and that you

already have created a design library for yourself. Please refer to Starting CadenceSection if you have not done so.

1. From the Library Manager, choose File thenNew and then Cellview

( File --> New --> Cellview )

2. Enter cellname and choose layoutcellview

A dialog box will appear prompting you for the design library, cellname and cellview.Make sure that the library name corresponds to your design library, choose a name foryour cell and choose Virtuoso as the design tool. The cellview will be selected as layout.
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Virtuoso and LSW

Two design windows will pop-up after you have entered the design name.

LSW

The Layer Selection Window (LSW), lets the user select different layers of the mask

layout. Virtuoso will always use the layer selected in the LSW for editing. The LSW canalso be used to determine which layers will be visible and which layers will be selectable.

To select a layer, simply click on the desired layer within the LSW.

Virtuoso

Virtuoso is the main layout editor of Cadence design tools. There is a small button bar onthe left side of the editor. Commonly used functions can be accessed by pressing these

buttons. There is an information line at the top of the window. This information line,

(from left to right) contains the X and Y coordinates of the cursor, number of selectedobjects, the travelled distance in X and Y, the total distance and the command currently

in use. This information can be very handy while editing. At the bottom of the window,

another line shows what function the mouse buttons have at any given moment. Note that

these functions will change according tto the command you are currently executing.

Most of the commands in Virtuoso will start a mode, the default mode is selection, as

long as you do not choose a new mode you will remain in that mode. To quit from any

mode and return to the default selection mode, the "ESC" key can be used.
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Drawing the N-Diffusion (Active)

Now we will start drawing our first transistor. which will be the NMOS transistor of the

CMOS inverter. From the schematic, we know that this transistor has a channel width of1.2u. The width of the transistor will correspond to the width of the active area. We will

select the n-diffusion layer and draw a rectangular active area to define the transistor.

1. Select nactive layer from the LSW

2. From the Create menu in Virtuoso select Rectangle

( Create --> Rectangle )

3. Draw the box

You are now in rectangle mode. Select the first corner of rectangle in the layout window

(you may select any point within the window but try to select a point close to the origin),click once, and then move the mouse cursor to the opposite corner. Using the information

bar, draw a box that is 3.6u horizontal and 1.2u vertical. All units are in micrometers by

default. To simplify the drawing, a grid of half a lambda is used, that is the cursor movesin 0.15u increments only.
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The Gate Poly

The second step is to draw the gate. We will use a vertical polysilicon rectangle to create

the channel. Note that the length of the transistor channel will be determined by the widthof this poly rectangle.

1. Selectpoly layer from the LSW

2. From the menuMisc chooseRuler

( Misc --> Ruler )

The ruler is a very handy function. In our case we need to draw the poly rectangle in the

middle of the diffusion region. Furthermore, design rules tell us thatpoly must extend atleast by 0.6u (2 Lambda) from edge of the diffusion(D.R: Poly,Minimum gate extension

of active). To pinpoint the location of the poly gate we can use two rulers. One ruler will

be used to determine the horizontal distance of the poly gate from the diffusion edge,while a second ruler will show the minimum amount of poly extension outside the

diffusion according to the design rules

3. Draw poly rectangle
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The starting point is pinpointed by two rulers. The rectangle function is used to draw a

poly rectangle that is 0.6u horizontal and 2.4u vertical.

Making Active Contacts

The next step is to make the active contacts. These contacts will provide access to thedrain and source regions of the NMOS transistor.

1. Select the ca (Active Contact) layer from the LSW.

2. Use the ruler to pinpoint a location 0.30u from the edges of diffusion(D.R: Active-Contact, Minimum active overlap).

3. Create a square with a width and height of 0.6u within the active area (D.R:

Active-Contact, Exact contact size).

4. From theEditmenu choose Copy

( Edit --> Copy )
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You could choose to draw the second contact the same way as you have drawn the first

one. However, copying existing features is also a viable alternative.

The copy dialog box will pop-up as soon as you select the copying mode. For thisoperation the default values are appropriate. The Snap Mode is an interesting option.

When this is in orthogonalsetting the copied objects will move only along one axis. Thisis a good feature to help you avoid alignment problems.

5. Copy the contact

After you enter the copy mode, an object must be selected. Click in the contact, you'll

notice that the outline of contact will attach to your cursor. Now move the object, andclick when you are satisfied with the location.

Design rulesstate that the minimum contact to poly spacing must be 0.6u (2 lambda)

(D.R: Active-Contact, Minimum spacing to gate of transistor). You can use a ruler to

pinpoint the location. Please note that you can interrupt any mode for placing a ruler (andzooming in and out). After you are finished (by hitting "ESC" key) you'll return to the

mode you were in.
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Now you have placed an active contact each into the source and drain diffusion regions

of the transistor.

Covering Contacts with Metal-1

Active contacts in fact only define holes in the oxide (connection terminals). The actual

connection to the corresponding diffusion region is made by the Metal layer.

1. Select layerMetal-1 from the LSW

2. Draw two rectangles 1.2u wide to cover the contacts
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Note that Metal-1 has to extend over the contact in all directions by at least 0.3u (1

lambda)(D.R: Metal-1,Minimum overlap of any contact).

The N-Select Layer

Each diffusion area of each transistor must be selected as being of n-type or p-type. This

is accomplished by a defining the "window: of n-type (or p-type) doping (implantation),

through a special mask layer called n-select (p-select).

1. Select nselectlayer from the LSW.

2. Draw a rectangle extending over the active area by 0.6u (2 lambda)in all

directions (D.R: Select, Minimum select overlap of active).
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This is it ! Our first transistor is finished, now let us make a few million more of the same

:-)

Drawing the P-Diffusion (Active)

Now that we have drawn the NMOS transistor, the next step is to draw the PMOStransistor. The basic steps invloved in drawing the PMOS are the same.

1. Selectpactive layer from the LSW

2. Draw a rectangle 3.6u by 1.2u

You can use the cursor keys and the zoom function to find yourself a place to build the

transistor. Make sure you leave enough separation between the NMOS and the PMOS.Note that the PMOS transistor will also be sorrounded by the N-well region.


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Transistor Features

These three steps are identical to the ones done for the NMOS.

1. Draw the gate poly


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2. Place the contacts

3. Cover contacts with Metal-1

The P-Select Layer

As with the NMOS transistor, the p-type doping (implantation) window over the activearea must be defined using the n-pelect layer.


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1. Selectpselectlayer from the LSW

2. Draw a rectangle that extends over the active area by 0.6u (2 lambda) in all

directions.

Drawing the N-Well

In this process, the silicon substrate is originally doped with p-type impurities. NMOS

transistors can be realized on this p-type substrate simply by creating n-type diffusion

areas. For the PMOS transistors however a different approach must be taken: A larger n-type region (n-well) must be created, which acts like a substrate for the PMOS transistors.

From the process point of view, the n-well is one of the first structures to be formed on

the surface during fabrication. Here we chose to draw the n-well after almost everything

else is finished. Note that the drawing sequence of different layers in a mask layout iscompletely arbitrary, it does not have to follow the actual fabrication sequence.

1. Select the nwelllayer from the LSW

2. Draw a large n-well rectangle extending over the P-Diffusion


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The n-well must extend over the PMOS active area by a large margin, at least 1.8u (6

lambda) (D.R: Active, Source/drain active to well edge).

Placing the PMOS and NMOS transistors

In this example, we did not pay much attention to the location of the transistors while

building them. As long as the design rules are not violated, the transistors can be placed

in any arbitrary arrangement. Yet based on our original signal flow diagram, it is moredesirable to place the PMOS transistor directly on top of the NMOS transitor- for a more

compact layout.

1. Select the PMOS transistor

First make sure that you are in selection mode. If you are in any other mode (like

rectangle drawing mode) exit the mode by pressing "ESC". Now using the mouse, clickand drag a box that covers your PMOS. If you were successful, all the objects within the

PMOS would be highlighted as in the figure below:
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2. From the menuEditselect the optionMove

( Edit --> Move )

A window will pop-up similar to the copy window. This time we will have to change the

Snap Mode option toAnyangle so that we can move the transistor freely.

3. Pick the reference point

We will be asked to find a reference point for the object to be moved. The cursor will

practically grab the object from that reference point. Since we want an accurateplacement, it is advisable to select a point for which alignment is simpler. The corner

between the diffusion and the poly is a good place to grab the PMOS.

After we have picked the reference point, the outline of the shape will appear attached tothe cursor and we will be able to move the shape around. Since theminimum distance

from diffusion to the n-well edge is 1.8u(D.R: Active, Source/drain active to well edge,
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the PMOS and NMOS have to be at least 3.6u apart. We can place a ruler to help us

aligning the two shapes and to measure the distance.

4. Place the transistor

You can drop the selected object (in this case consisting of the n-well, the p-active, polyand contacts) into its final location by clicking once on the left mouse button.

Connecting the Output


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