Chapter 8

COMPUTATIONAL ELEMENTS

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Design of an ALU Subsystem• Design of 4-bit adder:

From the table one form of the equation is:Sum Sk = Hk Ck-l + Hk Ck-1

New carry Ck = AkBk + HkCk-1

Where Half sum Hk = AkBk + AkBk

For Ak = Bk, then, Ck = Ak = Bk

Ak ≠ Bk, then, Ck = Ck-l

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of AdderGeneration:

• This principle of generation allows the system to take advantage of the

occurrences “Ak=Bk”.

Propagation:

• If we are able to localize a chain of bits Ak Ak+1... Ak+p and Bk Bk+1...

Bk+p for which Ak not equal to Bk for k in [k, k+p], then the output

carry bit of this chain will be equal to the input carry bit of the chain.

Pk = Ak XOR Bk

Gk = Ak Bk

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder

Figure 6.21: CMOS adder element (Symmetrical arrangement)

= AkBk + HkCk-1

=

+

COMPUTATIONAL ELEMENTS

Further Consideration of Adder

Adder element using pass/generate concept

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder

Figure 6.22: Manchester carry-chain element

• The Manchester Carry Chain: • If the carry path is precharged to VDD, the transmission gate is then reduced to a simple NMOS transistor.

• In the same way the PMOS transistors of the carry generation is removed.

• The Manchester cell is very fast, but a large set of such cascaded cells would be slow due to the distributed RC effect and the body effect making the propagation time grow with the square of the number of cells.

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder

Figure 6.23: Cascaded Manchester carry-chain elements with buffering

• The Manchester Carry Chain:

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder

Figure 6.25: Carry select adder structure (6-bit)

• Adder Enhancement Techniques:– Carry select adders:

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder• Adder Enhancement Techniques:

– Carry select adders:

Optimization of the carry select adder:• Computational time

T = k1nk1 – delay through one adder cell

• Dividing the adder into blocks with 2 parallel pathsT = k1n/2 + k2

k2 – time needed by multiplexer of next block to select actual output carry• For a n-bit adder of M-blocks and each block contains P adder cells in

series so thatT = Pk1 + (M – 1) k2 ;

n = M.P minimum value for T is when M= (k1n / k2 )1/2

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder• Adder Enhancement Techniques:

– Carry skip adders:

Figure 6.26: Carry skip adder structure

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder• Adder Enhancement Techniques:

– Carry skip adders:

Figure 6.27: Carry skip adder structure

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder• Adder Enhancement Techniques:

– Carry skip adders:

Figure 6.28: Carry skip adder structure (24-bit)

COMPUTATIONAL ELEMENTS

UNIT – VI SUBSYTEM DESIGN PROCESSES AND ILLUSTRATION

Further Consideration of Adder• Adder Enhancement Techniques:

– Carry skip adders:Optimization of the carry skip adder:• Let us formalize that the total adder is made of N adder cells. It contains M

blocks of P adder cells. The total of adder cells is thenN = M.P

• The time T needed by the carry signal to propagate through P adder cells isT = k1.P

• The time T' needed by the carry signal to skip through M adder blocks isT‘ = k2.M

• The problem to solve is to minimize the worst case delay which is:Tworst = 2(P – 1).k1 + (M – 2)

where P = n/M• T is minimum when M = (2n.k1/k2)1/2

Serial-parallel multiplier (2*2)

Serial-parallel multiplier (4*4)

The Braun Array multiplier(4 bit)

The Braun Array multiplier (4 bit)