chapter 3 vlsi design

© Digital Integrated Circuits2nd Devices

Chapter 3Chapter 3VLSI DesignVLSI Design

The DevicesThe DevicesMarch 28, 2003


Goal of this chapterGoal of this chapter

Present intuitive understanding of device operation

Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-sub-micron

effects Future trends


The DiodeThe Diode

n

p

p

n

B A SiO2Al

A

B

Al

A

B

Cross-section of pn-junction in an IC process

One-dimensionalrepresentation diode symbol

Mostly occurring as parasitic element in Digital ICs


Depletion RegionDepletion Regionhole diffusion

electron diffusion

p n

hole driftelectron drift

ChargeDensity

Distancex+

-

ElectricalxField

x

PotentialV

W2-W1

(a) Current flow.

(b) Charge density.

(c) Electric field.

(d) Electrostaticpotential.


Diode CurrentDiode Current


Models for Manual AnalysisModels for Manual Analysis

VD

ID = IS(eVD/T – 1)+

–

VD

+

–

+

–VDon

ID

(a) Ideal diode model (b) First-order diode model


Junction CapacitanceJunction Capacitance


Secondary EffectsSecondary Effects

–25.0 –15.0 –5.0 5.0

VD (V)

–0.1

I D (A

)

0.1

0

0

Avalanche Breakdown


Diode ModelDiode Model

ID

RS

CD

+

-

VD


SPICE MODELS

• SPICE: Simulation Program with Integrated Circuit Emphasis, by UCB in early 1970’s.

• Level 1: Long Channel Equations - Very Simple

• Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations

• Level 3: Semi-empirical - Based on curve fitting to measured devices

• Level 4 (Berkeley Short-Channel IGFET Model, BSIM3v3): Empirical - Simple and Very Popular,.

• Full-fledged BSIM3v3 model (denoted as LEVEL 49) covers over 200 parameters.


SPICE ParametersSPICE Parameters


What is a Transistor?What is a Transistor?

VGS VT

RonS D

A Switch!

|VGS|

An MOS Transistor


The MOS TransistorThe MOS Transistor

PolysiliconAluminum/Cu


MOS Transistors -MOS Transistors -Types and SymbolsTypes and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact


Threshold Voltage: ConceptThreshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel


The Threshold VoltageThe Threshold Voltage


The Body EffectThe Body Effect

-2.5 -2 -1.5 -1 -0.5 00.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VBS

(V)

VT (

V)


Current-Voltage RelationsCurrent-Voltage Relations

QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D (A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT


Transistor in LinearTransistor in Linear

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions


Transistor in SaturationTransistor in Saturation

n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

Pinch-off


Current-Voltage RelationsCurrent-Voltage RelationsLong-Channel DeviceLong-Channel Device


A model for manual analysisA model for manual analysis


Current-Voltage RelationsCurrent-Voltage RelationsThe Deep-Submicron EraThe Deep-Submicron Era

LinearRelationship

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D (A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation


Velocity SaturationVelocity Saturation

(V/µm)c = 1.5

n

(m/s

)

sat = 105

Constant mobility (slope = µ)

Constant velocity


PerspectivePerspective

IDLong-channel device

Short-channel device

VDSVDSAT VGS - VT

VGS = VDD


IIDD versus V versus VGSGS

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10-4

VGS (V)

I D (A

)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10-4

VGS (V)

I D (A

)

quadratic

quadratic

linear

Long Channel Short Channel


IIDD versus V versus VDSDS

-4

VDS (V)0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

I D (A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10-4

VDS (V)

I D (A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

ResistiveSaturation

VDS = VGS - VT

Long Channel Short Channel


A unified modelA unified modelfor manual analysisfor manual analysis

S D

G

B


Simple Model versus SPICE Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS

(V)

I D (A

)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT


A PMOS TransistorA PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0 x 10-4

VDS (V)

I D (A

)

Assume all variablesnegative!

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V


Transistor Model Transistor Model for Manual Analysisfor Manual Analysis


The Transistor as a SwitchThe Transistor as a SwitchVGS VT

RonS D

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid


The Transistor as a SwitchThe Transistor as a Switch

0.5 1 1.5 2 2.50

1

2

3

4

5

6

7x 10

5

VDD

(V)

Req

(O

hm)


The Transistor as a SwitchThe Transistor as a Switch


MOS CapacitancesMOS CapacitancesDynamic BehaviorDynamic Behavior


Dynamic Behavior of MOS TransistorDynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB


The Gate CapacitanceThe Gate Capacitance

tox

n+ n+

Cross section

L

Gate oxide

xd xd

L d

Polysilicon gate

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W


Gate CapacitanceGate Capacitance

S D

G

CGC

S D

G

CGC

S D

G

CGC

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

Cutoff SaturationTriode


Gate CapacitanceGate Capacitance

WLCox

WLCox

2

2WLCox

3

CGC

CGCS

VDS /(VGS-VT)

CGCD

0 1

CGC

CGCS = CGCDCGC B

WLCox

WLCox

2

VGS

Capacitance as a function of VGS(with VDS = 0)

Capacitance as a function of the degree of saturation


Measuring the Gate CapMeasuring the Gate Cap

2 1.52 12 0.5 0

3

4

5

6

7

8

9

103 102 16

2

VGS (V)

VGS

Gate

Ca

paci

tan

ce (

F)

0.5 1 1.5 22 2

I


Diffusion CapacitanceDiffusion Capacitance

Bottom

Side wall

Side wallChannel

SourceND

Channel-stop implant NA1

SubstrateNA

W

xj

LS


Capacitances in 0.25 Capacitances in 0.25 m CMOS m CMOS processprocess


The Sub-Micron MOS TransistorThe Sub-Micron MOS Transistor

Threshold Variations Subthreshold Conduction Parasitic Resistances


Threshold VariationsThreshold Variations

VT

L

Long-channel threshold Low VDS threshold

Threshold as a function of the length (for low VDS)

Drain-induced barrier lowering (for low L)

VDS

VT


Sub-Threshold ConductionSub-Threshold Conduction

0 0.5 1 1.5 2 2.510-12

10-10

10-8

10-6

10-4

10-2

VGS (V)

I D (A

)

VT

Linear

Exponential

Quadratic

Typical values for S:60 .. 100 mV/decade

The Slope Factor

ox

DnkT

qV

D C

CneII

GS

1 ,~ 0

S is VGS for ID2/ID1 =10


Sub-Threshold Sub-Threshold IIDD vs vs VVGSGS

VDS from 0 to 1.0V

kT

qV

nkT

qV

D

DSGS

eeII 10


Sub-Threshold Sub-Threshold IIDD vs vs VVDSDS

DSkT

qV

nkT

qV

D VeeIIDSGS

110

VGS from 0 to 0.3V


Summary of MOSFET Operating Summary of MOSFET Operating RegionsRegions

Strong Inversion VGS > VT

Linear (Resistive)

VDS < VDSAT

Saturated (Constant Current)

VDS VDSAT

Weak Inversion (Sub-Threshold) VGS VT

Exponential in VGS with linear VDS dependence


Parasitic ResistancesParasitic Resistances

W

LD

Drain

Draincontact

Polysilicon gate

DS

G

RS RD

VGS,eff


Latch-up (Effect of Parasitic Resistance)Latch-up (Effect of Parasitic Resistance)


SPICE Transistors Parameters


MAIN MOS SPICE PARAMETERS


SPICE Parameters for Parasitics


SPICE Model for NMOS and PMOSSPICE Model for NMOS and PMOS


SPICE Deck for a CMOS InverterSPICE Deck for a CMOS Inverter


SPICE Simulation ResultSPICE Simulation Result


Future PerspectivesFuture Perspectives

25 nm FINFET MOS transistor


SummarySummary

Transistor Modeling is important for CMOS circuit design

(updated by IC manufacturing companies based on

ongoing technologies).

SPICE parameters provide a good link between

manufacturer and designers.

SPICE model/parameters need to be updated to reflect

the behavior of the MOS in deep sub-micron technology.

Recently, capacitor/inductor modeling become important

for Radio-frequency (RF) designs.

chapter 3 vlsi design

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