JNTU ONLINE EXAMINATIONS [Mid 2 - VLSI design]

1. For the 4X4 bit barrel shifter, the regularity factor is given by1. 82. 43. 24. 16

2. The level of any particular design can be measured by1. SNR2. Ratio of amplitudes3. regularity4. quality

3. In tackling the design of system the more significant property is1. logical operations2. test ability3. topological properties4. nature of architecture

4. Any bit shifted out at one end of data word will be shifted in at the other end of the word is called

1. end-around2. end-off3. end-less4. end-on

5. In the VLSI design the data and control signals of a shift register flow in1. horizontally and vertically2. vertically and horizontally3. both horizontally4. both vertically

6. The subsystem design is classified as1. first level2. top level3. bottom level4. leaf-cell level

7. The larger system design must be partition into a sub systems design such that1. minimum interdependence and inter connection2. complexity of interconnection3. maximum interdependence4. arbitarily chosen

8. To simplify the subsystem design, we generally used the1. interdependence2. complex interconnections3. regular structures4. standard cells

9. System design is generally in the manner of1. down-top2. top-down3. bottom level only4. top level only

10. Structured design begins with the concept of1. hierarchy

2. down-top design3. bottom level design4. complex function design

11. Any general purpose n-bit shifter should be able to shift incoming data by up to number of places are

1. n2. 2n3. n-14. 2n-1

12. For a four bit word, a one-bit shift right is equivalent to a1. two bit shift left2. three-bit shift left3. one bit shift left4. four-bit shift left

13. The type of switch used in shifters is1. line switch2. transistor type switch3. crossbar switch4. gate switch

The representation of basic cell used in multiplier is

14. = latchGFA = gated full adderPi = partial product sum inP = partial product sum outCi = carry inC = carry outd = line required for two's complement operation

Shown in figure (a)

1.Figure(a)Shown in figure (a)

2.Figure(a)Shown in figure (a)

3.Figure(a)Shown in figure (a)

4.Figure(a)

15. 1. 2. 3.

shown in figure (a)

4.Figure(a)

16. The carry chain in adder is consist with1. cross-bar swith2. transmission gate3. bus interconncection4. pass transistors

17. VLSI design of adder element basically requires1. EX-OR gate, Not and OR gates2. multiplexers, inverter circuit and communication paths3. multiplexers, EX-OR and NAND gates4. inverter circuits and communication paths

18. The number of basic cells required for an n-bit X n-bit multiplier is1. (3n+1)2. (3n+1)2n

3.

4.

19. The heart of the ALU is1. Register2. adder3. control bus4. I/O port

20. In the VLSI design the adder requirements may be stated asif Ak=Bk then else

1. if then else

2. if Ak=Bk then else

3. if Ak=Bk then

4. else S=21. In the VLSI design the carry of adder requirements may be stated as

if then C= &

1. then C=if then C= &

2. then C=if then C= &

3. then C=if then C= &

4. then C=22. Carry line in adder must be buffered after or before each adder element because

1. slow response of series pass transistors2. slow response of parallel line3. fast response of parallel pass transistors4. fast response of series line

23. The ALU logical functions can be obtained by a suitable switching of the1. carry line between adder elements2. sum line between adder elements3. carry line between shifter & buffer4. sum line between shifter & buffer

24. To fast an arithmetic operations, the multipliers and dividers is to use architecture of1. parallel2. serial3. pipelined4. switched

25. The logical expressions for the two output signals in terms of the four input signals in comparator for VLSI design areAi & Bi are two numbers to be comparedCi+1 & Di+1 are inputs form o/p of previous stageCi & Di are the out puts of the current stage

1.

2.

3.

4.

26. The representation of function of parity generator is

1.

2.

3.

4. 27. The number of bits increases in comparator then the

1. height increases2. width grows linearly3. width reduces linearly4. height reduces

28. The representation of a basic one bit cell isShown in figure (a)

1.Figure(a)Shown in figure (a)

2.Figure(a)

Shown in figure (a)

3.Figure(a)Shown in figure (a)

4.Figure(a)

29. The standard cell for an n-bit parity generator is1. n-1 bit cell2. one bit cell3. two bit cell4. n+1 bit cell

30. The parity information is passed from one cell to the next and is modified or not by a cell depending on the state of the

1. previous information2. output line3. input lines4. next information

31. The parity information (pi) passed from one cell to the next is modified when the input line (Ai) is at the state of

1. zero2. overline{A}i3. one4. independent of input line state

32. When cells of parity generator are butted together (indicate false statement)1. design rule errors are not present2. wastage of area is avoided3. inlet and outlet points of cells must be match up4. layer and position match is not necessary

33. The standard cell representation of comparator in VLSI design isAi and Bi are two mumbers to be compared.Ci+1 and Di+1 are inputs from outputs of previous stageCi and Di are the outputs of the currents stage.

Shown in figure (a)

1.Figure(a)Shown in figure (a)

2.Figure(a)Shown in figure (a)

3.Figure(a)Shown in figure (a)

4.Figure(a)

34. The two output signals of comparator remain at zero as long as the two bits being compared are

1. same2. zero3. one4. different

35. In the comparator the two inputs if A>B then the outputs are1. Ci=0 & Di=12. Ci=1 & Di=03. Ci=1 & Di=14. Ci=0 & Di=0

36. In the comparator the two inputs if A<B then the outputs are1. Ci=0 & Di=02. Ci=1 & Di=13. Ci=0 & Di=14. Ci=1 & Di=0

37. The width of n bit comparator isWhere w is the width of leaf cell

1. n w2. w3. (n-1) w4. n

38. The main draw back of asynchronous counter with respect to VLSI is1. The output change with respect to clock edge2. counter stages are cacaded3. the last counter stage to settle can be quite large4. clocking of each stage is carried out by the previous stage

39. ONE/ZERO detection circuits for word width of less than 32 bits is the1. pseduo-nMOS OR gate2. pseduo-nMOS NOT gate3. pseduo-nMOS NOR gate4. nmos OR gate

40. The delay from the last changing output to the ripple zero/one detector is a1. constant one gate delay2. variable delay3. greater than two gate delays4. constantly increasing delay

41. The speed that sychronous up/down counter can operate is determined by the1. ripple-carry time from the LSB to MSB2. substantially the clock time3. delay of registers4. settling time of counter

42. Detecting all ones or all zeros on wide words require1. large fanout AND or OR gates2. large fanin AND or OR gates3. large fan in EX-NOR or EX-OR gates4. large fanout NOR or NAND gates

43. In zero/one detector, the delay to the output is porportional to(N is bit width of the word)

1. N2. N2

3. -log N4. log N

44. Self-loading of large word widths in ONE/ZERO detectors is avoided by1. split into 8 or 16 bit chunks2. use large fan in gates3. use large word width pseudo-nMOS NOR gates4. use large fanout gates

45. Binary counters are used to cycle through a sequence of1. Decimal numbers2. binary numbers3. hexa decimal numbers4. octal numbers

46. An asynchronous counter has outputs that change at1. varying times with respect to the clock edge2. substantially the same clock time3. twice that of the clock edge time4. half time of the clock

47. The clocking of each stage of ripple counter is carried out by the1. common clock2. previous counter stage3. connected positive and negative cycles alternately4. master-slave flip-flop

48. Proper placement of memory elements makes maximum use of the1. available clock period2. cost of area3. power dessipation4. parasitics

49. A design that requires high density memory is usually1. a single ship2. on chip3. partitioned into several chips4. DRAMS

50. Random access memory at the chip level is classed as memory that has1. an access time dependent of the physical location of the data2. an access time independent of the physical loction of the data3. reading or writing of a particular datum with address4. examines a data word and compares this data with internally stored data

51. The following memory examines data word and compares this data with internally stored data

1. serial access memory2. random access memory3. content addressable memory4. shift registers memory

52. The main characteristics of on chip memory is1. small and slow2. large and slow3. small and faster4. large and faster

53. DRAM has a1. smaller layout and uses large power2. smaller layout and uses less power

3. more power and slower4. more power and faster

54. SRAM has a1. faster, more power and larger2. slower, more power and larger3. faster, less power and smaller4. faster less power and larger

55. On chip memory is comes under the category of1. high density memory2. medium density memory3. low density memory4. large density memory

56. On chip memory usually in the order of1. 10k bytes2. 50k bytes3. 1k bytes4. 100 k bytes

57. The simplest and safest way to use memory in a system is to treat it as a1. sequential component2. combinational component3. decoders4. NOR gates

58. Serial access memory at the chip level is classed as memory that has1. shift registers2. counters3. accesstime is independent of location of data4. internally stored data is used

59. The PLA provides a systematic and regular way of implementing multiple output functions of n variables in

1. POS form2. SOP form3. complex form4. simple form

60. V(input variables) X P(product terms) PLA is to maintain generality within the constraints of its dimensions then for

1. AND gate have n inputs and output OR gate must have P inputs2. AND gate have P inputs and output OR gate must have n inputs3. Both AND gate and OR gate have n inputs4. both AND and or gates have P inputs

61. A MOS PLA is realized by using the gate of1. AND2. OR3. AND-OR4. NOR

62. A CMOS PLA is realized by1. pseudo nmos NOR gate2. CMOS NOR gate3. pseudo nmos NAND gate4. CMOS NAND gate

63. The mapping of irregular combinational logic functions into regular structures is provided by the

1. FPGA2. CPCD3. standard cells4. PLA

64. The general arrangement of PLA is1. AND/OR structure2. OR/AND structure3. NAND/NOR structure4. EX-OR/OR structure

65. V XP X Z PLA represents as1. V-no.of input variables

P-no.of output functionsZ-no.of gates

2. V-no.of gatesP-no.of OR gatesZ- no.of AND gates

3. V-no.of input variablesP-no.of product termsZ-no.of output functions

4. V-no.of gatesP-no.of AND gatesZ-no.of output functions

66. To realize any finite state machine requirements, the PLA along with1. NOR gate is used2. feed back links is used3. NAND gate is used4. NOT gate is used

67. To reduce the PLA dimensions, the simplification must be done on a1. individual output basis2. multi-output basis3. individual product term4. individual input basis

68. The regularity of the PLA sturcture shows that both the AND and OR planes are constructed from

1. different standard cells2. standard cells are not used3. same standard cells4. feed back control links

69. The behavior AND/OR structure of a system may be capured in1. hardware description language2. software language3. tabulation method4. state design model

70. VHDL differs from other software languages by including1. behaviour of system2. compilers, debuggers and simulatois3. syntax4. machine understanding language

71. The advantage of fuse-based FPGAS compared to other FPGAs is1. allows large number of interconnections2. complex fabrication process

3. larger in size4. modified without changing hardware

72. Where the design is of moderate complexity and time to silicon is of paramount importance then the probably suitable approach is

1. FPGA2. PLA3. standard cell4. PAL

73. A single time programmable FPGA is the type of1. fuse-based FPGA2. SRAM-FPGA3. EPROM-FPGA4. Flash based FPGA

74. The SRAM-FPGA's consists of a large array of programmable logic cells known as1. Erasable programmable logic devices-EPLD2. configurable logic blocks-CLB3. micro cells4. AND/OR array

75. The fabrication process of EPROM-FPGA is1. easy and high integration density2. easy and low integration density3. complex and high integration density4. complex and low integration density

76. The following is a chip whose final logic sturcture is directly configured by the end user1. gate array design2. field programmable logic3. standard cell design4. full custom design

77. FPGA can be programmed as per the1. positive logic2. negative logic3. users logic4. fixed logic

78. The logic cells in FPGA contains1. only combinational circuits2. only sequential circuits3. both combinational & sequential circuits4. only Flip-Flop circuits

79. The individual cells of FPGA are interconnected by1. AND gates and switches2. matrix of wires and programmable switches3. OR gates and non programmable switches4. AND & OR gates

80. The programming in fuse-based FPGAS is done by1. configurable logic blocks2. memory cell3. multiplexer4. closing antifuse switches

81. A slow rate control is used in the I/O block of CPLD because of1. matching with other parts2. suppressing the occurrence of the noise

3. grounding the I/O pin4. global tree state control

82. Which part of the CPLD is programmed to pass the latched or unlatched, true or complement output to the external output

1. AND gates of array2. OR gates of array3. I/O cell4. standard cell

83. A slow rate control in the I/O block of CPLD is used to make the rising and falling of the output pulse

1. zero2. one3. faster4. slow

84. A macro cell in CPLD is composed of1. J-K flip-Flop2. R-S Flip-Flop3. T-Flip-Flop4. D-Flip-Flop

85. CPLD devices are used for design modification because these are1. reprogrammable2. non programmable3. always a fixed program4. design modificaions are not possible

86. CPLD is a devices of numeorus integrated SPLDs and interconnections between them is1. non programmable2. programmable3. used single SPLD4. permanent connections are used

87. To compose a circuit in case of CPLD, it has wiring among1. the pins2. the logic3. connection on printed board4. the function

88. CPLD is possible to rewrite it many times because1. it is records the contents of the circuit to the flash memory2. a standard cell is used3. it is a plastic loaded chip4. it is AND/OR array

89. The CPLD can be rewritable in about1. < 10times2. < 100 times3. < 1000times4. > 1000times

90. During programming of CPLD, the I/O pin is at the state of1. logic O2. logic 13. high impedance4. open

91. The function block of CPLD consists of1. AND array, OR array and macro cell

2. OR array, product term allocator and macrocell3. AND array, product term allocator and marcocell4. AND array, product term and OR array

92. In the standard cell, all the cells should have1. identical heights and widths2. identical heights and the widths of the cells may vary3. identical widths and the variable heights4. variable heights and widths

93. Cells in different rows of standard cells can be connected by using1. internal wires2. feed through cells3. intra wires4. route around a complete row

94. When a design is implemented in the standard cell design style1. only signal routing has to be done2. replacement of library cells3. change of the design fucntion4. change of placement of blocks

95. Standard cell designs are less area efficient than a full custom design due to1. feed through cells2. multiple cell rows3. fixed size of the cells4. lower clock rates

96. Where the design is of a reduced cost and include size memories the preferable approach is

1. FPGA2. gate array logic3. standard cell4. full custom

97. Logic gates are placed in rows of standard cells of1. equal height2. equal width3. variable height4. constant width

98. Logic gate are placed in rows of standard cells are interconnected using1. internal wires2. intra wire3. routing channel4. switch box

99. Semicustom design using standard cells enable the designes to use1. a functional modules (available in library)2. a layout automatically generated3. an interconnections between cells4. only basic logic functions

100. In the standard cell design methodology1. each transistor is manually designed2. predefined logic and function blocks are available3. final logic structure is directly configured4. an array of unconnected logic gates

101. Standard cell designs are operate at1. higher clock rates and less area efficient

2. lower clock rates and less area efficient3. lower clock rates and high area efficient4. higher clock rates and high area efficient

102. PAL16R8, here R denotes the1. number of inputs2. number of outputs3. active high4. presence of flip-flop

103. PAL10L8, here L denotes the1. active high2. active low3. number of inputs4. number of outputs

104. If one function depend on other functions in PAL then1. OR gate is used2. feed back is used3. ex-OR gate is used4. realization is not possible

105. One approach that is becoming more popular and feasible is to model chips as collections of

1. standard cells2. no.of gates3. reprogrammable gate arrays4. semicustom design sub systems

106. Programmable array logic provide a convinient way of realizing1. combinational networks only2. sequential networks only3. both combinational and sequential network4. not used for realization

107. Programmable array logic is made up of1. programmable AND and OR array2. programmable AND and fixed OR array3. Fixed AND and programmable OR array4. Fixed AND and OR array

108. The number of product terms in PAL depends on1. number of AND gates2. number of OR gates3. number of addition of both AND and OR gate4. independent of number of gates

109. To realise the sequential networks in PAL, the type of flip-flop used is1. D flip-flop2. T flip-flop3. J-K flip-flop4. R-S flip-flop

110. The combination PAL devices with active-low outputs mean1. AND-OR logic2. AND-NOR logic3. AND-NAND logic4. NAND-OR logic

111. In order to realize a Boolean function with a combinational PAL device, the function must be expressed in

1. POS form2. SOP form3. Standard form4. complex form

112. When the PAL sequential device has a tristate buffer at the output stage then the type of circuit implemented is

1. sequential circuit2. product terms3. pos form4. combinational circuit

113. An interface description of design entity in VHDL must define the1. logical interface to the outside world2. internal operations3. organization of hardware4. logical definition

114. The following is the Design flow through typical CMOS VLSI toolsShown in figure (a)

1.Figure(a)Shown in figure (a)

2.Figure(a)Shown in figure (a)

3.Figure(a)Shown in figure (a)

4.Figure(a)

115. VHDL was developed for the VHSIC components to1. design and interchange format2. simulation and fault analysis only3. design description and simulation4. certification and architectural evaluation

116. The primary abstraction in VHDL is called1. interface description2. body description3. structural description4. design entity

117. Each port declaration of design entity in VHDL includes a1. hardware description2. port name, associated mode and type3. internal operations4. logical functions

118. The component declarations in VHDL include aninface description for each of the1. signals2. input port3. output/port

4. logic gates119. VHDL provides high-level definition and simulation of

1. simple digital systems2. complex digital systems3. standall cell design systems4. analog systems

120. The design is commenced with a1. RTL description2. behavioral description3. logic description4. functional description

121. Generally logic optimization systems divide the problem into1. technology dependent phase and technology mapping phase2. technology independent phase and technology mapping phase3. combinational circuits and sequential circuits4. registers and logic gates

122. Logic optimization is used to improve the logic to meat1. logic constraints2. timing or area constraints3. power constraints4. parasitic constraints

123. In the case of state-machines RTL compilers need to provide for1. automatic state assignment and minimization2. trigger the registers onthe rising edge of clock3. set of logic gates4. set of registers

124. Logic optinmization scheme convertsthe logic into a1. two level PLA POS form2. standard form3. two level PLA SOP form4. combinational and Register circuits

125. Logic synthesis systems are very useful for1. transforming between technologies2. very good silicon implementation3. to create control logic4. to create micro code

126. Behavioral synthesis is1. technology dependent and specify the implementation2. technology independent and specify the implementation3. technology independent and without specify the implementation4. technology dependent and without specify the implementation

127. Which of the following synthesis converts RTL description to a set of registers and combinational logic

1. behavioral synthesis2. RTL synthesis3. logic level synthesis4. layout synthesis

128. RTL description are captured using1. hardware description language (HDL)2. software description language3. cathedral series

4. micro controllers129. The wait statement of VHDL indicates the presence of

1. counters2. logic gate3. multiplexer4. clocked register

130. The case operator of VHDL indicates the1. counters2. logic gate3. multiplexer4. clocked register

The delay of the gate in logic level simulators can be calculated as the intrinsic gate delay (no load) actual load in some units

131. the delay per load in some units

1. +

2. x +

3. + x

4. 132. Standard cell and memory are simulated at the level of

1. both at logic level2. both at functional level3. logic level and functional level4. fuctional & logic level

133. RTL simulations may be done with the actual clock timing by estimating the1. layout loading capacitancess2. required speed of design3. size of tansistor4. power dessipation iin the circuit

134. The enccution time of timing simulator compared to circuit simulators is1. more2. less3. equal4. not comparable

135. The layout is a faithfull reproduction of the structure of the RTL description means1. all the components are placed correctly2. all signals are routed correctly3. functionality is correct

4. system performs as rquired136. Simulator of software tools is used to

1. compile the program2. synthesize the given circuit3. predict and verify the performance4. transfer structureal description to physical form

137. The most detailed and accurate simulation technique is1. gate level2. timing3. logic level4. circuit-level

138. Circuit level simulators are characterized by1. high accuracy and long simulation time2. less accuracy and long simulation time3. high accuracy and short simulation time4. less accuracy and short simulation time

139. Circuit level & timing simulations evaluated on a timing sub step basis, where as logic-level simulation is

1. appled voltage basis2. applied current basis3. event driven basis4. logic - level basis

140. Switch level simulators merge logic simulators techniques with some circuit simulation techniques by modeling transistors as

1. gates2. open circuits3. short circuits4. switches

141. Switch - level simulators are combination of1. circuit level and timing simulators2. Circuit level and logic level simulators3. logic level & timing simulators4. gate and logic level simulators

142. YACR2 router is used to route the1. switch box2. maze3. rectangular channel4. global routing

143. The min-cut alogrithm minimizes the area by1. spliting the conceptual layout until the leaf cells are reached2. minimize the SOP form of given function3. minimize the POS form of given function4. uses standard cells and proper floor planning

144. Maze routers can route any configuration but have comparatively1. short running time2. small area3. long running time4. large area

145. Interactive graphic editors are used to capature the1. RTL circuit2. behaviour of system

3. layout4. structure of system

146. In layout systhesis generally two phases are required they are1. designing and minimizing2. placement and routing3. optimization of logic and functioning4. testing and verification

147. The traditional method of capturing a digital system design is1. schematic editor2. flow table3. ASIC design4. compiler

148. Many design systems allow a diagrams because these are1. more easy2. quickly understood3. samll in size4. small area

149. Many design systems generally used HDL because of1. easy2. quickly understood3. small in size4. easily modified

150. Schematic editors in digital design systems provids a1. means to draw and connect components2. compilation of code3. simulation of system4. synthesis of system

151. A layout editor might interface to a design rule checking program to allow interactive checking of

1. layout minimization2. DRC errors3. design errors4. possibility of transistor sizing

152. Floor plan editors provide graphical feed back about1. size and placement of modules2. internal layout details3. connectivity of components4. input / output port details

153. Pearl program analyzer is used to calculate1. node voltages2. loop urrents3. DRC errors4. delays in circuit operation

154. The timing analyzer does not recognize some paths for some reasons these paths are called

1. critical paths2. crossed paths3. sneak paths4. long paths

155. Simulations with delays are used to check the1. timiing problems

2. DRC errors3. functionality4. speed of system

156. Pearl program analyzer is used to calculate1. node voltages2. loop currents3. DRC errors4. delays in circuit oeration

157. Network isomorphism is used to prove that a layout is equivalent to1. a network extracted from a schematic2. optimum layout3. optimized placement and routing4. fabrication mask

158. Electron Beam exposure system is used to1. create a data used for mask making2. make a layout from net list3. check the design rules4. verify the timing analysis

159. A timing analyzer implemented at the transistor level can provide a designer1. rapid global functional simulation2. rapid feed back about critical paths3. detailed module verification4. details of DRC errors

160. Network isomorphism is used to prove that1. two network are equivalent and therefore should function equivalently2. the critical path in the system isthe longest path3. the layout satisfies the design rules4. the design is optimum

161. The process of comparing two network is commonly called (indicate incorrect answer)1. Layout versus schematic2. network analysis3. network isomorphism4. netlist compoarison

162. A design-rule-checker is used to1. find DRC errors2. conforms the layout to the geometric design rules3. verify the functionality of the geometric design rules4. verify the functionality of the design

163. The last step in the design process is1. layout extraction2. back annotation3. pattern generation4. design -rule verification

164. For MOS circuits the dominent faults are due to1. short circuits in diffusion layers2. open circuits in diffusion laye3. short circuits in interconnections4. open circuits in interconnections

165. Very effective aid to testing and testbility of a design is1. a reset facility2. facility to probe the circuit nodes

3. provide circuit modification4. sealed in over glass

166. Correct operation of a design must not be dependent on1. Rise times or fall times2. short circuits in diffussion layer3. Layout4. short and open circuits in metal layer

167. Generally functional tests are impractical due to1. fast simulation times and short verification sequences2. fast simulation times and long verification sequences3. slow simulation times and very long verification sequences4. slow simulation times and short verification sequences

168. During testing of VLSI system (Indicate the false statement)1. The chip is sealed by an overglass layer2. circuits nodes cannot be probed for monitoring3. circuits can be modified4. circuits cannot be modified

169. Generally the amount of chip area dedicated for testability is

1.

2.

3.

4. 170. The advantage of a reset facility in the design is

1. testing always from fixed position2. testing proceed from known enditions3. testing proceed from unknown conditions4. It is not related to testing

171. A 20 bit counter is split into four five bit section, them the required steps for testing are

1. 2. four sets of 25

3. five sets of 24

4. five sets of 25

172. Manufacturing tests are used to verify that1. function of a chip as a whole2. every gate operates as expected3. function in the field4. the clock response of the chip

173. VHDL, verilog hardware description languages are used for testing of1. manufacturing tests2. fanctionality test3. Design testing4. chip testing

174. Functionality tests seek to verify the1. function of a chip as a whole2. every gate operates as expected3. function in the field

4. the clock response of the chip175. Adhoc testbility means

1. testability arrangements configured with the architecture changes2. testbility with structure changes3. testbility arrangements configured without changing the archtecture4. testbility without structure changes

176. A measure of goodness of a test programm is1. the amount of fault coverage2. time3. cost4. degree of performance

177. At the prototype state it is possible to provide special test points by1. providing extra pads for probing2. It is not possible to test3. modifing the circuit4. link connections

178. A finite state machine with 'n' possible inputs to the conbinational logic and 'm' memory elemens then the required test vectors are

1. m+n2. 2m

3. 2n

4.

179. Generally the system is partitioned for testing because1. reducing the chip area2. reducing the no. of pads3. reducing the number of test vectors4. reduce the required power

180. The two key concepts underlying all considerations for testabiloity are1. set and reset2. controllability and observability3. intial and final conditions4. pads and links

181. Controllability in testing means1. being able to set known internal states2. being able to generate all states3. being able to generate all combinations of circuit states4. read out the result of the state changes

182. Being able to generate all states to fully excise all combinations of circuit states is called1. controllability2. observability3. combinationatorial testbility4. reset facility

183. Being able to read out the result of the state changes as they occur is called1. controllability2. reset facility3. combinational testability4. observality

184. The facults occure due to thin-oxide shorts or metal-to metal shorts are called1. stuck at zero facults2. short-circuit faults

3. open-circuit faults4. bridge faults

185. Radom logic is probably best tested via1. self testing2. full serial scan or parallel scan3. boundary scan4. LFSR method

186. Self-test circuitry approach is based on1. linear feed back shift registers only2. linear feed back shift registers, exclusive-OR and clock system or gate3. clock system only4. enclusive OR gates only

187. The combination of LSSD scan path and linear feed back shift register is called1. self test circuitry2. signature analysis technique3. structured testbility4. built-in logic block observation

188. In the following which one is corrcet with respect to BILBO testing for control inputs C0=1, C1=1

1. linear shift mode2. signature analysis mode3. data latch4. reset mode

The control inputs 189. in BILBO testing the coresponding mode is

1. linear shift mode2. signature analysis mode3. datalatch4. reset mode

190. In the BILBO arrangements, when C0=0, C1=1 then the corresponding mode is1. linear shift mode2. signature analysis mode3. data latch4. reset mode

191. The following the mode when C0=1, and C1=0 in the BILBO arrangement1. linear shift mode2. signature analysis mode3. data latch4. reset mode

192. On chip testing is obtained by using1. self - test circuitry2. adhoc testability3. structured testability4. LSSD approach

193. Signature analysis techniques are1. on chip testing2. structured testing3. LSSD testing4. adhoc testability

194. The manufacturing cost is low by detecting the malfunctioning of chip at a level of1. wafer level

2. packaged-chip3. system level4. field

195. The tests that are usually carried after chip is manufactured are called1. functionality test2. design verification3. manufacturing test4. technology test

196. Generally memories are tested by1. self-test2. full serial scan3. parallel scan4. LFSR method

197. In order to reconfogure flip - flops appropriately, it is necessary to be able to include a double throw switch in the

1. simple scan path2. address path3. control singnal path4. data path

198. The test access port or TAP controller in a boundry - scan system level testing is a1. 16 - state FSM2. 8 - state register3. 8 - state interface pins4. 16 - state NAND gates

199. The following path is used to reduce testing time in the LSSD1. simple scan path2. parallel path3. single path4. complex path

200. The test access port or TAP controller in a boundary - scan system - level testing has connections of

1. one single bit2. one multiple bits3. four or five single bit4. one or two multiple bits

201. The insuction register (IR) in boundry-scan system level testing has to be at least1. one bit long2. two bit long3. there bit long4. four bit long

202. Subsystems can be checked out individually by providing the appropriate1. additional inlet/outlet pads2. additional circuit nodes3. additional links4. It is not possible to check

203. The essence of the LSSD approach is to design all circuity in a1. transistor to transistor2. transistor to registor3. register to register4. register to transistor

204. In the structured testing technique, LSSD means

1. level scan sensistive default2. level simple scan design3. level scan simple default4. level sensitive scan design

205. In the LSSD approach the resisters behaves like a1. shift register in operation mode and latch in testmode2. shift register in test mode and latch in operation mode3. shift registers in both test and operation mode4. latch in both test and operation mode

206. The IEEE 1149 boundary scan is used for1. chip level testing2. design test3. system level testing4. circuit level testing

207. To increase the immunity to open - circuit faults usually involve incorporating1. misaligned2. connection redundancy3. nature of defects4. frequency of defects

208. To find the bridging faults, the following popular testing method is used1. scan testing2. I L A3. I D D Q4. self testing

209. The layout is tested by using1. Design rule checker2. simulator3. PROBE4. BILBO

210. The layout modifications improves the performance1. typically 10 % - 20 %2. greatethan 50 %3. typically 100 %4. typically 30 % to 50 %

211. NET is used to1. verify its compliance with the design rules2. extract the circuit from the mask layout

test for the number of 3. contacts4. simulate the leaf cell

212. PROBE is used to1. verify the design rules2. extract the circuit from the mask layout3. layout testing4. simulate the cell

213. To reduce parasitics, the changes are made in1. circuit2. transstor size3. layout4. logic

214. The steady state response to any allowed input state change is independent of the circuit and wire delays within the system then this logic system is called

1. level-sensitive2. finite state machine3. stable - state4. combinational logic circuit

215. Long counters are tested by1. scan - based approaches2. self test3. buit - in testing4. ad-hoc testing

216. The following type of a fault should not distrub the functionality of the circuit1. Delay fault2. bridge fault3. open circuit4. stuck at faults