ax8052f143cn - soc超低功耗rf微控制器(适用于 27 - 1050 mhz...

© Semiconductor Components Industries, LLC, 2015

August, 2017 − Rev. 51 Publication Order Number:

AX8052F143CN/D

AX8052F143

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♦��TX �(868 MHz)7.5 mA (0 dBm) 16 mA (10 dBm) 48 mA (16 dBm)

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−138 dBm (0.1 kbps), 868 MHz, PSK−130 dBm (1 kbps), 868 MHz, PSK−120 dBm (10 kbps), 868 MHz, PSK−109 dBm (100 kbps), 868 MHz, PSK−108 dBm (125 kbps), 868 MHz, PSK

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AX8052F143

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Figure 1. Functional Block Diagram of the AX8052F143

AX8052F143

ANTP

ANTN

IF Filter and

AGC PGAs

AGC

Crystal

Oscillator

typ. 16MHz

Communication Controller &

Radio Interface Controller

LNA

Divider

ADCDigital IF

Channel

Filter

PA

diff

De-

modulator

Fo

rwa

rd e

rro

r

co

rre

ctio

n

Modulator

Mixer

CLK16P

CLK16N

RSSI

Radio configuration

VDD_ANAVoltage

Regulator

POR, references

256

DebugInterface

Axsem8052

SystemController

FLASH64k

AESCrypto Engine

ADCComparators

SPImaster/slave

UART 1

UART 0

InputCapture 1

InputCapture 0

OutputCompare 1

OutputCompare0

TimerCounter 2

TimerCounter 1

TimerCounter 0

GPIO

PA0

PA1

PA2

PA3

PA4

PA5

RESET_N

GND

VDD_IO

8k

RA

M

PC0

PC1

PC2

PC3

PC4

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

I/O Multiplexer

DBG_EN

IRQ

Re

q

Reset, Clocks, Power

I-B

us

P-B

us

X-B

us

SFR

-Bu

s

DMAController

DM

A R

eq

SYSCLK

Temp Sensor

wakeuposcillator

RC Oscillator

tuning forkcrystal

oscillator

wakeuptimer 2x

RF FrequencyGeneration

Subsystem

PAse

FOUT

ANTP1

L1

L2

FILT

VDD_IO

FXTAL

low poweroscillator

640 Hz/ 10 kHz

Wake on Radio

En

co

de

r

Fra

min

g

FIF

O/p

ac

ke

t b

uff

er

Ra

dio

co

ntr

olle

rtim

ing

an

d p

ac

ke

th

an

dlin

g


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Table 1. PIN FUNCTION DESCRIPTIONS

Symbol Pin(s) Type Description

VDD_ANA 1 P Analog power output, decouple to neighboring GND

GND 2 P Ground, decouple to neighboring VDD_ANA

ANTP 3 A Differential antenna input/output

ANTN 4 A Differential antenna input/output

ANTP1 5 A Single−ended antenna output

GND 6 P Ground, decouple to neighboring VDD_ANA

VDD_ANA 7 P Analog power output, decouple to neighboring GND

GND 8 P Ground

FILT 9 A Optional synthesizer filter

L2 10 A Optional synthesizer inductor

L1 11 A Optional synthesizer inductor

SYSCLK 12 I/O/PU System clock output

PC4 13 I/O/PU General purpose IO





PB0 18 I/O/PU General purpose IO






PB6 24 I/O/PU General purpose IO, DBG_DATA

PB7 25 I/O/PU General purpose IO, DBG_CLK

DBG_EN 26 I/PD In−circuit debugger enable

RESET_N 27 I/PU Optional reset pin. If this pin is not used it must be connected to VDD_IO

GND 28 P Ground

VDD_IO 29 P Unregulated power supply

PA0 30 I/O/A/PU General purpose IO






VDD_IO 36 P Unregulated power supply

TST1 37 A Must be connected to GND

TST2 38 A Must be connected to GND

CLK16N 39 A Crystal oscillator input/output (RF reference oscillator)

CLK16P 40 A Crystal oscillator input/output (RF reference oscillator)

GND Center pad P Ground on center pad of QFN, must be connected


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Table 2. ALTERNATE PIN FUNCTIONS

GPIO Alternate Functions

PA0 T0OUT IC1 ADC0

PA1 T0CLK OC1 ADC1

PA2 OC0 U1RX ADC2 COMPI00

PA3 T1OUT ADC3 LPXTALP

PA4 T1CLK COMPO0 ADC4 LPXTALN

PA5 IC0 U1TX ADC5 COMPI10

PB0 U1TX IC1 EXTIRQ0

PB1 U1RX OC1

PB2 IC0 T2OUT PWRAMP

PB3 OC0 T2CLK EXTIRQ1 DSWAKE ANTSEL

PB4 U0TX T1CLK

PB5 U0RX T1OUT

PB6 DBG_DATA

PB7 DBG_CLK

PC0 SSEL T0OUT EXTIRQ0

PC1 SSCK T0CLK COMPO1

PC2 SMOSI U0TX

PC3 SMISO U0RX COMPO0

PC4 COMPO1 ADCTRIG EXTIRQ1


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Figure 2. Pinout Drawing (Top View)

AX8052F143

QFN40

8

7

6

5

4

3

2

1

9 10 11 12 13 14 15 16 17 18 19 20

21

22

23

24

25

26

27

28

40 39 38 37 36 35 34 33 32 31 30 29

VDD_ANA

ANTP

GND

ANTN

ANTP1

GND

GND

VDD_ANA

FIL

T L2 L1

SY

SC

LK

EX

TIR

Q1/

AD

CT

RIG

/CO

MP

O1/

PC

4

CO

MP

O0/

U0R

X/S

MIS

O/P

C3

U0T

X/S

MO

SI/P

C2

CO

MP

O1/

T0C

LK/S

SC

K/P

C1

EX

TIR

Q0/

T0O

UT

/SS

EL/

PC

0

EX

TIR

Q0/

IC1/

U1T

X/P

B0

OC

1/U

1RX

/PB

1

PW

RA

MP

/T2O

UT

/IC0/

PB

2

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5/A

DC

5/IC

0/U

1TX

/CO

MP

I10

PA

4/A

DC

4/T

1CLK

/CO

MP

O0/

LPX

TALN

PA

3/A

DC

3/T

1OU

T/L

PX

TALP

PA

2/A

DC

2/O

C0/

U1R

X/C

OM

PI0

0

PA

1/A

DC

1/T

0CLK

/OC

1

PA

0/A

DC

0/T

0OU

T/IC

1

VD

D_I

O

GND

RESET_N

DBG_EN

PB7/DBG_CLK

PB6/DBG_DATA

PB5/U0RX/T1OUT

PB4/U0TX/T1CLK

PB3/OC0/T2CLK/EXTIRQ1/DSWAKE/ANTSEL


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Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol Description Condition Min Max Units

VDD_IO Supply voltage −0.5 5.5 V

IDD Supply current 200 mA

Ptot Total power consumption 800 mW

Pi Absolute maximum input power at receiver input ANTP and ANTNpins in RX mode

10 dBm

II1 DC current into any pin except ANTP, ANTN, ANTP1 −10 10 mA

II2 DC current into pins ANTP, ANTN, ANTP1 −100 100 mA

IO Output Current 40 mA

Via Input voltage ANTP, ANTN, ANTP1 pins −0.5 5.5 V

Input voltage digital pins −0.5 5.5 V

Ves Electrostatic handling HBM −2000 2000 V

Tamb Operating temperature −40 85 °C

Tstg Storage temperature −65 150 °C

Tj Junction Temperature 150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.(��) �� ，��。��，�� ，�� !��，"#�$%。1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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Table 4. SUPPLIES

Sym Description Condition Min Typ Max Units

TAMB Operational ambient temperature −40 27 85 °C

VDDIO I/O and voltage regulator supply voltage 1.8 3.0 3.6 V

VDDIO_R1 I/O voltage ramp for reset activation; Note 1

Ramp starts at VDD_IO ≤ 0.1 V 0.1 V/ms

VDDIO_R2 I/O voltage ramp for reset activation; Note 1

Ramp starts at 0.1 V < VDD_IO < 0.7 V 3.3 V/ms

VBOUT Brown−out threshold Note 2 1.3 V

IDS Deep Sleep current 100 nA

ISL256P Sleep current, 256 Bytes RAM retained Wakeup from dedicated pin 500 nA

ISL256 Sleep current, 256 Bytes RAM retained Wakeup Timer running at 640 Hz 900 nA

ISL4K Sleep current, 4.25 kBytes RAM retained Wakeup Timer running at 640 Hz 1.5 �A

ISL8K Sleep current, 8.25 kBytes RAM retained Wakeup Timer running at 640 Hz 2.2 �A

IRX Current consumption RXRF frequency generation subsystem:Internal VCO and internal loop−fiter

868 MHz, datarate 6 kbps 9.5 mA

169 MHz, datarate 6 kbps 6.5

868 MHz, datarate 100 kbps 11

169 MHz, datarate 100 kbps 7.5

ITX−DIFF Current consumption TX differential

868 MHz, 16 dBm, FSK, Note 3RF frequency generation subsystem:Internal VCO and internal loop−filterAntenna configuration:Differential PA, internal RX/TX switch

48 mA


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Table 4. SUPPLIES

UnitsMaxTypMinConditionDescriptionSym

IRX−SE Current consumption TXsingle ended

868 MHz, 0 dBm, FSK, Note 3RF frequency generation subsystem:Internal VCO and internal loop−filterAntenna configuration:Single ended PA, external RX/TXswitching

7.5 mA

IMCU Microcontroller running power consump-tion

All peripherals disabled 150 �A/MHz

IVSUP Voltage supervisor Run and standby mode 85 �A

ILPXTAL Crystal oscillator current(RF reference oscillator)

16 MHz 160 �A

ILFXTAL Low frequency crystal oscillator current 32 kHz 700 nA

IRCOSC Internal oscillator current 20 MHz 210 �A

ILPOSC Internal Low Power Oscillator current 10 kHz 650 nA

640 Hz 210 nA

IADC ADC current 311 kSample/s, DMA 5 MHz 1.1 mA

IWOR Typical wake−on−radio duty cycle current 1s, 100 kbps 6 �A

1. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended for AX8052F143−1 and AX8052F143−2, see the AX8052Application Note: Power On Reset

2. Digital circuitry is functional down to typically 1 V.3. Measured with optimized matching networks.

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(Ploss = 1 dB、PAefficiency = 0.5、Ioffset = 6 mA @ 868MHz�iIoffset = 3.5 mA (169 MHz)。

Table 5. CURRENT CONSUMPTION VS. OUTPUTPOWER

Pout [dBm]

Itxcalc [mA]

868 MHz 169 MHz

0 7.5 4.5

1 7.9 4.9

2 8.4 5.4

3 9.0 6.0

4 9.8 6.8

5 10.8 7.8

6 12.1 9.1

7 13.7 10.7

8 15.7 12.7

9 18.2 15.2

10 21.3 18.3

11 25.3 22.3

12 30.3 27.3

13 36.7 33.7

14 44.6 41.6

15 54.6 51.6

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Table 6. LOGIC

Symbol Description Condition Min Typ Max Units

Digital Inputs

VT+ Schmitt trigger low to high threshold point VDD_IO = 3.3 V 1.55 V

VT− Schmitt trigger high to low threshold point 1.25 V

VIL Input voltage, low 0.8 V

VIH Input voltage, high 2.0 V

VIPA Input voltage range, Port A −0.5 VDD_IO V

VIPBC Input voltage range, Ports B, C −0.5 5.5 V

IL Input leakage current −10 10 �A

RPU Programmable Pull−Up Resistance 65 k�

Digital Outputs

IOH Output Current, highPorts PA, PB and PC

VOH = 2.4 V 8 mA

IOL Output Current, lowPorts PA, PB and PC

VOL = 0.4 V 8 mA

IOH Output Current, highPin SYSCLK

VOH = 2.4 V 4 mA

IOL Output Current, lowPin SYSCLK

VOL = 0.4 V 4 mA

IOZ Tri−state output leakage current −10 10 �A

AC

Table 7. CRYSTAL OSCILLATOR (RF REFERENCE OSCILLATOR)


fXTAL Crystal or frequency Note 1, 2, 3 10 16 50 MHz

gmosc Oscillator transconductance range Self−regulated see note 4 0.2 20 mS

Cosc Programmable tuning capacitors at pinsCLK16N and CLK16P

AX5043_XTALCAP = 0x00default

3 pF

AX5043_XTALCAP = 0x01 8.5 pF

AX5043_XTALCAP = 0xFF 40 pF

Cosc−lsb Programmable tuning capacitors, incre-ment per LSB of AX5043_XTALCAP

AX5043_XTALCAP = 0x01– 0xFF

0.5 pF

fext External clock input (TCXO) Note 2, 3, 5 10 16 50 MHz

RINosc Input DC impedance 10 k�

NDIVSYSCLK Divider ratio fSYSCLK = FXTAL/ NDIVSYSCLK 20 24 210

1. Tolerances and start−up times depend on the crystal used. Depending on the RF frequency and channel spacing the IC must be calibratedto the exact crystal frequency using the readings of the register AX5043_TRKFREQ.

2. The choice of crystal oscillator or TCXO frequency depends on the targeted regulatory regime for TX, see separate documentation onmeeting regulatory requirements.

3. To avoid spurious emission, the crystal or TCXO reference frequency should be chosen so that the RF carrier frequency is not an integermultiple of the crystal or TCXO frequency.

4. The oscillator transconductance is regulated for fastest start−up time during start−up and for lowest power curing steady state oscillation.This means that values depend on the crystal used.

5. If an external clock or TCXO is used, it should be input via an AC coupling at pin CLK16P with the oscillator powered up andAX5043_XTALCAP = 000000. For detailed TCXO network recommendations depending on the TCXO output swing refer to the AX5043Application Note: Use with a TCXO Reference Clock.


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Table 8. LOW−POWER OSCILLATOR (TRANSCEIVER WAKE ON RADIO CLOCK)


fosc−slow Oscillator frequency slow modeLPOSC FAST = 0 inAX5043_LPOSCCONFIG register

No calibration 480 640 800 Hz

Internal calibration vs. crystalclock has been performed

630 640 650

fosc−fast Oscillator frequency fast modeLPOSC FAST = 1 inAX5043_LPOSCCONFIG register

No calibration 7.6 10.2 12.8 kHz

Internal calibration vs. crystalclock has been performed

9.8 10.2 10.8

Table 9. RF FREQUENCY GENERATION SUBSYSTEM (SYNTHESIZER)


fREF Reference frequency The reference frequency must be chosenso that the RF carrier frequency is not aninteger multiple of the reference frequency

10 16 50 MHz

Dividers

NDIVref Reference divider ratio range Controlled directly with bits REFDIV in reg-ister AX5043_PLLVCODIV

20 23

NDIVm Main divider ratio range Controlled indirectly with registerAX5043_FREQ

4.5 66.5

NDIVRF RF divider range Controlled directly with bit RFDIV in regis-ter AX5043_ PLLVCODIV

1 2

Charge Pump

ICP Charge pump current Programmable in increments of 8.5 �A viaregister AX5043_PLLCPI

8.5 2168 �A

Internal VCO (VCOSEL = 0)

fRF RF frequency range RFDIV = 1 400 525 MHz

RFDIV = 0 800 1050

fstep RF frequency step RFDIV = 1fREF = 16.000000 MHz

0.98 Hz

BW Synthesizer loop bandwidth The synthesizer loop bandwidth an start−up time can be programmed with the reg-isters AX5043_PLLLOOP andAX5043_PLLCPI.For recommendations see the AX5043Programming Manual, the AX−RadioLabsoftware and AX5043 Application Noteson compliance with regulatory regimes.

50 500 kHz

Tstart Synthesizer start−up time if crystaloscillator and reference are running

5 25 �s

PN868 Synthesizer phase noise 868 MHzfREF = 48 MHz

10 kHz from carrier −95 dBc/Hz

1 MHz from carrier −120

PN433 Synthesizer phase noise 433 MHzfREF = 48 MHz



VCO with external inductors (VCOSEL = 1, VCO2INT = 1)

fRFrng_lo RF frequency rangeFor choice of Lext values as well asVCO gains see Figure 3 and Figure 4

RFDIV = 1 27 262 MHz

fRFrng_hi RFDIV = 0 54 525

PN169 Synthesizer phase noise 169 MHzLext=47 nH (wire wound 0603)AX5043_RFDIV = 0, fREF= 16 MHzNote: phase noises can be im-proved with higher fREF




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Table 9. RF FREQUENCY GENERATION SUBSYSTEM (SYNTHESIZER)

UnitsMaxTypMinConditionDescriptionSymbol

External VCO (VCOSEL = 1, VCO2INT = 0)

fRF RF frequency range fully externalVCO

Note: The external VCO frequency needsto be 2 x fRF

27 1000 MHz

Vamp Differential input amplitude at L1, L2terminals

0.7 V

VinL Input voltage levels at L1, L2 termi-nals

0 1.8 V

Vctrl Control voltage range Available at FILT in external loop filtermode

0 1.8 V

Figure 3. VCO with External Inductors: Typical Frequency vs. Lext


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Figure 4. VCO with External Inductors: Typical KVCO vs. Lext

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Table 10.

Lext [nH]

Freq [MHz]

RFDIV = 0

Freq [MHz]

RFDIV = 1 PLL Range

8.2 482 241 0

8.2 437 219 15

10 432 216 0

10 390 195 15

12 415 208 0

12 377 189 15

15 380 190 0

15 345 173 15

18 345 173 0

18 313 157 15

22 308 154 0

22 280 140 14

27 285 143 0

27 258 129 15

33 260 130 0

33 235 118 15

39 245 123 0

39 223 112 14

47 212 106 0

47 194 97 14

56 201 101 0

56 182 91 15

68 178 89 0

68 161 81 15

82 160 80 1

82 146 73 14

100 149 75 1

100 136 68 14

120 136 68 0

120 124 62 14

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Table 11. TRANSMITTER


SBR Signal bit rate 0.1 125 kbps

PTX Transmitter power @ 868 MHz Differential PA, 50 � singleended measurement at anSMA connector behind thematching network, Note 2

−10 16 dBm

Transmitter power @ 433 MHz −10 16

Transmitter power @ 169 MHz −10 16

PTXstep Programming step size output power Note 1 0.5 dB

dTXtemp Transmitter power variation vs. tempera-ture

−40°C to +85°CNote 2

± 0.5 dB

dTXVdd Transmitter power variation vs. VDD_IO 1.8 to 3.6 VNote 2

± 0.5 dB

Padj Adjacent channel powerGFSK BT = 0.5, 500 Hz deviation, 1.2 kbps, 25 kHz channel spacing, 10 kHz channel BW

868 MHz −44 dBc

433 MHz −51

PTX868−harm2 Emission @ 2nd harmonic 868 MHz, Note 2 −40 dBc

PTX868−harm3 Emission @ 3rd harmonic −60

PTX433−harm2 Emission @ 2nd harmonic 433 MHz, Note 2 −40 dBc

PTX433−harm3 Emission @ 3rd harmonic −40

1. Pout �AX5043_TXPWRCOEFFB

212�1� Pmax

2. 50 � single ended measurements at an SMA connector behind the matching network. For recommended matching networks see

Applications section.

Table 12. RECEIVER SENSITIVITIES The table lists typical input sensitivities (without FEC) in dBm at the SMA connector with the complete matching network for BER=10−3 at433 or 868 MHz.

Data rate[kbps]

FSKh = 0.66

FSKh = 1

FSKh = 2

FSKh = 4

FSKh = 5

FSKh = 8

FSKh = 16 PSK

0.1 Sensitivity [dBm] −135 −134.5 −132.5 −133 −133.5 −133 −132.5 −138

RX Bandwidth [kHz] 0.2 0.2 0.3 0.5 0.6 0.9 2.1 0.2

Deviation [kHz] 0.033 0.05 0.1 0.2 0.25 0.4 0.8

1 Sensitivity [dBm] −126 −125 −123 −123.5 −124 −123.5 −122.5 −130

RX Bandwidth [kHz] 1.5 2 3 6 7 11 21 1

Deviation [kHz] 0.33 0.5 1 2 2.5 4 8

10 Sensitivity [dBm] −117 −116 −113 −114 −113.5 −113 −120

RX Bandwidth [kHz] 15 20 30 50 60 110 10

Deviation [kHz] 3.3 5 10 20 25 40

100 Sensitivity [dBm] −107 −105.5 −109

RX Bandwidth [kHz] 150 200 100

Deviation [kHz] 33 50

125 Sensitivity [dBm] −105 −104 −108

RX Bandwidth [kHz] 187.5 200 125

Deviation [kHz] 42.3 62.5

1. Sensitivities are equivalent for 1010 data streams and PN9 whitened data streams.2. RX bandwidths < 0.9 kHz cannot be achieved with an 48 MHz TCXO. A 16 MHz TCXO was used for all measurements at 0.1 kbps.


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Table 13. RECEIVER


SBR Signal bit rate 0.1 125 kbps

ISBER868 Input sensitivity at BER = 10−3

for 868 MHz operation,continuous data,without FEC

FSK, h = 0.5, 100 kbps −106 dBm

FSK, h = 0.5, 10 kbps −116

FSK, 500 Hz deviation, 1.2 kbps −126

PSK, 100 kbps −109

PSK, 10 kbps −120

PSK, 1 kbps −130

ISBER868FEC Input sensitivity at BER = 10−3, for 868 MHz oper-ation, continuous data,with FEC

FSK, h = 0.5, 50 kbps −111 dBm

FSK, h = 0.5, 5 kbps −122

FSK, 0.1 kbps −137

ISPER868 Input sensitivity at PER = 1%, for 868 MHz opera-tion, 144 bit packet data, withoutFEC

FSK, h = 0.5, 100 kbps −103 dBm

FSK, h = 0.5, 10 kbps −115

FSK, 500 Hz deviation, 1.2 kbps −125

ISWOR868 Input sensitivity at PER = 1% for 868 MHz opera-tion, WOR−mode, without FEC

FSK, h= 0.5, 100 kpbs −102 dBm

IL Maximum input level Full selectivity 0 dBm

FSK, reduced selectivity 10

CP1dB Input referred compression point 2 tones separated by 100 kHz −35 dBm

RSSIR RSSI control range FSK, 500 Hz deviation,1.2 kbps

−126 −46 dB

RSSIS1 RSSI step size Before digital channel filter; calculatedfrom register AX5043_AGCCOUNTER

0.625 dB

RSSIS2 RSSI step size Behind digital channel filter; calculatedfrom registers AX5043_AGCCOUNTER,AX5043_TRKAMPL

0.1 dB

RSSIS3 RSSI step size Behind digital channel filter; reading reg-ister AX5043_RSSI

1 dB

SEL868 Adjacent channel suppression 25 kHz channels , Note 1 45 dB

100 kHz channels, Note 1 47

BLK868 Blocking at ± 10 MHz offset Note 2 78 dB

RAFC AFC pull−in range The AFC pull−in range can be pro-grammed with the AX5043_MAXR-FOFFSET registers.The AFC response time can be pro-grammed with the AX5043_FRE-QGAIND register.

± 15 %

RDROFF Bitrate offset pull−in range The bitrate pull−in range can be pro-grammed with theAX5043_MAXDROFFSET registers.

± 10 %

1. Interferer/Channel @ BER = 10−3, channel level is +3 dB above the typical sensitivity, the interfering signal is CW; channel signal ismodulated with shaping

2. Channel/Blocker @ BER = 10−3, channel level is +3 dB above the typical sensitivity, the blocker signal is CW; channel signal is modulatedwith shaping


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Table 14. RECEIVER AND TRANSMITTER SETTLING PHASES


Txtal XTAL settling time Powermodes:POWERDOWN to STANDBYNote that Txtal depends on the specificcrystal used.

0.5 ms

Tsynth Synthesizer settling time Powermodes:STANDBY to SYNTHTX or SYNTHRX

40 �s

Ttx TX settling time Powermodes:SYNTHTX to FULLTXTtx is the time used for power ramping, thiscan be programmed to be 1 x tbit, 2 x tbit, 4 x tbit or 8 x tbit.Note 1

0 1 x tbit 8 x tbit �s

Trx_init RX initialization time 150 �s

Trx_rssi RX RSSI acquisition time(after Trx_init)

Powermodes:SYNTHRX to FULLRX

Modulation (G)FSKNote 1

80 + 3 x tbit

�s

Trx_preambl-

e

RX signal acquisition time tovalid data RX at full sensitivi-ty/selectivity(after Trx_init)

9 x tbit

1. tbit depends on the datarate, e.g. for 10 kbps tbit = 100 �s

Table 15. OVERALL STATE TRANSITION TIMES


Ttx_on TX startup time Powermodes:STANDBY to FULLTXNote 1

40 40 + 1 x tbit �s

Trx_on RX startup time Powermodes:STANDBY to FULLRX

190 �s

Trx_rssi RX startup time to valid RSSI Powermodes:STANDBY to FULLRX

Modulation (G)FSKNote 1

270 + 3 x tbit

�s

Trx_data RX startup time to valid data at fullsensitivity/selectivity

190 + 9 x tbit

�s

Trxtx RX to TX switching Powermodes:FULLRX to FULLTX

62 �s

Ttxrx TX to RX switching(to preamble start)

Powermodes:FULLTX to FULLRX

200

Thop Frequency hop Switch between frequency de-fined in register AX5043_FRE-QA and AX5043_FREQB

30 �s

1. tbit depends on the datarate, e.g. for 10 kbps tbit = 100 �s


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Table 16. LOW FREQUENCY CRYSTAL OSCILLATOR


fLPXTAL Crystal frequency 32 150 kHz

gmlpxosc Transconductance oscillator LPXOSCGM = 00110 3.5 �s

LPXOSCGM = 01000 4.6



RINlpxosc Input DC impedance 10 M�

Table 17. INTERNAL LOW POWER OSCILLATOR


fLPOSC Oscillation Frequency LPOSCFAST = 0Factory calibration applied.Over the full temperature andvoltage range

630 640 650 Hz

LPOSCFAST = 1Factory calibration appliedOver the full temperature andvoltage range

10.08 10.24 10.39 kHz

Table 18. INTERNAL RC OSCILLATOR


fLFRCPOSC Oscillation Frequency Factory calibration applied.Over the full temperature andvoltage range

19.8 20 20.2 MHz

Table 19. MICROCONTROLLER


TSYSCLKL SYSCLK Low 27 ns

TSYSCLKH SYSCLK High 21 ns

TSYSCLKP SYSCLK Period 47 ns

TFLWR FLASH Write Time 2 Bytes 20 �s

TFLPE FLASH Page Erase 1 kBytes 2 ms

TFLE FLASH Secure Erase 64 kBytes 10 ms

TFLEND FLASH Endurance: Erase Cycles 10 000 100 000 Cycles

TFLRETroom FLASH Data Retention 25°CSee Figure 5 for the lower limitset by the memory qualification

100 Years

TFLREThot 85°CSee Figure 5 for the lower limitset by the memory qualification

10


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Figure 5. FLASH Memory Qualification Limit for Data Retention after 10k Erase Cycles

10

100

1000

10000

100000

15 25 35 45 55 65 75 85Temperature [�C]

Dat

a re

ten

tio

n t

ime

[yea

rs]

Table 20. ADC / COMPARATOR / TEMPERATURE SENSOR


ADCSR ADC sampling rate GPADC mode 30 500 kHz

ADCSR_T ADC sampling rate temperature sensor mode 10 15.6 30 kHz

ADCRES ADC resolution 10 Bits

VADCREF ADC reference voltage & comparator internalreference voltage

0.95 1 1.05 V

ZADC00 Input capacitance 2.5 pF

DNL Differential nonlinearity ± 1 LSB

INL Integral nonlinearity ± 1 LSB

OFF Offset 3 LSB

GAIN_ERR Gain error 0.8 %

ADC in Differential Mode

VABS_DIFF Absolute voltages & common mode voltage indifferential mode at each input

0 VDD_IO V

VFS_DIFF01 Full swing input for differential signals Gain x1 −500 500 mV

VFS_DIFF10 Gain x10 −50 50 mV

ADC in Single Ended Mode

VMID_SE Mid code input voltage in single ended mode 0.5 V

VIN_SE00 Input voltage in single ended mode 0 VDD_IO V

VFS_SE01 Full swing input for single ended signals Gain x1 0 1 V

Comparators

VCOMP_ABS Comparator absolute input voltage 0 VDD_IO V

VCOMP_COM Comparator input common mode 0 VDD_IO −0.8

V

VCOMPOFF Comparator input offset voltage 20 mV

Temperature Sensor

TRNG Temperature range −40 85 °C

TRES Temperature resolution 0.1607 °C/LSB

TERR_CAL Temperature error Factory calibrationapplied

−2 2 °C


AX8052F143

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Figure 6. AX8052 Memory Architecture

Arbiter

XRAM

0000−0FFF

Arbiter

XRAM

1000−1FFF

Arbiter

X Registers

4000−7FFF

Arbiter

SFR Registers

80−FF

Arbiter

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00−FF

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FLASH

0000−FFFF

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Prefetch

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Figure 7. AX8052 Memory Architecture

XRAM

FLASH

0000−007F

0080−00FF

0100−1FFF

2000−207F

2080−3F7F

3F80−3FFF

4000−4FFF

5000−5FFF

6000−7FFF

8000−FBFF

FC00−FFFF

Address

Calibration Data

IRAMIRAM

P (Code) Space X Space

I (internal) Space

direct access indirect access

SFR

IRAM

SFR

RREG

RREG (nb)

XREG

FLASH

Calibration Data


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Table 21. POWER MANAGEMENT

PCONregister Name Description

00 RUNNING The microcontroller and all peripherals are running. Current consumption depends on the system clockfrequency and the enabled peripherals and their clock frequency.

01 STANDBY The microcontroller is stopped. All register and memory contents are retained. All peripherals continue tofunction normally. Current consumption is determined by the enabled peripherals. STANDBY is exitedwhen any of the enabled interrupts become active.

10 SLEEP The microcontroller and its peripherals, except GPIO and the system controller, are shut down. Their regis-ter settings are lost. The internal RAM is retained. The external RAM is split into two 4 kByte blocks. Soft-ware can determine individually for both blocks whether contents of that block are to be retained or lost.SLEEP can be exited by any of the enabled GPIO or system controller interrupts. For most applicationsthis will be a GPIO or wakeup timer interrupt.

11 DEEPSLEEP The microcontroller, all peripherals and the transceiver are shut down. Only 4 bytes of scratch RAM areretained. DEEPSLEEP can only be exited by tying the PB3 pin low.


AX8052F143

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Figure 8. Clock System Diagram

LPOSCCalib

FRCOSCCalib

Wakeup

Timer

WDT

Clock

Monitor

Prescaler÷1,2,4,...

FRCOSC

XOSC

LPXOSC

LPOSC

Interrupt

Internal Reset

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ch F

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Clo

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witc

h

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AX8052F143

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Figure 9. ADC Block Diagram

TemperatureSensor

ADC Core

Clock Trigger

Gain Ref

VREF

1 V

VDDIO

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PPP

NNN

FR

CO

SC

LPO

SC

XO

SC

LPX

OS

C

SY

SC

LK

Sys

tem

Clo

ck

One Shot

Free Running

Timer 0

Timer 1

Timer 2

PC4

ADC Result

ACOMP1REF

ACOMP1ST/PA7/PC1ACOMP1IN

ACOMP1INV

ACOMP0IN

ACOMP0REFACOMP0INV

ACOMP0ST/PA4/PC3

System Clock

ADCCONV

AD

CC

LKS

RC

x 0.

1, x

1, x

10

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scal

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SYSCLK-R�"ÈÆÓ�)G�M$��A��RFp��y。�A��1�2048。R�A�

�A�#>1�lm，å�#�50%。AX5043_PINCFG1¤��SYSCLK[3:0] ��)GA��A�#。

�Ä�SYSCLK�"。

,�-.(POR)�RESET_N��

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7 ©。R�1�¸ª�\，��S�7 �。

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}1�0¿$AX5043_PWRMODE¤��RST ，»�}@0�7 。

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Figure 10. Port Pin Schematic

VDDIO

PORTx.y

DIRx.y

Special Function

PALTx.y

PINx read clock

PINx.y

Interrupt

INTCHGx.y

ANALOGx.y

65 k�

§10st�GPIOcd。DIR¤�� M�S -

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AX8052F143

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�Zlm!，PORT¤�� }�MS -R84

h。

]¸�G��$，PORT¤�� }�Mz2�(1)KzÄ�(0)�zY。�$!�f,gh0�g8。

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��。INTCHG¤�� 2��¯。-R¤��

Ü©�S -R�h。]¸2�“�t��¯”，5-R¤��7'7 �¯。

PWRAMP � ANTSEL]¸}PALTRADIO )�6、}DIRB )�2，PB

2��PWRAMP��}��。]¸}PALTRADIO )�7、}DIRB )�3，PB3��ANTSEL��}��。]¸H<-R)��Yç，��<²Q

D�DIRB ，vA}AX5043_PINFUNCPWRAMPHAX5043_PINFUNCANTSEL)�Z。


AX8052F143

www.onsemi.cn26

/0�

@0� ©��?~¤��，vH<¤��}

�©E��X$5�&。@0� ©(q�

/�4�×10 FIFO。�45FIFOèÕ�'(��)�¯��，H�t~��DMA��，JXRAM#

@0�FIFO1&��$5。

RF�� 1!"

RF�'�0Û��T��OPF�NF�，H

�Fâ�Ô<�33��p��'，�"|o�RF�'。NF��591 Hz��'A0'，�

i5�–�50�μs�B�PM�&，!��)G(:j;“ACg8”�A)。B�PM�&1éÖB�24�B�D%RX/TX，�v59��)�。

R�!@×+，RF�'}j2�ØN�，R�0E

×+，}j2��'J=�。

�'�<)G�o� A�'。

�)GNF��Q，��!�Z�l：

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Q|êsÙ A��300 kHz�1 MHz��D

YZ

3.�M�Q��$5�'。R�FSK�MSK�

�，2¢NF��Q�<#$5�'�¾。

VCOi�VCO�}ÚÛ��QA��0��

�%��"�'。o�'��0E�!@×+。�J

AX5043_FREQ¤��1 Hz�L')Go�'。R

�433 MHzAO×+，�<)GAX5043_PLLVCODIV¤��RFDIV 。

OPF�VCOk1��J800 – 1050 MHz�400 –520 MHz��'��。�?J��-RL1�L21&��Ã�S�(，�} A�'��®H�

54 – 525 MHz�27 – 262 MHz。��$o �，�<

}AX5043_PLLVCODIV¤��VCO2INT �

VCOSEL �<)G��。

oS，K�}AX5043_PLLVCODIV¤��

VCO2INT )G�0、}VCOSEL )G�1，��

��OPS�VCO。�<J�� L1 L2��

��!��RF��"#�$%��。��!"� �

��，&'�()!FILT*��VCO#$�+。%��)!��+",!0 – 1.8 V。&�-#./��01�$%��23：4�567&VCO�89:&�;�7&VCO�，<'()*=>?+,。

VCO�� AX8052F143!/F�74��，��P

RgM��'�0Û��)G，74)G~U�VCO��。�¡�<J�£��o��。�?)GAX5043_PLLRANGINGAHAX5043_PLLRANGINGB¤��RNG_START ，�24o��。D �5，0bt��?�ÇÜ。)GAX5043_PLLRANGINGA¤��RNG_START��AX5043_FREQA��'��，v)GAX5043_PLLRANGINGB¤��

RNG_START��AX5043_FREQB��'��。

RNGERR �t74��zë~U��。VCO74��OPF�VCO��S�(�VCO。

��

AX8052F143��QA��G#ÚÛ��b

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G，��?¤��AX5043_PLLLOOPHAX5043_PLLLOOPBOOST��FLT[1:0])G；ÚÛ��

¤��AX5043_PLLCPIHAX5043_PLLCPIBOOST��PLLCPI[7:0])G。NF��Q�^h�50 – 500 kHz，!��AX5043_PLLLOOPHAX5043_PLLLOOPBOOST)G，D@L°�u，:j;：“ACg8”�A。

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t�}¤��AX5043_PLLLOOPBOOST�AX5043_PLLCPIBOOST��)G��O�&(oO�&�)G)，�£ÌKVFAX5043_PLLLOOP�AX5043_PLLCPIo��59EB��7424。

}FLT[1:0] )G�00，�Ý?��QA�，>VCO��}�"�-RFILT�S��QA�。Þß��o�+ �，�59#��QA

��X��Q，s@}o�+ �#OPS�VCO�N��。


AX8052F143

www.onsemi.cn27

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Table 22. RF FREQUENCY GENERATION REGISTERS

Register Bits Purpose

AX5043_PLLLOOPAX5043_PLLLOOPBOOST

FLT[1:0] Synthesizer loop filter bandwidth and selection of external loop filter, recommended usage is toincrease the bandwidth for faster settling time, bandwidth increases of factor 2 and 5 are possi-ble.

AX5043_PLLCPIAX5043_PLLCPIBOOST

Synthesizer charge pump current, recommended usage is to decrease the bandwidth (andimprove the phase−noise) for low data−rate transmissions.

AX5043_PLLVCODIV REFDIV Sets the synthesizer reference divider ratio.

RFDIV Sets the synthesizer output divider ratio.

VCOSEL Selects either the internal or the external VCO

VCO2INT Selects either the internal VCO inductor or an external inductor between pins L1 and L2

AX5043_FREQA, AX5043_FREQB Programming of the carrier frequency

AX5043_PLLRANGINGA,AX5043_PLLRANGINGB

Initiate VCO auto−ranging and check results

RF��(ANTP/ANTN/ANTP1)AX8052F143!��Z�>�! �：

1. RX�TX��LA-RANTP�ANTN。

RX/TXD%J��m。Þß��o �，�

59E��"�'、E�:C'，�iw!7

!�°�>�。Ë:jª§15。2. RX��LA>�-RANTP�ANTN。TX��

�S>�-RANTP1。RX/TXD%JS��m。��RX/TXD%?@Hw!7!�GOFD%。Þß��o �，�59§18��I'��"��，s@}o �#§17��S��'J=��N��。

��#S�PA�N��，��-RPB2��S�RX/TXD%?@(§17)。��4>�!@�，

��-RPB3��S�>�?@(§19)。2�>�A�，��J^!@$5T�，}MWà

?>��!;!�E��y�'�>�。��t��

��MW}RSSIh¿$FIFO。>�A �OP

74�。

LNALNA�J=�7>��LARF�y，�}�y¤¯

�84I/QØN�。��S�_�ad}>�Yç�

�ICYç。�<J>�-R��DCj2�y�GND。

PAJTX ��，PA}�'�0Û��0��y�"

�LA>�SÛH�S>�-R。�?¤��

AX5043_MODECFGA��TXDIFF �TXSE !;>�SÛ。

PA��"�'�?¤��AX5043_TXPWRCOEFFB)G。

PA��$��00-ì.，�59��8'。

�"n'�MG(ÔJí)，�?¤��AX5043_MODECFGA��AMPLSHAPE !;o ��。PANI�� &��U��)G，�>��?¤��

AX5043_MODECFGA��SLOWRAMP ，)�1 – 8 �&。。

�"�'�i4AU��PA�ª�S�Yç。

23 IF 4#$��%&�

$�IF��QA��+��$�IF�y�$5 �。�<��N��/��i$5�

'。��U��}Ç¾:C'3�。

��QA��995 Hz�221 kHz��Q。

AXSEMRadioLab��q59E$8�o��¤

��)G。!b��oái¤��âm，Ll:

j;AX5043��¥¦。�¡J��£，�<�»

��¤��)G。


AX8052F143

www.onsemi.cn28

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Table 23. CHANNEL FILTER AND DEMODULATOR REGISTERS

Register Remarks

AX5043_DECIMATION This register programs the bandwidth of the digital channel filter.

AX5043_RXDATARATE2… AX5043_RX-DATARATE0

These registers specify the receiver bit rate, relative to the channel filter bandwidth.

AX5043_MAXDROFFSET2…AX5043_MAXDROFFSET0

These registers specify the maximum possible data rate offset

AX5043_MAXRFOFFSET2… AX5043_MAXR-FOFFSET0

These registers specify the maximum possible RF frequency offset

AX5043_TIMEGAIN, AX5043_DRGAIN These registers specify the aggressiveness of the receiver bit timing recovery. Moreaggressive settings allow the receiver to synchronize with shorter preambles, at theexpense of more timing jitter and thus a higher bit error rate at a given signal−to−noiseratio.

AX5043_MODULATION This register selects the modulation to be used by the transmitter and the receiver, i.e. whether ASK, FSK should be used.

AX5043_PHASEGAIN, AX5043_FREQGAINA,AX5043_FREQGAINB, AX5043_FREQGAINC,AX5043_FREQGAIND, AX5043_AMPLGAIN

These registers control the bandwidth of the phase, frequency offset and amplitudetracking loops.

AX5043_AGCGAIN This register controls the AGC (automatic gain control) loop slopes, and thus thespeed of gain adjustments. The faster the bit−rate, the faster the AGC loop should be.

AX5043_TXRATE These registers control the bit rate of the transmitter.

AX5043_FSKDEV These registers control the frequency deviation of the transmitter in FSK mode. Thereceiver does not explicitly need to know the frequency deviation, only the channelfilter bandwidth has to be set wide enough for the complete modulation to pass.

'(�

�� ÑX�`、+��1&。�!

;�?�!��% �。

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)5�FIFO]K=�$��F}$5AÑF$5T。Ñ

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�$5�²©�� Mm。²©�¢R''�iv

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MW5FIFOHC¤��HFIFO�$¤��，�UM

FIFOzë�2èð。

J�¯ ��，��EMPTY、NOT EMPTY、

FULL、NOTFULL��Ka��¯。�?çQ�

¯V�，»²�HèÕFIFO，�Uo�¯。

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DMA��$5。

J@0�FIFO�XRAM�f�1&。�?HZ�

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èã/�。AX8052F143K��ÍM$5T''�$5T �，��bt$5T''。

J$5T ��，�74qCRC。HDLC �zAX8052F143��2ÑX �。Jo ��，

AX8052F143��74$5TéM，��?ê$�8


AX8052F143

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=��òJ8=(CRC)�O>É$5T~U8(o��!)。

11： HDLC �z��K$5g��(HDLC、ISO 13239)�@。

!b��"�$5TÇ�。

Table 24. HDLC PACKET STRUCTURE

Flag Address Control Information FCS (Optional Flag)

8 bit 8 bit 8 or 16 bit Variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit

HDLC$5T�?��0x7E��ñ±�éM。

JAX8052F143�，cd��u�ÕM�。

X8=±�(FCS)�)G�CRC−CCITT、CRC−16HCRC−32。

!@�8=CRC，��FIFO>ÊÇ¸，CRC}i+�!@�$5。

��M−Bus ��$5TÇ�Lª!b。

11： ��M-Bus �z�EN13757−4��

Table 25. WIRELESS M−BUS PACKET STRUCTURE

Preamble L C M A FCSOptional Data Block

(optionally repeated with FCS) FCS

variable 8 bit 8 bit 8 bit 8 bit 16 bit 8 − 96 bit 16 bit

@�59HDLC��i�@��M−Bus�L°�u，:��AXSEM RadioLab��j;AX5043��¥¦。

#$��

JVW ��，AX8052F143��.$5TéM

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��，!@��!@�.$5，w J!@ ��

>? �Õ�� (��9G�)。>? 9G�£，}R~��Ü±�t。

9G�''�4�32#g。

RX AGC � RSSIAX8052F143!��!@��y�'�t�

(RSSI)：1.$�IF��QA�19�RSSI。��!@��Æ�IFQA��"{JADC�+��+

��。¤��AX5043_AGCCOUNTERT�AGC��h，��+RSSI。oRSSI�L'�

0.625 dB。)GRF�'�0Û��£，»��

�Dh。

2.$�IF��QA�1£�RSSI。¤��AX5043_RSSIT� �$�IF��QA�1£

�RSSI�h。oRSSI�L'�1 dB。3.�6'$�IF��QA�1£�RSSI。+��KJAX5043_TRK_AMPLITUDE¤��

�n'�u。�?ÇNAX5043_AGCCOUNTER�AX5043_TRK_AMPLITUDE¤��，��q�A0'(%�0.1 dB)RSSIh，)H'àá�

��<qëq。AXSEM RadioLab��q59E$8�o��¤��)G。

&��

450E�)G，��PA�0qZ�$：

Table 26. MODULATIONS

Modulation Bit = 0 Bit = 1 Main Lobe Bandwidth Max. Bitrate

ASK PA off PA on BW = BITRATE 125 kBit/s

FSK/MSK/GFSK/GMSK �f = −fdeviation �f = +fdeviation BW = (1 + h) ⋅BITRATE 125 kBit/s

PSK �� = 0° �� = 180° BW = BITRATE 125 kBit/s

h =��$。»KL##g'�#；fdeviation =0.5�h�#g'，AX8052F143��h<32��y。

ASK =nç{�FSK =�ç{�MSK=EÀ�ç{�；MSKzFSK��Zg l

m，~�h = 0.5，�o

fdeviation = 0.25�#g'；#FSKD#，MSK�%ó

z��XPô��。

PSK =Dç{�o��/�(4−FSKQS)��*��。��ÔJ

íAG�R3nMG。


AX8052F143

www.onsemi.cn30

K�PRõn��((G)FSK、(G)MSK)��3nMG，��PANÔ�N3。Wì2�3nMG。

�'MG��z�MG(FSK, MSK)H�äMG(GMSK, GFSK)，�!;BT = 0.3HBT = 0.5。

Table 27. 4−FSK MODULATION

Modulation DiBit = 00 DiBit = 01 DiBit = 11 DiBit = 10 Main Lobe Bandwidth Max. Bitrate

4−FSK �f = −3fdeviation �f = −fdeviation �f = +fdeviation �f = +3fdeviation BW = (1 + 3 h) ⋅BITRATE 125 kBit/s

4−FSK�'MGWì��MG。

*6�� (AFC)AX8052F143!/74�'./��，�eJRXQA��Q�./0E��'。AX8052F143��)��'./¤��AX5043_TRKRFFREQ，��}

!@��'# A�ybL。R�AFC��，��

�!T��q�'Vg：

�f �AX5043_TRKRFFREQ

232 fXTAL

PWRMODE 78�

AX8052F143@0�7��m��，��

��àá。�� ?PCON¤��，)AX5043_PWRMODE¤��}��@0��ï<�A。

Table 28. PWRMODE REGISTER

AX5043_PWRMODERegister Name Description

0000 POWERDOWN All digital and analog functions, except the register file, are disabled. The core supply volt-ages are switched off to conserve leakage power. Register contents are preserved.Access to the FIFO is not possible and the contents are not preserved. POWERDOWNmode is only entered once the FIFO is empty.

0001 DEEPSLEEP The transceiver is fully turned off. All digital and analog functions are disabled. All registercontents are lost.To leave DEEPSLEEP mode the pin SEL has to be pulled low. This will initiate startup andreset of the transceiver. Then the MISO line should be polled, as it will be held low duringinitialization and will rise to high at the end of the initialization, when the chip becomesready for operation.It is recommended to use the functions ax5043_enter_deepsleep() and ax5043_wake-up_deepsleep() provided in libmf

0101 STANDBY The crystal oscillator and the reference are powered on; receiver and transmitter are off.Register contents are preserved and accessible.Access to the FIFO is not possible and the contents are not preserved. STANDBY is onlyentered once the FIFO is empty.

0110 FIFO The reference is powered on. Register contents are preserved and accessible.Access to the FIFO is possible and the contents are preserved.

1000 SYNTHRX The synthesizer is running on the receive frequency. Transmitter and receiver are still off.This mode is used to let the synthesizer settle on the correct frequency for receive.

1001 FULLRX Synthesizer and receiver are running.

1011 WOR Receiver wakeup−on−radio mode.The mode the same as POWERDOWN, but the 640 Hz internal low power oscillator isrunning.

1100 SYNTHTX The synthesizer is running on the transmit frequency. Transmitter and receiver are still off.This mode is used to let the synthesizer settle on the correct frequency for transmit.

1101 FULLTX Synthesizer and transmitter are running. Do not switch into this mode before the synthesiz-er has completely settled on the transmit frequency (in SYNTHTX mode), otherwise spuri-ous spectral transmissions will occur.

Table 29. A TYPICAL AX5043_PWRMODE SEQUENCE FOR A TRANSMIT SESSION

Step PWRMODE Remarks

1 POWERDOWN

2 STANDBY The settling time is dominated by the crystal used, typical value 3ms.

3 FULLTX Data transmission

4 POWERDOWN


AX8052F143

www.onsemi.cn31

Table 30. A TYPICAL AX5043_PWRMODE SEQUENCE FOR A RECEIVE SESSION

Step PWRMODE [3:0] Remarks

1 POWERDOWN

2 STANDBY The settling time is dominated by the crystal used, typical value 3ms.

3 FULLRX Data reception

4 POWERDOWN

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�，��VDD_IO��PM��。$�-R�I/O{�VDD_IO。

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4!@H0E×+。�?AX5043_PWRMODE¤��)G�� ，'74OF�h)G。

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AX8052F143

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��4:

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�%��

Figure 11. Typical Application Diagram with Connection to the Debug Adapter

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4

GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F143

100pF1uF

DBG_EN

DBG_RT_N

GND

DBG_DATA

DBG_CLK

GND

DBG_VDD

Jumper JP1

1

2

3

4

5

6

7

8

RF reference XTAL

32 kHz XTAL

Debug adapterconnector

F*�JP1−1(]¸�2�?��(E=50mA)��ð�)}AX8052F143�ö�S|ñò!c。

]¸��，PB6�PB7��u��

84。]¸��，��5�PB6�PB7h��

��-RC.��)G。

PB3(u��84，��AX8052F143^"¿'�� 。ë�，�'�0�Yç。

�!;32 kHz<�，-RCLK16N�CLK16P�B�<�}�+RF RX/TX�p��'。Ã45<�$5

b�!;<�v �。J-RCLK16N�CLK16P，��；J-RPA3�PA4，��<7!S��。


AX8052F143

www.onsemi.cn33

&'()*�+�(868 / 433 MHz RX / TX��)，,-

.50 ��/�。

Figure 12. Structure of the Differential Antenna Interface for TX/RX Operation to 50 � Single−ended Equipment orAntenna

IC antennapins

LT1

LC1

LB1

CT1

CC1CM1

LT 2

LC2

CT2

CC2 CM2

CB2

LB2

CF

LF

CA CA

Optional filter stageto suppress TX

harmonics

50 � single−endedequipment or antenna

Table 31. TYPICAL COMPONENT VALUES

Frequency BandLC1,2[nH]

CC1,2[pF]

CT1,2[pF]

LT1,2[nH]

CM1[pF]

CM2[pF]

LB1,2[nH]

CB2[pF]

CF[pF]

optional

LF[nH]

optional

CA[pF]

optional

868 / 915 MHz 18 nc 2.7 18 6.2 3.6 12 2.7 nc 0 � nc

433 MHz 100 nc 4.3 43 11 5.6 27 5.1 nc 0 � nc

470 MHz 100 nc 3.9 33 4.7 nc 22 4.7 nc 0 � nc

169 MHz 150 10 10 120 12 nc 68 12 6.8 30 27

&'1�*�+�(868 / 915 / 433 MHz TX��)，,-

.50 ��/�

Figure 13. Structure of the Single−ended Antenna Interface for TX Operation to 50 � Single−ended Equipment orAntenna

IC AntennaPin LT

LC

CT

CC

CF1

LF1

CA1 CA2



Frequency Band LC [nH] CC [pF] CT [pF] LT [nH] CF1 [pF] LF1 [nH] CA1 [pF] CA2 [pF]

868 / 915 MHz 18 nc 2.7 18 3.6 2.2 3.6 nc

433 MHz 100 nc 4.3 43 6.8 4.7 5.6 nc


AX8052F143

www.onsemi.cn34

&'1�*�+�(169 MHz TX2��)，,-.

50 ��/�

Figure 14. Structure of the Single−ended Antenna Interface for TX Operation to 50 � Single−ended Equipment orAntenna

IC AntennaPin LT

LC

CT

CC

CF1

LF1

CA1


CA2

CF2

LF2

CA3


Frequency BandLC

[nH]CC[pF]

CT[pF]

LT[nH]

CF1[pF]

LF1[nH]

CF2[pF]

LF2[nH]

CA1[pF]

CA2[pF]

CA3[pF]

169 MHz 150 2.2 22 120 4.7 39 1.8 47 33 47 15

3�45*��TX/RX678�

Figure 15. Typical Application Diagram with Dipole Antenna and Internal TX/RX Switch

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4

GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F143


AX8052F143

www.onsemi.cn35

3�1�*��TX/RX678�

Figure 16. Typical Application Diagram with Single−ended Antenna and Internal TX/RX Switch

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4

GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F14350 �


AX8052F143

www.onsemi.cn36

3�9� :�PA�9�TX/RX678�

Figure 17. Typical Application Diagram with Single−ended Antenna, External PA and External Antenna Switch

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4

GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F143

PA

TX/RX switch

50 �


AX8052F143

www.onsemi.cn37

3�1�PA

Figure 18. Typical Application Diagram with Single−ended Antenna, Single−ended Internal PA,without RX/TX Switch

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4

GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F14350 �

11： @��o�G�L°�u�s@，:j;

AX8052F143��º：0 dBm / 8 mATX�9.5 mA RX�G(868 MHzAO)。


AX8052F143

www.onsemi.cn38

3�;<*�

Figure 19. Typical Application Diagram with Two Single−ended Antenna and External Antenna Switch

Antenna switch

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4

GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F143

PB3

PB3


AX8052F143

www.onsemi.cn39

3�9�VCO�=

Figure 20. Typical Application Diagram with External VCO Inductor

LVCO

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F143


AX8052F143

www.onsemi.cn40

3�9�VCO

Figure 21. Typical Application Diagram with External VCO

VC

TR

L

OU

TP

OU

TN

EN

VCO

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F143


AX8052F143

www.onsemi.cn41

3�TCXO

Figure 22. Typical Application Diagram with a TCXO

TCXO

C1_TCXO

C2_TCXO

EN_TCXO

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

CLK

16P

CLK

16N

TS

T1

TS

T2

VD

D_I

O

PA

5

PA

4

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

FIL

T

L2 L1 SY

SC

LK

PC

3

PC

2

PC

4GND PB3

PA

3

PA

2

PA

1

PA

0

VD

D_I

O

PC

1

PC

0

PB

0

PB

2

PB

1

AX8052F143

PB2

PB2

11： �@45TCXO�"ónRTCXOad��L°s@，:j;AX5043��º：��

TCXOj[��。


AX8052F143

www.onsemi.cn42

QFN40=,4:

=,>?QFN40 5 x 7 mm

Figure 23. Package Outline QFN40 5 x 7 mm

NOTES:1. ‘e’ represents the basic terminal pitch2. Datum ‘C’ is the mounting surface with which the package is in contact.3. ‘3’ specifies the vertical shift of the flat part of each terminal from the mounting surface.4. Dimension ‘A’ includes package warpage.5. Dimension ‘b’ applies to the metallised terminal and is measured between 0.15 to 0.30 mm from the terminal tip. If the terminal

has the optional radius on the other end of the terminal, the dimension ‘b’ should not be measured in the radius are 6. Package dimension take reference from JEDEC MO−2207. AWLYYWW is the packaging lot code8. V is the device version9. RoHS

AX8052F143−VAWLYYWW

ON


AX8052F143

www.onsemi.cn43

QFN40-$@�

Figure 24. QFN40 Soldering Profile

Preheat Reflow Cooling

TP

TL

TsMAX

TsMIN

ts

tL

tP

T25°C to Peak

Tem

pera

ture

Time

25°C

Table 34.

Profile Feature Pb−Free Process

Average Ramp−Up Rate 3°C/s max.

Preheat Preheat

Temperature Min TsMIN 150°C

Temperature Max TsMAX 200°C

Time (TsMIN to TsMAX) ts 60 – 180 sec

Time 25°C to Peak Temperature T25°C to Peak 8 min max.

Reflow Phase

Liquidus Temperature TL 217°C

Time over Liquidus Temperature tL 60 – 150 s

Peak Temperature tp 260°C

Time within 5°C of actual Peak Temperature Tp 20 – 40 s

Cooling Phase

Ramp−down rate 6°C/s max.

1. All temperatures refer to the top side of the package, measured on the the package body surface.


AX8052F143

www.onsemi.cn44

QFN40��

1.@�PCBñò�ñ¬}ô�s@]§25ot。

Figure 25. PCB Land and Solder Mask Recommendations

A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimumB = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimumC = Clearance from PCB land edge to solder mask opening to be as tight as possible

to ensure that some solder mask remains between PCB pads.D = PCB land length = QFN solder pad length + 0.1 mmE = PCB land width = QFN solder pad width + 0.1 mm

2. PCBõñò��õ?÷(�&!cñò)，�|êPCBÜ[�� ~!c²ø�õÇ

'。õ?÷$U��öõ�¢，�?

õ &H5�?�UM。

3.�+PCBõ?÷�$U'|ê÷[!c²ø�

S�öõ��õÇ'。�¸，�+IC!�ø?PCð��'|ê��õ��I'，)�

2JÑ��,D@1�ðzë�ù�õ。

),./

�>!."#?@

1.R�ñù�úû，Þß�� ð。

2.Þß��ú'�0.125 – 0.150 mm (5 – 6,ü)� ð��}ô。

3.R�PCBõñò，}ñùûJPCB�，�lzJ ð�)�=U�À�? ，? ¨[ý

åQFNS|ñò[ý�50%。ñù�?��

�G(HüG)²øúû，]§26ot。

4.�yñò�? ÃåQFNñò[ý�50−80%，]§27ot。

5.H�，��X�cúûñù，÷ýÃ�þG

üÎ。

6. IC-��°À&s�2# ð�PCB�UR�。úþñù19， ð�PCBÑ��&s

ÃJ+1,ü�。

7.Þß��¼²�ñ�，]¸��î�8ñ�，

õñò!��ñ�'��²�。

Figure 26. Solder Paste Application on Exposed Pad


AX8052F143

www.onsemi.cn45

Figure 27. Solder Paste Application on Pins

Minimum 50% coverage 62% coverage Maximum 80% coverage

Table 35. DEVICE VERSIONS

Device Marking AX8052 Version AX5043 Version

AX8052F143−1 1 1

AX8052F143−2 1C 1


AX8052F143

www.onsemi.cn46

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coveragemay be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyeris responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless ofany support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can anddo vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’stechnical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorizedfor use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devicesintended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnifyand hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductorwas negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyrightlaws and is not for resale in any manner. (��)ON Semiconductor&ON'Semiconductor Components Industries, LLC (()*� �)+�,�-.*/&/+��/0/1��23。()*� �4567��、23、89、2�:;&��<=�9。�>�?()*� ��@/��A，BCDwww.onsemi.com/site/pdf/Patent*Marking.pdf。()*� �59EF�G�HI�@��JK，L�MNO<。()*� ��E�@�P�QRSQ%��、TI+U�，��VUWXQ+�Q�@+�YZ�[�\，]��E^_��`VU\， a!��"Pb�`、cd�`+ef�`。#0XE��Q�()*� ��@�XQ&�@g\， ahiH5�j、�k&($lm+3%，�n()*� �o&pqr+XQ�A。()*� �st�&/+ku�o&�“'v”ws.�x�XQ��Z��y[J(，z{%��|}c~�ZJ(。H5�)ws( a“'v�”)��0�E��P�XQ�N��。()*� ��，��9�。()*� ��@]��、��+�9Q)[��*��，+FDA 3�+��+./��,5 x+�-.��+��，+¡01��。¢#0£#()*� ��@+��Q"¤��+¥�9XQ，#0X�()*� �¦�§¨©ª、ª�、,�-、*«�-&¬22"VUH5®¯、°Q、�`¯3&°Q，4¦±d+cd�[�²³j´°Q、5¤��+¥�9�Q *�1µ6`+¶7®¯，8�¤�®¯·¸()*� �.¹º��+9»�¼.�½。()*� �4¾:µ;w<�“¿À:�/¿9N=�>”。F�GÁH5SQ89�ÂÃ，�Ä4Å_�Æ。

PUBLICATION ORDERING INFORMATIONN. American Technical Support: 800−282−9855 Toll FreeUSA/Canada

Europe, Middle East and Africa Technical Support:Phone: 421 33 790 2910

Japan Customer Focus CenterPhone: 81−3−5817−1050

AX8052F143CN/D

LITERATURE FULFILLMENT:Literature Distribution Center for ON Semiconductor19521 E. 32nd Pkwy, Aurora, Colorado 80011 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: [email protected]

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your localSales Representative

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