24wb less pin 21 dw suffix case 752ab - onsemi · m1 m2 c14 l2 d6 d9 t1 c4 vout r11 r30 u1 c7 r10...

38
© Semiconductor Components Industries, LLC, 2012 December, 2012 Rev. 1 1 Publication Order Number: NCP1910JP/D NCP1910 ATX電源用高性能コンボ・ コントローラ NCP1910SO24WBパッケージに収されており、世代 ATXまたはTVコンバータへの力供目的とする 搭載しています。NCP1910は、65 kHz連続導 モード力コントローラおよび高電圧ドライバを供する LLCコントローラを備え、85以上のオフライン力を供できます。厳しい効化の解決するために、 PFC調整な周波数フォールドバックを実装し、負荷 くなる のスイッチング 損失 を低 しています。 ATXおよびTVの仕必要とされるすべての信号シーケ ンスに処するために、コントローラには2側と1側のハ ンドシェイクを可にするいくつかの専用ピンが備わってい ます。これらの信号にはパワー・グッド・ラインだけでなく 、オプトカプラを経由してコントローラをオン/オフする制ピンも含まれています。のために、2OVP入力で、 メイン帰還ネットワークがドリフトする場合に必要な冗供しています。流状態発生した場合、フォー ルト入力が動リカバリ・ソフトスタート・シーケンスをト リガしてちに反します。 特長 波数65 kHzCCMコントローラ ラインみを低するためのモード制きなアンダシュートを削する動的応答エンハンサ ラッチオフ機能付きの独立した圧保センス・ピン 調整な周波数フォールドバックによる軽負荷ホールドアップたすための50 ms遅延 付き調整なライン・ブラウンアウト保最適化されたセンス抵抗接続されるプログラム スレッショルド ±1 AピークドライブLLCコントローラは25 kHzから500 kHzで動作 600 V高電圧ドライバ内1 A/0.5 Aのシンク/ソース温度範囲で±3%最小波数精度 300 nsの内デッドタイム値 調整なソフトスタート・シーケンス 迅速動リカバリ保のためにソフトスタート をトリガするフォールト入力 2側によるのためのon /offピン 正確なスレッショルド/ヒステリシス調整のための 5V リファレンス圧を内パワー・グッド出力管理信号 2グランド・ピン(スキップなし)Aバージ ョン、単一グランドとLLCコントローラスキッ プ動作を備えたB バーション 20 V動作 フリー・デバイス 代表的アプリケーション 複数出力のATX(Aバージョン) TV(Bバージョン) MARKING DIAGRAM SO24WB Less Pin 21 DW SUFFIX CASE 752AB http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 37 of this data sheet. ORDERING INFORMATION NCP1910XXX AWLYYWWG 1 XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = PbFree Package

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Page 1: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

© Semiconductor Components Industries, LLC, 2012

December, 2012 − Rev. 11 Publication Order Number:

NCP1910JP/D

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MARKING DIAGRAM

SO−24WB Less Pin 21DW SUFFIX

CASE 752AB

http://onsemi.com

See detailed ordering and shipping information in the packagedimensions section on page 37 of this data sheet.

ORDERING INFORMATION

NCP1910XXXAWLYYWWG

1

XXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekG = Pb−Free Package

Page 2: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

http://onsemi.com2

Figure 1. Pin Connections

GND/PGNDOVP2DRVPG adj.VCCVrefMLBO adj.

ON/OFFBridgePG outMURtVbootSS

Skip/AGNDFBCS/FFVCTRL

1 24

FoldLBOCSVM

PIN DESCRIPTION

Pin N� Pin Name Function Pin Description

1 SS Soft−start A capacitor to ground sets the LLC soft−start duration

2 Rt The LLC feedback pin A resistive arrangement sets the maximum and minimumswitching frequencies with opto coupler−based feedbackcapabilities.

3 PG out The open−collector power good signal This pin is low when Vbulk is ok, opens when Vbulk passesbelow a level adjusted by PGadj pin.

4 on/off Remote control When pulled low, the circuit operates: the PFC starts first andonce FB is in regulation, the LLC is authorized to work. Whenleft open, the controller is in idle mode.

5 BO adj. Brown−out adjustment This pin sets the on and off levels for the PFC powering theLLC converter

6 Vref The 5 V reference pin This pin delivers a stable voltage for threshold adjustments

7 PG adj. The power good trip level From the Vref pin, a dc level sets the trip point for the PFCbulk voltage at which the PG out signal is down.

8 OVP2 Redundant OVP A fully latched OVP monitoring the PFC bulk independentlyfrom FB pin.

9 FB PFC feedback Monitors the boost bulk voltage and regulates it. It also servesas a quick auto−recovery OVP

10 VCTRL PFC Error amplifier output PFC error amplifier compensation pin

11 VM PFC current amplifier output A resistor to ground sets the maximum power level

12 LBO PFC line input voltage sensing Line feed forward and PFC brown−out

13 Fold PFC fold back This pin selects the power level at which the frequency startsto reduce gradually.

14 CS PFC current sense This pin senses the inductor current and also programs themaximum sense voltage excursion

15 CS/FF Fast−fault input When pulled above 1 V, the LLC stops and re−starts via a fullsoft−start sequence.

16 Skip/AGND Skip (B)/AGND (A) This pin is either used as the analog GND for the signal circuit(A) or for skip operation (B).

17 GND/PGND GND (B)/PGND (A) The controller ground for the driving loop (A) or the lumpground pin for all circuits (B)

18 DRV PFC drive signal The driving signal to the PFC power MOSFET

19 VCC The controller supply The power supply pin for the controller, 20 V max.

20 ML Lower−side MOSFET Drive signal for the lower side half−bridge MOSFET

22 Bridge Half−bridge This pin connects to the LLC half−bridge

23 MU Upper−side MOSFET Drive signal for the upper side half−bridge MOSFET

24 Vboot Bootstrapped Vcc The bootstrapped VCC for the floating driver

Page 3: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

http://onsemi.com3

*It i

s re

com

men

ded

to s

epar

ate

the

trace

s of

pow

er g

roun

d an

d an

alog

gro

und.

The

pow

er g

roun

d (p

in 1

7) fo

r driv

ing

loop

(PF

C D

RV

and

LLC

ML)

is c

onne

c-te

d to

the

PF

C M

OS

FE

T d

irect

ly. T

he a

nalo

g gr

ound

for

adju

stm

ent c

ompo

nent

s is

rou

ted

toge

ther

firs

t and

then

con

nect

ed to

the

anal

og g

roun

d pi

n (p

in16

) an

d th

e P

FC

sen

se r

esis

tor

dire

ctly

.

Fig

ure

2. T

ypic

al A

pp

licat

ion

Sch

emat

ic in

A V

ersi

on

M1

M2

C14

L2D

6

D9

T1

C4

Vo

ut

R11

R30

U1

C7

U2BR

10

R18

. .

.

R9

R17

R8

R16

C3

Ove

r C

urre

ntC

15

R29

D12

D11

C13

R28

1 2 3 4 5 86 7 9

10

1314151617181920

11 12

222324

U10

0

C12

R22

R12

U2A

U3A

C10

0.1u

Bul

k

12 V

aux

.

on/o

ffF

B

Vcc

R21

Vre

f

Pow

erG

ood

C6

0.1u

R14

R15

PG

adj

.R

13

BO

leve

l

R31

0.1

D4

D8

D3

D7

C5

D2

C1

L1

R19 10

D10

R20

10k

R1

3.5M

R2

1.5M

R32

3.6kR4

2.2M

R5

3.5M

Inpu

tLi

ne

D5

D1

R23

120k

C8

0.22

uC2

R24

24k

R3

1.5M

R7

2.2M

R26

24k

C9

1u

R25

24k

R27

39k

C11

1n

R33

1.2k

R6

Vre

f

X2

PA

D2

X3

V33

V32

C16

0.1u

R34

8.4k

C17 1n

(*)(*

)

Q1

R35

300

C18

1n

Page 4: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

http://onsemi.com4

*It i

s re

com

men

ded

to s

epar

ate

the

trac

es o

f pow

er g

roun

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d an

alog

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The

ana

log

grou

nd tr

aces

for

adju

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s ar

e ro

uted

toge

ther

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the

grou

nd p

in (

pin

17).

The

pow

er g

roun

d fo

r dr

ivin

g lo

op (

PF

C D

RV

and

LLC

ML)

is c

onne

cted

from

gro

und

pin

(pin

17)

to th

e P

FC

sen

se r

esis

tor

dire

ctly

and

as s

hort

as

poss

ible

.

Fig

ure

3. T

ypic

al A

pp

licat

ion

Sch

emat

ic in

B V

ersi

on

M1

M2

C14

L2D

6

D9

T1

C4

Vo

ut

R11

R30

U1

C7

U2B

R10

R18

. .

.

R9

R17

R8

R16

C3

Ove

r C

urre

ntC

15

R29

D12

D11

C13

R28

1 2 3 4 5 86 7 9 10

1314151617181920

11 12

21222324

U10

0

C12

R22

R12

U2A

U3A

C10

0.1u

Bul

k

12 V

aux

.

on/o

ff

FB

Vcc

R21

Vre

f

Pow

erG

ood

C6

0.1u

R14

R15

PG

adj

.R

13

BO

leve

l

R31

0.1

D4

D8

D3

D7

C5

D2

C1

L1

R19

10

D10

R20

10k

R1

3.5M

R2

1.5M

R32

3.6kR4

2.2M

R5

3.5M

Inpu

tLi

ne

D5

D1

R23

120k

C8

0.22

u

C2

R24

24k

R3

1.5M

R7

2.2M

R26

24k

C9

1u

R25

24k

R27

39k

C11

1n

R33

1.2k

R6

Vre

f

X2

PA

D2

X3

V33

V32

C16

0.1u

R34

8.4k

C17

1n

(*)(*

)

Q1

R35

300

C18

1n

R36

C19

skip

Page 5: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

http://onsemi.com5

+

+

VOVPVUVP

105% Vpref

8% Vpref

PFC_OPL

+

OVP2

FB

95% Vpref

+

VLD

Vpref

VCTRL

OTA

Vctrl(min)

A

BMultiplier

LBO

CS

VDD

VLBO^2

“1” BO NOTOK,“0” BOK

A

BA/B

ICS

AB

Vctrl−Vctrl(min)

ICS x VLBO^2

+

+

ICS x VLBO > 275 uA

ICS > 200 uA

ICS SU

M 2

K1

K2

PFC_OL

VM

+ −

“0” / “1”Vpref / 10%Vpref

S

R

QQ

+

Vpref

PFC_OVPPFC_OL

TSD

VLBO^2

VDD

IVLD

DynamicResponseEnhancer

“1” = UVP, “0” ok

Closedif “1”

“1” OVP, “0” = ok

Vfold

ICS

Vdd

Oscillator section

ICt(min)

DRV

Vcc

foldbackPFC drive signal

OnoffUVLO

Latch

RFBpull down

“1” = OPL

“1” = OCP

PFC_UVP

The “PFC_OK” toggles high when:− VLD is low− PFC issues a driving pulseThe “PFC_OK” toggles low when:− Vctrl stays out of window [Vctrl,min toVctrl,max] > 1 sec− at this point, the latch is reset and the“PFC_OK” output goes low.

“1” = below 5% reg“0” ok

Auto−recovery internal OVP

+

−VOVP2

107% Vpref “1” OVP2, “0” = okLatched adjustable OVP2

PFC_OVP2latched

Vctrl

+

Vctrl(min) − 0.1 V

Vctrl

+

1 secdelay

If PFC issues an abnormalsituation, then latch off

Grand Reset

PFC_OK

PFC_OK

S

R

QQ

PFC_OK

Grand Reset

PFC_SKIP(0.6 V clampvoltage isactivated.)

VLBOPFC_BO+

−ILBO

VLBOT

20 us filter

Latch

PFC_BO

PFC_SKIP

+

Vctrl(max)PFCflag

ICt

Vfold(max)

Ict(fold)

S

RQQ

PFC_OVP

Grand Reset

PFC_OCP

PFC_OPL

GrandReset

“1” open“0” close

PFC_abnormallatched

PFC_BO

PFC_BO

PFC_BO

PFC_BO

+

“1” = FB > Vpref

S

RQQ

Grand ResetPFC_BO

Figure 4. Internal PFC Block Diagram

ICS � VLBO2

4(Vctrl � Vctrl(min))

BO delay

Page 6: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

http://onsemi.com6

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Figure 5. Internal LLC Block Diagram

Page 7: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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MAXIMUM RATINGS TABLE

Symbol Rating Value Unit

VBridge Continuous High Voltage bridge pin, pin 22 −1 to 600 V

VBOOT–VBridge Floating supply voltage, pin 24−22 −0.3 to 20 V

VMU, VDRV High side output voltage, pin 23 VBRIDGE − 0.3 toVBOOT + 0.3

V

VML Low side output voltage, pin 18, 20 −0.3 to VCC + 0.3 V

dVBridge/dt Allowable output slew rate on the Bridge pin, pin 22 50 V/ns

VCC Power Supply voltage, pin 19 20 V

Pin voltage, all pins (except pin 2, 6, 18 − 24, GND) −0.3 to 10 V

RθJA Thermal Resistance Junction−to−Air50 mm2, 1 oz650 mm2, 1 oz

8065

°C/W

Storage Temperature Range −60 to + 150 °C

ESD Capability, Human Body Model (All pins except VCC and HV) 2 kV

ESD Capability, Machine Model 200 V

VCC Power Supply voltage, pin 19 20 V

Pin voltage, all pins (except pin 2, 6, 18 ~ 24, GND) −0.3 to 10 V

VRt Rt pin voltage −0.3 to 5 V

Vref_out Vref pin voltage −0.3 to 7 V

IMAX Pin current on pin 10, 12, and 13 0.5 mA

IPGout Pin current on pin 3 5 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.1. This device(s) contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC Standard JESD22−A114EMachine Model 200 V per JEDEC Standard JESD22−A115−A

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

COMMON TO BOTH CONTROLLERS

SUPPLY SECTION

VCC(on) Turn−on threshold level, VCC going up 19 9.4 10.4 11.4 V

VCC(min) Minimum operating voltage after turn−on 19 8 9 10 V

VCC(Hys) Hysteresis between VCC(on) and VCC(min) 19 1.2 − − V

VBoot(on) Startup voltage on the floating section 24,22 7.8 8.8 9.8 V

VBoot(min) Cutoff voltage on the floating section 24,22 7 8 9 V

Istartup Startup current, VCC < VCC(on) 19 − − 100 �A

ICC1 PFC consumption alone, DRV pin unloaded, on/off pin grounded,LLC off (PFC is 65 kHz)

19 − 5.1 6.4 mA

ICC2 PFC consumption, DRV pin loaded by 1 nF, on/off pin grounded, LLCoff (PFC is 65 kHz)

19 − 5.9 7.4 mA

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor dischargeslope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltageis still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

Page 8: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

http://onsemi.com8

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

COMMON TO BOTH CONTROLLERS

SUPPLY SECTION

ICC4 IC consumption, both PFC and LLC loaded in no load conditions(PFC is 65 kHz and Rt = 70 k� (LLC is 25 kHz))

19 − 5.9 7.2 mA

ICC5 IC consumption, both PFC and LLC loaded 1 nF load conditions(PFC is 65 kHz and Rt = 70 k� (LLC is 25 kHz))

19 − 6.9 8.6 mA

ICC6 IC consumption in fault mode from Vboot (drivers disabled, Vboot >Vboot(min))

19 − 64 300 �A

ICC7 IC consumption in OFF mode from VCC (on/off pin is open) 19 − − 950 �A

REFERENCE VOLTAGE

Vref−out Reference voltage for external threshold setting @ Iout = 5 mA 6 4.75 5 5.25 V

Vref−out Reference voltage for external threshold setting @ Iout = 5 mA – TJ =25°C

6 4.9 5 5.1 V

VrefLineReg Vcc rejection capability, Iout = 5 mA − �VCC = 1 V – TJ = 25°C 6 − 0.01 5 mV

VrefLoadReg Reference variation with load changes, 1 mA < Iref < 5 mA – TJ =25°C

6 − 1.6 7 mV

Iref−out Maximum output current capability 6 5 − − mA

NOTE: Maximum capacitance directly connected to VREF pin must be under 100 nF.

DELAY

tDEL1 Turn−on LLC delay after PFC OK signal is asserted − 10 20 30 ms

tDEL2 Turn−off LLC after power good pin goes low (Note 3) − 2 5 8 ms

PROTECTIONS

RPull−up on/off pin pull−up resistor 4 − 5 − k�

ton/off Propagation delay from on to off (ML & MU are off) (Note 4) 4 − − 1 �s

Von Low level input voltage on on/off pin (NCP1910 is enabled) 4 − − 1 V

Voff High level input voltage on on/off pin (NCP1910 is disabled) 4 3 − − V

Vop Open voltage on on/off pin 4 − 7 − V

IPG Maximum Power good pin sink current capability 3 5 − − mA

VPG Power good saturation voltage for IPG = 5 mA 3 − − 350 mV

IPGadj Input bias current, PGadj pin 7 − 10 − nA

VPGadjH PG comparator hysteresis 7 − 100 − mV

TSD Temperature shutdown (Note 4) − 140 − − °C

TSDhyste Temperature Hysteresis Shutdown − − 30 − °C

POWER FACTOR CORRECTION

GATE DRIVE SECTION

RPOH Source Resistance @ IDRV = −100 mA 18 − 9 20 �

RPOL Sink Resistance @ IDRV = 100 mA 18 − 6.6 18 �

tPr Gate Drive Voltage Rise Time from 1.5 V to 10.5 V (CL = 1 nF) 18 − 60 − ns

tPf Gate Drive Voltage Fall Time from 10.5 V to 1.5 V (CL = 1 nF) 18 − 40 − ns

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor dischargeslope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltageis still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

Page 9: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

POWER FACTOR CORRECTION

REGULATION BLOCK

VPREF PFC Voltage reference − 2.425 2.5 2.575 V

IEA Error Amplifier Current Capability 10 − �30 − �A

GEA Error Amplifier Gain − 100 200 300 �S

IB Bias Current @ VFB = VPREF 9 0 − 0.3 �A

VCTRLVCTRL(max)VCTRL(min)�VCTRL

Maximum Control Voltage @ VFB = 2 VMinimum Control Voltage @ VFB = 3 V�VCTRL = VCTRL(max)−VCTRL(min)

101010

−−

2.7

3.60.63

−−

3.3

V

VOUTL / VPREF Ratio (VOUT Low Detect Threshold / VPREF) (Note 4) − 94 95 96 %

HOUTL / VPREF Ratio (VOUT Low Detect Hysteresis / VPREF) − − 0.5 − %

IVLD + IEA Source Current when (VOUT Low Detect) is activated 10 190 230 260 �A

CURRENT SENSE

VS Current Sense Pin Offset Voltage, (ICS = 100 �A) 14 − 10 − mV

ICS(OCP) Over−Current Protection Threshold 14 185 200 215 �A

POWER LIMIT

ICSx VLBO Over Power Limitation Threshold − 215 275 335 �VA

ICS(OPL1)ICS(OPL2)

Over−Power Current Threshold (VLBO = 1.8 V, VM = 0 V)Over−Power Current Threshold (VLBO = 3.6 V, VM = 0 V)

− 11956

15375

18799

�A

PULSE WIDTH MODULATION

FPSW PFC Switching Frequency 18 58 65 72 kHz

FPSW(fold) Minimum Switching Frequency (Vfold = 1.5 V, VCTRL = VCTRL(min) +0.1 V)

18 34 39 43 kHz

DCPmax Maximum PFC Duty Cycle 18 − 97 − %

DCPmin Minimum PFC Duty Cycle 18 − − 0 %

VCTRL(fold) VCTRL pin voltage to start frequency foldback (Vfold = 1.5 V) 10 1.8 2 2.2 V

VCTRL(foldend) VCTRL pin voltage as frequency foldback reducing to the minimum(FPSW = FPSW(fold), Vfold = 1.5 V)

10 1.4 1.6 1.8 V

Vfold(max) Maximum internal fold voltage (Note 4) − 1.97 2 2.03 V

LINE BROWN−OUT DETECTION

VLBOT Line Brown−Out Voltage Threshold 12 0.96 1.00 1.04 V

ILBOH Line Brown−Out Hysteresis Current Source 12 6 7 8 �A

tLBO(blank) Line Brown−Out Blanking Time − 25 50 75 ms

tLBO(window) Line Brown−Out Monitoring Window (Note 4) − 25 50 75 ms

VLBO(clamp) LBO Pin clamped voltage if VBO < VLBOT during tLBO(BLANK) (ILBO =100 �A)

12 − 980 − mV

VLBOH Hysteresis (VLBOT – VLBO(clamp)) (Note 4) 12 10 35 60 mV

ILBO(clamp) Current Capability of LBO 12 100 − − �A

VLBO(PNP) LBO pin voltage when clamped by the PNP Transistor (ILBO =100 �A)

12 0.4 0.7 0.9 V

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor dischargeslope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltageis still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

Page 10: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

POWER FACTOR CORRECTION

LINE BROWN−OUT DETECTION

VLBO(PD) Pull Down VLBO Threshold 12 1.8 2 2.2 V

tLBO(Pdlimit) Pull Down VLBO Time Limitation − 4.5 5 6.1 ms

tPFCflag Time Delay to Confirm that VCTRL is the maximum to Pull down VLBO − 2.5 5 7.5 ms

tLBO(Pdblank) Pull Down VLBO Blanking Time − 55 77 90 ms

CURRENT MODULATION

IM1

IM2

Multiplier Output Current (VCTRL =VCTRL(max) – 0.2 V , VLBO = 3.6 V,ICS = 50 �A)Multiplier Output Current (VCTRL =VCTRL(max) – 0.2 V , VLBO = 1.2 V,ICS = 150 �A)

11

11

46

15

58

19

72

24.5

�A

OVER−VOLTAGE PROTECTION

VOVP1 Internal Auto Recovery Over Voltage Threshold 9 2.536 2.615 2.694 V

VOVP1H Hysteresis of Internal Auto Recovery Over Voltage Threshold(Note 4)

9 − 44 60 mV

tOVP1 Propagation Delay (VFB = 108% VPREF) to Drive Low 9, 18 − 500 − ns

VOVP2 External Latched Over Voltage Threshold 8 2.595 2.675 2.755 V

KOVPH The difference between VOVP2 and VOVP1 over VPREF ((VOVP2 −VOVP1)/VPREF)

− − 2 − %

tDELOVP2 External Latched OVP Integrating Filter Time Constant − − 20 − �s

Ib,OVP2 Input bias current, OVP2 8 − 10 − nA

UNDER−VOLTAGE PROTECTION

VUVP(on)/VPREF UVP Activate Threshold Ratio 9 4 8 12 %

VUVP(off)/VPREF UVP Deactivate Threshold Ratio 9 6 12 18 %

VUVP(H) UVP Lockout Hysteresis 9 − 4 − %

tUVP Propagation Delay (VFB < 8 % VPREF) to Drive Low 9 − 18 − 7 − �s

PFC ABNORMAL

tPFCabnormal PFC Abnormal Delay Time (VCTRL = VCTRL(max) or VCTRL =VCTRL(min) – 0.1 V)

− 1 1.5 2.1 sec

LLC CONTROL SECTION

OSCILLATOR

FLsw,min Minimum switching frequency, Rt = 70 k� on Rt pin 2 24.25 25 25.75 kHz

FLsw switching frequency, DTL = 300 ns, Rt = 7 k� on Rt pin 2 208 245 282 kHz

FLsw,max Maximum switching frequency, DTL = 300 ns, Rt = 3.5 k� on Rt pin 2 424 500 575 kHz

DCL Operating Duty−Cycle symmetry 23, 20 48 50 52 %

VrefRt Reference voltage for oscillator charging current generation 2 3.33 3.5 3.67 V

RSS Discharge switch resistance 1 − 70 − �

SSRST Soft−start reset voltage 1 − 200 − mV

VSkip Skip cycle threshold, B version only 16 350 400 450 mV

Vskip,hyste Hysteresis level on skip cycle comparator, B version only 16 − 50 − mV

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor dischargeslope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltageis still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

Page 11: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

LLC CONTROL SECTION

DRIVE OUTPUT

TLr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 23, 20 − 40 − ns

TLf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 23, 20 − 20 − ns

RLOH Source resistance 23, 20 − 12 26 �

RLOL Sink resistance 23, 20 − 5 11 �

DTL Dead time, measured between 50% of the rise and fall edge 23, 20 268 327 386 ns

IHV,leak Leakage current on high voltage pins to GND (600 Vdc) 22, 23, 24 − − 5 �A

PROTECTIONS

IBOadj Input bias current, BOadj pin 5 − 15 − nA

VBOadjH BO comparator hysteresis 5 − 100 − mV

tBOK BO comparator Integrating Filter Time Constant from High to Low 5 − 150 − �s

tBONOTOK BO comparator Integrating Filter Time Constant from Low to High 5 − 20 − �s

VCS1 Current−sense pin level that resets the soft−start capacitor 15 0.95 1 1.05 V

VCS2 Current−sense pin level that permanently latches off the circuit 15 1.42 1.5 1.58 V

tCS Propagation delay from VCS1/2 activation to respective action 15 − − 500 ns

3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later,when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor dischargeslope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltageis still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms.

4. Guaranteed by design.

Page 12: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

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TYPICAL CHARACTERISTICS

8

8.5

9

9.5

10

10.5

11

−50 −25 0 25 50 75 100 125

VC

C(o

n) A

ND

VC

C(m

in) (

V)

Figure 6. VCC(on) and VCC(min) vs. Temperature

TEMPERATURE (°C)

VCC(on)

VCC(min)

7

7.5

8

8.5

9

9.5

10

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Vbo

ot(o

n) A

ND

Vbo

ot(m

in) (

V)

Figure 7. Vboot(on) and Vboot(min) vs.Temperature

Vboot(on)

Vboot(min)

0

25

50

75

100

−50 −25 0 25 50 75 100 125

I sta

rtup

(�A

)

TEMPERATURE (°C)

Figure 8. Istartup vs. Temperature

550

650

750

850

950

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Figure 9. ICC7 vs. Temperature

I CC

7 (�

A)

4.75

4.85

4.95

5.05

5.15

5.25

−50 −25 0 25 50 75 100 125

Vre

f−ou

t (V

)

Figure 10. Vref-out vs. TemperatureTEMPERATURE (°C)

4.987

4.988

4.989

4.99

0 1 2 3 4 5 6

Vre

f−ou

t @ 2

5°C

(V

)

TEMPERATURE (°C)Figure 11. Vref-out @ 25�C vs. Iref-out

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TYPICAL CHARACTERISTICS

1

1.5

2

2.5

3

−50 −25 0 25 50 75 100 125

Von

AN

D V

off (

V)

TEMPERATURE (°C)

Figure 12. Von and Voff vs. Temperature

Von

Voff

2

4

6

8

10

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

RP

OH

AN

D R

PO

L (�

)

Figure 13. RPOH and RPOL vs. Temperature

RPOH

RPOL

2.4

2.5

2.6

2.7

2.8

−50 −25 0 25 50 75 100 125

VP

RE

F, V

OV

P1,

AN

D V

OV

P2

(V)

TEMPERATURE (°C)

Figure 14. VPREF, VOVP1, and VOVP2 vs.Temperature

VOVP2

VOVP1

VPREF

−40

−35

−30

−25

−20

−50 −25 0 25 50 75 100 125

I EA

(sou

rce)

(�A

)

TEMPERATURE (°C)

Figure 15. IEA(source) vs. Temperature

20

25

30

35

40

−50 −25 0 25 50 75 100 125

I EA

(sin

k) (�A

)

TEMPERATURE (°C)

Figure 16. IEA(sink) vs. Temperature

100

150

200

250

300

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

GE

A (�S

)

Figure 17. GEA vs. Temperature

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TYPICAL CHARACTERISTICS

3.3

3.4

3.5

3.6

3.7

3.8

3.9

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VC

TR

(max

) (V

)

Figure 18. VCTRL(max) vs. Temperature

2.7

2.8

2.9

3

3.1

3.2

3.3

−50 −25 0 25 50 75 100 125

�V

CT

R (

V)

TEMPERATURE (°C)

Figure 19. �VCTRL vs. Temperature

190

200

210

220

230

240

250

260

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

I VLD

+ I E

A (�A

)

Figure 20. IVLD+IEA vs. Temperature

185

190

195

200

205

210

215

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

I CS

(OC

P) (�A

)

Figure 21. ICS(OCP) vs. Temperature

120

130

140

150

160

170

180

190

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

I CS

(OP

L1) (�A

)

Figure 22. ICS(OPL1) vs. Temperature

55

65

75

85

95

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

I CS

(OP

L2) (�A

)

Figure 23. ICS(OPL2) vs. Temperature

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TYPICAL CHARACTERISTICS

58

60

62

64

66

68

70

72

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

FP

SW

(kH

z)

Figure 24. FPSW vs. Temperature

34

36

38

40

42

44

−50 −25 0 25 50 75 100 125

FP

SW

(fol

d) (

kHz)

TEMPERATURE (°C)

Figure 25. FPSW(fold) vs. Temperature

0.96

0.98

1

1.02

1.04

−50 −25 0 25 50 75 100 125

VLB

OT (

V)

TEMPERATURE (°C)

Figure 26. VLBOT vs. Temperature

6

6.5

7

7.5

8

−50 −25 0 25 50 75 100 125

I LB

OH

(�A

)

TEMPERATURE (°C)

Figure 27. ILBOH vs. Temperature

4

6

8

10

12

14

16

18

−50 −25 0 25 50 75 100 125

VU

V(o

n) /

VP

RE

F A

ND

VU

P(o

ff) /

VP

RE

F (

%)

TEMPERATURE (°C)

Figure 28. VUVP(on)/VPREF and VUVP(off)/VPREFvs. Temperature

VUVP(on) / VPREF

VUVP(off) / VPREF

24

24.5

25

25.5

26

−50 −25 0 25 50 75 100 125

FLS

W,m

in (

kHz)

TEMPERATURE (°C)

Figure 29. FLsw,min vs. Temperature

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TYPICAL CHARACTERISTICS

210

220

230

240

250

260

270

280

−50 −25 0 25 50 75 100 125

FLS

W (

kHz)

TEMPERATURE (°C)

Figure 30. FLsw vs. Temperature

425

450

475

500

525

−50 −25 0 25 50 75 100 125

FLS

W,m

ax (

kHz)

TEMPERATURE (°C)

Figure 31. FLsw,max vs. Temperature

−50 −25 0 25 50 75 100 1253.3

3.4

3.5

3.6

3.7

Vre

fRT (

V)

TEMPERATURE (°C)

Figure 32. VrefRt vs. Temperature

100

150

200

250

300

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

SS

RS

T (

mV

)

Figure 33. SSRST vs. Temperature

350

375

400

425

450

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Vsk

ip (

mV

)

Figure 34. Vskip vs. Temperature

2

4

6

8

10

12

14

16

18

20

22

24

−50 −25 0 25 50 75 100 125

RLO

H,M

L A

ND

RLO

L,M

L (�

)

TEMPERATURE (°C)

Figure 35. RLOH,ML and RLOL,ML vs.Temperature

RLOL,ML

RLOH,ML

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TYPICAL CHARACTERISTICS

2

4

6

8

10

12

14

16

18

20

22

24

−50 −25 0 25 50 75 100 125

RLO

H,M

U A

ND

RLO

L,M

U (�

)

TEMPERATURE (°C)

RLOL,MU

RLOH,MU

Figure 36. RLOH,MU and RLOL,MU vs.Temperature

300

310

320

330

340

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

DT

L (n

s)

Figure 37. DTL vs. Temperature

0.95

0.975

1

1.025

1.05

−50 −25 0 25 50 75 100 125

VC

S1

(V)

TEMPERATURE (°C)

Figure 38. VCS1 vs. Temperature

1.4

1.45

1.5

1.55

1.6

−50 −25 0 25 50 75 100 125TEMPERATURE (°C)

VC

S2

(V)

Figure 39. VCS2 vs. Temperature

20

40

60

80

100

120

140

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

t CS (

ns)

Figure 40. tCS vs. Temperature

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NCP1910

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C in

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L I L

C bulk

V in

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Figure 41. CCM PFC Boost Converter

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Figure 43. PFC Duty Modulation and Timing Diagram

VPREF

VPREF

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NCP1910

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11

VM

PFC DutyModulation

RMCM

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Figure 45. The Multiplier Voltage Pin Configuration

VM �RMICS

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4�VCTRL � VCTRL�min��

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PFC_BOVLBOT

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tLBO(blank) tLBO(window)

VLBO(clamp)

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Figure 46. The Line Brown−Out Configuration

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Page 23: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

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RLBOU � RLBOL

� ILBOH

(eq. 9)

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RLBOU � RLBOL

VLBO � 2 Vac,rms

RLBOL

RLBOU � RLBOL

� ILBOHRLBOL

• PFCC����h��®«�a��-��4X²

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1 ��LBO3�line

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0.967�

2

Vac,on

Vac,off

� 1� VLBOT

ILBOH

RLBOU � � 2 Vac,on

ILBOHRLBOL � VLBOT

� 1�RLBOL

(eq. 12)

Page 24: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

http://onsemi.com24

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Figure 47. PFC Current Sensing Configuration

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IL (eq. 13)

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Figure 48. PFC Over−Power Limitation Configuration

9�

> 275 �VA?

Ø(ICS x VLBO)Az{~£?275 �VA�y0 ����.C�PFC'*.�����34#�a���A

] ���%OPL��Ø(ICS x VLBO)A275 �VA~£?+�FB< ��:h���p@��{�<���%U�275 �VA~£?��Èèa���(IL x Vac)�)<#� ��~ 15�j=�l�~+�^SB<���%

ICSVLBO � 275 �VA

(eq. 15)

�ILRSENSE

RCS

���2 2 KLBO

� Vac� � 275 �VA

IL Vac �RCS �

RSENSE KLBO

97 �VA

UU5�

KLBO �RLBOL

RLBOU � RLBOL

Page 25: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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PFC�;<=>�'(���Ud4�~�C�-(VPREF)��`PQR��S�T�±2%�TQ�< +�(d��E56��(����2.5 V)%VPREF��PFCx@K���.=9���� d4�~�C�-5�%

PFC%?@A�B

OTA

VbulkVin

RFBU

RFBL

RZ

CZ

CP

VCTRL(min)

To Multiplier of VM pin

FB

VCTRL

VPREF

Figure 49. VCTRL Type−2 Compensation

Figure 49�±�+���PFC"�����-Vbulk��LM¹Áµ(RFBL +,RFBU)�í#�FBR�5q����%Vbulk��~16�±�� �.=9���%

Vbulk � VPREF

RFBU � RFBL

RFBL

(eq. 16)

12IJVFBB����-Vbulk�Â#� �����-�.=9�3�-wE(OVP)��93Ù<A� +,F�-wE(UVP)������%3Û~�K�¾?X(*�C��q@��CXp�[(OTA)��������<SkVbulk�< �¬9� ]-�-VCTRL�8p#��%VCTRL�h�

R���VCTRL(min)QVVCTRL(max)�55�%PFC�r���¬����� IJ��34x�(�-

VCTRL(min)�Ú$�«�IJ��<Sk�VCTRL − VCTRL(min)5�%

U�]-�-VCTRL��À�Q�¬9� IJ5¦ PFC����-VbulkQV8p� �ÕÖ�=��-5�%VCTRL��«���ivZ�.[−2^»nÛ(Figure 49�±�RZ�CZ� +,CP)�¬a� U��+T�] �Ü­56��%a�AC�-A50 Hz�ef���^X�����p� ���3�[�X?�[XKC�}�À¤=�����20 Hz1¤�] � U����#��%

CZ >> CP�ef��VbulkQVVCTRL���-¬º�~ 16�ÆT�`S���%GEA�t*�Xp�[

��.�5�%

VCTRL

Vbulk

�RFBL GEARZ

RFBL � RFBU

1 � sRZCZ

sRZCZ�1 � sRZCP

�(eq. 17)

PFC%��CDAVin2;E�F;G2�F

~ 7QV~ 13�+��a�.�R�q�CZin�~ 18�+��Ã6;�U�A56��%

Zin �2RMRSENSE KLBO

2 Vac2 VbulkIL

� 2RCS �VCTRL � VCTRL�min�� VPREFIL−50

(eq. 18)

ILAIL−50�Ñ#$ef�~ 18�~19�+��Ã6;�U�A56��%

Zin �2RMRSENSE KLBO

2 Vac2 Vbulk

� 2RCS �VCTRL � VCTRL�min�� VPREF

(eq. 19)

ÒÓ����uCM��ÒÓ�-VM��=�p¹��É� �:�^�5�%�=�p¹���³��.�q@��4IL�,Å#�$��%�}�a�4�?�X����uCin^�&��.�q@��4IL��=�p¹��É#��%����uCM���

��uCinA�4�?�d�E���Á5�$��Ñ5¦ ef�IL�IL−50�<���%a�.�R�q

�CZin��50 Hz���60 Hz��«�5ÕÖ�=�<����A^X��$��%"�8�ηA»V� Qé=56 ef�a��

������(Pin�Pout)��~20 +,~21QV�Q���%¬�Vac��RMSa��-�Â#�$��%

Pin �Vac

2

Zin

� 2 RCS �VCTRL � VCTRL�min�� VPREF

2RMRSENSEKLBO2 Vbulk

(eq. 20)

�VCTRL � VCTRL�min��

Vbulk

Pin � �Pin � �

�2 RCS �VCTRL � VCTRL�min�� VPREF

2RMRSENSEKLBO2 Vbulk

(eq. 21)

�VCTRL � VCTRL�min��

Vbulk

Vin24��'4>W�'�+T�������a

��-QVCD#�$��%#�AT������²����a��-QVCD#� ��^»?�[klA{Ý�<���%

PFCHIJ;G�KFL1(NCP1910��" !G�8��Fy� �:��

PFCx@K���=��4>�?'��@B����#�$��%Vin

24��'4>W�'B��+�������(VCTRL − VCTRL(min))�Ä×#��%¿

Page 26: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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��:PFC=��4>�?'��@��(VCTRL − VCTRL(min))�FoldR���-Vfold�ÄÞ#�`$��%

PFC=��4>�?'��@B��mß9{)�@Ð��Figure 50�±#��%

Figure 50. The PFC Frequency Foldback Block

+ −“0” / ”1”VPREF / 10%VPREF

Oscillator section

Vref

Ict(min)Ict

Vfold

Vfold(max)

S

R

Q

Q

PFC OK

Grand Reset

PFCOSC

Vdd

Ict(fold)

PFC BO

Vctrl

Vctrl(min)

UU5�♦ ICt(min)�Sh�=���] #��%

♦ ICt�ICt(min)�7_µ�¨��4���#�¿�

�+T�îàh�=���]-#��%

♦ Vfold��=��4>�?'��@��®� �

�~£?��=#��%

♦ ICt(fold)��Vfold�(VCTRL − VCTRL(min)) ���á

¤âï�ÆT��ICtQV�4�ã$�¿��+

T�h�=���F¤���%

♦ VCTRL�)#=��4>�?'��@A¯°�

ð6���U5m=��$��%

♦ Vfold(max)��=��4>�?'��@�@�

�~£?�] � �:�^�5������

2 V5�%=��4>�?'��@��uhG��<Sk

Figure 50�PFCokIJAN.�pu�(� Æ���x�{?���%=��4>�?'��@A�®� ��~£?��VREFR��FoldR���

LM¹Áµ��ä#���56��%���FoldR��N�#�=��4>�?'��@���x�{?� U�^56��%

Figure 51��h�=���VCTRL���Ñ�±#��%

VCTRL−VCTRL(min) � Power

Fsw(fold)

Fsw

VfoldVfold – 0.4

The slope is fixed internally.The power level at which fre-quency starts reducing is ad-justable by modifying Vfold.

Figure 51. The Relationship between Frequency and VCTRL

FR

EQ

UE

NC

Y

Page 27: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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PFC��,�>�Æ�x@K��5·¸#�+���Vin

24��'

X4>W�'�8��+T�������a��-QVCD#�$��%U��+T���å<���=��4>�?'��@�;N]-�$�ëÁA»V���%#Q#�ACa��-A�*.�QVF*

.��æç�F¤� +�<jè<5é5��LBOR�2�4�?��a��-¬9�Ü�� l<9QAF¤� �:���A] � U�A¦���%Î�����?@�-A3Q�F¤#��LLC�����Aª�� ;�/A¦���%¿��:NCP1910��$SØ PFC��{�C(B���O#�$��%U�7¼��1¤�ef�LBOR��VLBO(PD)(��2 V)�[?q|�� ^�5�%• VLBOAVLBO(PD)(2 V)+��B�P��a�A�*

.�5¦��QP

• VCTRLA�tPFCflag5=ê���.ÈG�+��

B��#�@��<��QP

• VbulkAîà���95%�¤"T�$ �P��VLDA(dj��$ ef5�%@[?Xq|�G���tLBO(PDlimit)(��5 ms)5=ê���%U���{�C(B��l<Aë�

Ê<$+��� �:���77 ms(��)�{*���EX�.ÈtLBO(PDblank)A�¿��$��%uhG��?@�-Aîà���95%�y0 �5��PFC��{�C(B��v����%

PFC>M1��N�F× !565K¥<.=9�`��:��VCTRLAS~£?�¦ �6�"��u.@?�C��[#��%VCTRL���Up@��{X@*�[�+T��0.6 VQV3.6 V��������%C��[XK���C��0.6 V�@*�["�A(dj��$ ��78#�@*�["�A�p@��{�< �C.�D�Eh�A"Ì#��%

�O8PQR

.=9{)�@��«�A�$ef�uh�<��78� ��� !���a��-�¬h�+T��PFCC�������-�3§<3��Kr�(�p�qKr�(A8  ;�/A¦���%Figure 52�±�+���NCP1910����-A.=56QVi��ef��:�����-�.=9���� �:�2P�B��/0�$��%

+

��1��

��

����

�������

046: ���;�

��&

���,���

<6: ���;�

���,�2 ���,��� ���

9��&

�'��%

�1.

���;�

�=4 �.

344 �.

Figure 52. PFC OVP and VLD

• +�(#$(OVP)�VFBAVPREF�105%�y0�ef(�<Sk�Vbulk >îà�?@�-�105%)�PFC'*.����wE��:�)��<���%VFBAVPREF�103.2%+�^F¤#�ef(�<Sk�OVP���~��5�44 mV��C�dK

C)�"��:h��h��½�#��%îà

VbulkA390 V�k=��$ ef�@�?@�

-�390 V�105% = 410 V�<���%#�AT��U�p[d��K�����S�5Fñì<F

�-=�?@X����uAK#�$��%

Page 28: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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• ��(89(VLD)�NCP1910���?@�-A.

=9~£?�95%+�^F¤#�ef���U200 �A�íî�4��+T��.=9?�[�@

��­9#��%�e565��OTA����4

�@K�@ +,@i�C�����30 �A5�%ÙFVoutq�Ú{)�@(VLD)�+��VFBAVPREF�95%+�^F¤� ��200 �A�^ò�4�(Figure 52�IVLD)AVCTRL�æ9�2��

��%U��+T�PFC��AF¤#�Ê ���Ê�3Ù<A/��Fy#�$��%VCTRLR

��VFB�4a���4�� �4����

Figure 53�±�� �5�%ó.Ì�ï����

� �:��100 pF(��)��\�[d�EX����uCFB�12R����ܭ� U���

�#��%

−250

−200

−150

−100

−50

0

50

2 2.2 2.4 2.6 2.8 3

VFB

VC

TR

L p

in c

urre

nt (�A

)

230 �A raises VCTRL rapidlywhen VFB is below 95%VPREF

No DRV when VFB isabove 105% VPREF

Figure 53. VFB vs. Current Flowing in/out From VCTRL Pin

PFCokST

PFC�PFCokIJ���#1¤��`#��%• VbulkAPFCi4(C��(ÎãG�95%+�^F¤#�ef�q.¾��@<At�N�u((IVLD)�.c�{?� %

• PFC=��4>�?'��@�.c�{?� %

• LLC−HB������uh� �:��.È(tDEL1)�.c�{?� %

• LLC−HB�uh«�PFCokA)��pu�(� Q�VbulkAPG~£?+�^F¤#�ef�LLC−Hb������ª�� �:��.È(tDEL2)�.c�{?� %PFCokIJ��PFCC���A�eh�G��<SkPFG���A�e���95%�y0�$ �6�

N.�<��¿�5<$�6�)��<���%

Figure 54�¼�#�BY$%PFCokIJ��1¤�$¡�Q�ef�)��<���%

• PFCC���Auh#��

• $¡�Q�*�D34IJ�ÞI#��• *.�X{*|�p|(Auh#�%PFCokIJ��1¤�ef�N.�<���%• DRVAh���®#�PFCC���A���95%�y0�(VLD���~�����AN.)�

• PFCC���A���100%�y0�(�<Sk�PFCREG���~�����AN.�<T�)%

Page 29: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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Grand Reset

PFC_OK

Latch

S

RQ

Q

PFC_BO

+

+

��

���;�

<6: ���;�

��&

����;

&��

Figure 54. PFCok Signal Block Diagram

PFCU;�>V��Figure 52 +, 54¼�#�BY$%U���.C��VCTRLAVCTRL(min)+�^F¤#�ef��

PFC'*.������#���%��56A78#�ef�VCTRL�)��Ú6¤äV���%

• VCCF�-)�@p|(

• on/offR��34IJ

• u�È?XK��(q|�(TSD)

• *.�X{*|�p|(• PFCF�-wE

2Ç�$¡�Q�5é�ef�NCP1910�VCTRLR��N�#�.=9{)�@�200 �A�4�����34#��%

ICA½,���3�� ��1¤A�`���%• VCTRL�)��Ú6¤äV��VCTRLAVCTRL(min)+�^F¤#�PFCA^F$�r���Xu.@?5�®� �5�PFC�DRV���34���5�%

• 200 �A�4�{)�@�3456���#��%

3Û~�K�¾?X(*�C��q@�Xp�[

(OTA)�nA�VCTRL�ØTB�2����%

U���r���Xu.@?�ØTB�Ò­���MOSFET���- +,�4C(~C�v0 �:5�%�<Sk�i4(C��(h�A»V���%

W���K��./%XY%PFCZ�[./(UVP)

ICC7

ICC2

8% VPREF 12% VPREFVFB

OperatingShutdown

Figure 55. PFC Under−Voltage Protection

Figure 55�±�+���VFBAVPREF�8%+�^F¤#�ef���.C�K��(q|�#��%�

��-AVPREF�12%�y0 ����.C�:h��h���®#��%�-�����op��e565��NCP1910Ah�� ����?@�-

Vbulk�e�a��-Vin+�^�B�12IJVFB�

e�VPREF�8%���12%+�^�B<Z�Å<�

���%U�F�-wEB��°<����VFBA

N��Q12LMRFBUA3�[�56�< <��12?�[��e�+ #®QV����wE� U�5�%

\�8�[./(OVP2])NCP1910���?@�-�g�3�-wE�`��:��FBR�5�3�-wE�ô��^�1³�*�R��OVP2R��/0�$��%U�B������12LM�'d4(�+ #®QV��nÛ�wE� U�5�%Figure 56�±�+���FBR��OVP�ÄÞ#�ef�OVP2��1¤�3P�ð$A¦���%

• OVP2R�A��� wE&�'�*�D345�%OVP2A(dj� ��NCP1910�PFC�LLCAº}�^ª�� *�D34X&�'�<���%

• �å<ó.Ìñ/�» �:��A20 �s4�?�AOVP2���~���«�òn§���$��%

• OVP2���~���d4�~�C�-��VPREF�107%5�%ROVPU�ROVPL�LM���OVP2~£?�(á�< ��RFBU�RFBL�LM��� 

�� U�^;�5�%¿�ef�FBR��OVP�~£?��e��?@�-�105%5�A�OVP2�~£?��e��?@�-�107%�<���%OVP2�+��$~£?A'(<ef��U�

��:,�¬ó� U�A56��%U�OVP2�B�A©(<ef��OVP2R��N�� U��+T��U�B����x�{?56��%

Page 30: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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�����

���������

04>: ���;�

���,���3

�'��%

34 �� ����������

� ��#���!

Figure 56. PFC 2nd Over−Voltage Protection

PFC%^_PFC��e��VCTRL~£?�q­� U��+T�q�#��%VCTRLAtPFCabnormalG�12��#�VCTRL(max)�ô� Q�VCTRL(min) − 0.1 V+�^F¤� ��PFCAÇ����34#��%tDEL2G�+3«�LLCAK��(q|�#��%U��*�D34wE5�%U�B��°<����PFCC����^Xh�<#5LLCAh�#<$+��� U�5�%

LLC'(��

�59`abc(CCO)U��4]-7_µ��50 kHzQV1 MHz�5�h��;��� �9"��/0�$��%�Y#�=���2¹=� D4d�[4)�[A�U52P���(Figure 57�A�B)���� �:�LLC'*.���5�Î�<õ8IJ(ML�MU)��25 kHzQV500 kHz��5C.�D�E#��%CCO��RtR�QV4�� �4AÒ­� ��C.�D�E=��^2�� +��op��$��%

Page 31: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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�&&

��

��

.

���7�����

���!

�����'��

� �7(�

� �7(�

���7�����

���7�����

���,�

���7�����

&��'��7���7(�7��7(�

��

������? ���

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����'�%

)� #� �)���

��

9&1

����� @ ���0 ���,��

�&;�3 ��)���

���,��1

Figure 57. The Current Controlled Oscillator Architecture and Configuration

���

����?

�U��.��EX����uCt��Rt R�QV4�� �4�Ä×� �45¨����%��

�4iDT��U�����u��-AVCtmax��� �K����%��¹������'*.����x�{?� �:���'�.}�����

�4K�@���+T������%�.��EX����u��-Aê)�<��½,¨�u.@?A®� ����K�@���x�{?���%$¡�Q�“turn−off LLC”IJAõö� ��CtAN���7_µ���x�{?#��%�_p[d��K��5��Sh�=����TQ5��� U�A'(5�%kl÷��@h� +,uh=���] � U�^'(5�%U�V��*b����H��Figure 57�±�+���RtR��N�� iU��·�c�(���#���56��%S�@ +,uh=��5��¿�ö���+�<Èè��ÑAø������%

• SC.�D�E=����Rmin�LM��+T

������%12h�A<B�i4(C��(

¹�A�5�3Ê�$ ef��U�=����

#��%

Rmin �490 � 106VRt

Fmin

(eq. 22)

• @C.�D�E=���h�R���Rmax�Õ

� �] ���%

@=����3[(\[*��÷�-��ï�

�ÞZ��%

Rmax �490 � 106VRt

Fmax � Fmin

(eq. 23)

• LMRSS�����uCSS�ònfS����_�

�����i4(C��(¹��k=#��%

RSS �490 � 106VRt

FSS � Fmin

(eq. 24)

UU5�♦ VRt = 3.5 V♦ Fmin�S=��

♦ Fmax�@=��

♦ FSS�@i4(C��(XC.�D�E=�

Page 32: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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LLC%d2��e1FSTA,�-�-�(PGadj]f

PGout]fghiBOadj])Figure 22�±�+���NCP1910�VbulkAF�Ê

ef���_�����Ah�#<$+�wE� µ����� {*|�p|("�(BO)�/0�$��%���NCP1910�:ùAXe56�¦ U��¹���2�M�­V� �:��W�XE�'IJ(PGout)���#��%

PFCAuh#��Vbulk�.=9�-�95%�y0 �52�� ���UPFC_OKIJApu�(���%20 ms(tDEL1)I���PGoutR�A)��

<���%

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�3�[�56���#��%

• VbulkA�PadjR��d4�~�C�-5k=�

�~£?�5F¤#�ef5�%

U�~£?���e�BOadjR�5k=� LLC���34�-+�^�B<���%

#�AT���e����34XK���C5�

�Ç�PGAs$#��2�M�K��(q|���/A'(5¦ U��­V���%

• PGIJAs$� 2P��.£�(��12+��¹¡(PFC UVP)�PFC�e����a�*.�X{*|�p|(�+T�PFC�4>�?(A78#�ef5�%$¡��ef^��U�PFCokIJAF¤#�PGoutIJAN.�pu�(��

5 ms�.È(tDEL2)A®h#��%U��.È�G�A+3� ��LLC������.`�ª�56��%

uh�K��(34� +,2P�IJ�.È(tDE

L1 +,tDEL2)�=ê�P$���«�Ù��ÃZ[x@K��Ú5·¸#��%{*|�p|(X���~���«���ô���2P�IJ�.ÈAòn§���$��%• tBOK��VbulkABO~£?�y0�«�uh� IJ�.È5�%

• tBONOTOK��VbulkABO~£?+�^F¤#�«�uh� IJ�.È5�%

NCP1910��PFC�FBR�QVVbulk�âï�ß»#�U����#���-x�C"��#$�S

�v0��%Figure 22�±�� ��VREFR��

PGadjR��BOadjR�� +,E*�'���¦ 3³�LM(R1�R2�R3)A��~�ÆT�PGoutIJ

+,LLC{*|�p|(�~£?��=#��%

VPG �R2 � R3

R1 � R2 � R3

VREF

(eq. 25)

� Vbulk,PG RFBL

RFBU � RFBL

� Vbulk,PG VPREF

Vbulk,nom

VBO �R3

R1 � R2 � R3

VREF

(eq. 26)

� Vbulk,BO RFBL

RFBU � RFBL

� Vbulk,BO VPREF

Vbulk,nom

UU5�♦ VPG�PGadjR���-

♦ VBO�BOadjR���-

♦ VREF�d4�~�C�-(��5 V )♦ VPREF��PFC12OTA���Ud4�~�C

�-(��2.5 V)♦ Vbulk,PG��PGoutR�A3�[�56�< �

6��?@�-

♦ Vbulk,BO��LLC�{*|�p|(B�Auh� �6��?@�-

♦ Vbulk,nom��390 V<���e��?@�-

~25�~265��� ���~27�+�<R2�R3��ÑAú����%

R2

R3

�Vbulk,PG

Vbulk,BO

� 1 (eq. 27)

U�+��Vbulk,PG�Vbulk,BOA¯0V��Ç�C��[�#�R3�ÕÖ� ��~27+�R2�~26+�R1�ú: U�A56��%×0Å�Vbulk,nomA390 V�Vbulk,PGA340 V�Vbulk,BOA330 V�#��%R3�10 k��LM�ÕÖ� ��R2�303 ��<���%^È$��LM�#��300 ��ÕÖ#��%U�+��R1�13.3 k��<���%

Page 33: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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PFC_FB

”1” BONOTOK

”1” enables LLC”0” LLC is locked

GrandReset

LLC_BO

R

PFC_OK”1” is ok”0” notok

R

”1” after reset”0” when PG outdrops after 5 ms

LLC_BO

”1” PGNOTOK

+

+

LLC_PG

LLCenable

VREF

BOadj

PGadj

PGout

R1 R2

R3

VCC

VSB

PGI for supervisory

tBOK

tBONOTOK

tDEL1

tDEL2

20 ms

5 msTo close switch

at SS pin

SS is reset

Figure 58. The PG and BO Block Diagram for LLC

LLC�O;G�K�j�(CS/FF ])Figure 59�±�+���NCP1910�1�M�3�456�q�#�����#®QVwE� �:�*�a�(CS/FFR�)�/0�$��%

CS/FFR���-AVCS1C~�K�?'(��1 V)�y0 ��SS R���UC.�DA� V���

VSSAVSS_RST(��150 mV)+�^F¤� �5CSS���#��%U��+��LLC�C.�D�E=

��(ML�MU)A2�#��1��4�z{~£?��w�#��%(*�CÉû�+�<$3 !565��1��

4Aæç�Ò­#�ø�~£?��� ;�/A¦���%¿��:NCP1910��CS/FFR����.C(PFC�LLC�º})�üù��*�D#�ýúQVwE� �Ü­���~��VCS2(��1.5 V)�/0�$��%

Page 34: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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+

−S

R

Q

Q

Grand Reset

Latch

”1” to disable LLC and PFC driver,and pull down PFCok

+

−”1” to set the SR−latch topull low SS pin

PFC_BO

CS/FF

VCS1

VCS2

PFC_OVP2

Figure 59. The Fast Fault Input at CS/FF pin

LLCU;�>V��(SS])�_�����5���_"��æ�@�4A4� ���Z �:��i4(C��(A'(5�%NCP1910���1¤�4>�?(56�/0��½uhÆ�i4(C��(X����u�ª`���� �:�SSR�A�¿��$��%• LCC{*|�p|(Auh

• *.�X{*|�p|(����W�XE�'X���~���+T�tDEL2�.ÈA®h#�QV

�tDEL2G�A+3

• LLC��94>�?(a�5¦ CS/FFR���

-AVCS1+�^2�

• VCC�UVLO

• PFC�UVP

• on/offR��34IJ

• u�È?XK��(q|�(TSD)SSR��M�C.�DA� �i4(C��(X

����u���� ��VSSAVSS_RST(��150 mV)+�^F¤� �5�C.�D�� ����<�

��%U��+T��½uhÆ�i4(C��(X

����uAª`���#�Y��b�<i4(C��(��`56��%LLC"�Ah���®� ��SSR���UC.�DA�6�þ�i4(C��(X����uAi4(C��(LMRSS�� �RtR�QV�4�Ú6�#��%U��4�i4(C��(X����u�¨�#��LLC�h�=����B#��%i4(C��(X����uA¨�

� ��LLC'*.����=��A�¶�F¤#�Fmin�<���%^kû���������-A������ ��CCO�]-��¢�12?�[�Ú6�A���%

LLC>M1�(Skip]fBL�k�%l)NCP1910B5��" !565�=�����"�� �:YZ5<B�C���.X&�'G�st���Fy� �:��Figure 60�±�+���3[(\[*��~@��x0¡��� C��[X&�'h�(SkipR�)������#�$��%U�R�A�~@��F�-�q�� ���~@��-A½,2�� �5LLC���?C(MLR� +,MUR�)� ¡���%

+

Rt

SS

RminRmax RSS

CSSFeedbackopto−coupler

Skip

VSkip

Disable ML andMU

Figure 60. The LLC Skip Mode Configuration

Page 35: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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LLC��[F�+LNCP1910��LLC������2MMOSFET�;NN�;�<��-'*.���O#�$��%U���.C��2MMOSFET�¸¹<��(�-�

��56 2üUVLO"�^/0�$��%4)����EX'*.�Xx@K����.pC��

VbootR��HBR����Cboot����u5�����%U�����u�iU{�(C(*�[Xq.3�'5½¨����%4)����EU¹�600 Vdc�52�56 �:�400 V�PFC4)�(t�'XC�����P34*.�Xp[d��K���K5�%

�!"'(��

LLCAPGoutST(tDEL1AtDEL2)%mnoghipqo%rs

LLC�K¥�h�� �:��PFC��/A�T�$<$ef�LLC�uh56���%ÙPFCokIJÚx@K��5·¸#�+���VbulkA�e�?@�-�95%�y0 ���UPFCokIJ�N.�pu�(���%PFCokIJAN.�<T�«�LLCAuh� Æ�PFCC����ª`�.=� �:���.È(tDEL1)A®h#��%tDEL1G�A+3� ��PGout R�AN���LLC�'*.���(MLR��MUR�)��®#��%

ACa��Ú6¦6�*.�X{*|�p|(565K��(q|�A78#�ef�PGoutIJ�3�

[�56�<���%���Ë��.È(tDEL2)A®

h#��%tDEL2A+3� ��LLC�'*.�(MLR��MUR�)�ª�#��%

Figure 61��LLC�PGout�uhG +,ª�G�IJ�±#��%

PFC��/A��(PFCokAN.�pu�(� )��tDEL1(��20 ms)A�®���%U�IJG�A

+3� ����L[A�`���%

• PGoutR�A)��pu�(���%

• LLC'*.�(MLR��MUR�)Ah���®5

6��%

ACa��[*E�¦$�K��(q|�� ��VbulkAF¤#���L[A�`���%

• VbulkA�PGadjR�5��� PGIJ~£?��� ��PGout R��3�[�56�<���%

• VbulkA�LLC�ª�~£?(BOadj R�5��� BO~£?)��#�ef�LLC�ª�#��%VbulkA" !<�5À�Q�F¤#�ef��

PGout R�A����QV5 ms+3(tDEL2)«��

LLC'*.�(MLR��MUR�)Aª�#��%

*.�X{*|�p|(56�+T�K��(q|�A78� ��PFCokIJA[?q|�����L[A�`���%

• U��UPFCokIJA)��< ��PGout R��3�[�56�<���%

• LLC'*.�(MLR��MUR�)��PGoutR�A

3�[�56�<T�5 ms+3(tDEL2)«�ª�#��%

Vbulk

time

95%

LLC works

off

off

tDEL1

tDEL2

5 ms

PG level

20 ms

PGout

BO level

Figure 61. The Timing for tDEL1 and tDEL2

�N���W/W;(on/off])NCP1910�d&�(]-B��*�R��#���� on/offR��/0�$��%• on/offR�A1 V1¤�Ú6¤äV� ��PFCAh���®#��%VbulkA��~£?�95%�y0�QV20 ms+3#�«�LLCAuh#��%

• on/offR�A3V�y0 ����.C��¢�PFC�LLC�º}�ª�#��Fst�456���

#��%h�&�'�on/offR�����

Figure 62�±#��%

Page 36: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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On/off pin

State

ON

Von Voff On/off pin

ICC

TBD

< 600 �A

OFF

Figure 62. Remote on/off (on/off Pin)

VCCZ�[ 1(�-�(UVLO)U���.C��K¥<h��wÍ� �:��

VCCAF�Ê �6�"�Ah�#<$+�F�-

)�@p|(X{)�@��O#�$��%UVLO���~����VCCR���-�&å�#�VCCA

VCC(on)�y0 �NCP1910�h��;��#��%���~����VCCAC~�K�?'�À¤�

�6�áh�#<$+��¦ �Q��C�dKC(VCC(Hys))��T�$��%VCCAUVLO���~���¤M�C~�K�?'(VCC(min))+�^F¤� ��"�����34#��%U��Ñ�Figure 63�±#��%uh«�h�R���9 VQV20 V5�%

���

�����+

���A���B ���A �B

9��

1�&

C 044�.

���

Figure 63. VCC Under−Voltage LockOut (UVLO)���

�� ��%L+�>

K¥�h�� �:��VCCR��ÈB�1 nFý100 nF(��)��\�[d�EX����u�Ü­� U���#��%NCP1910�iU��5�.pC� �¡<�5�VCC(on)�VCC(min)���C�

dKC�SB<T�$��%#�AT��C���.��<��F�-�5NCP1910��.pC� U����#��%

t�uK��v1�w-

�Uu�È?"���NfUPQATSD~£?�y0 ��"����(X'*.{���x�{?#���C.�D�3456�w�#��%

PQA��110°C(�<Sk�TSD − TSDhyste)1¤�F¤� �����A.c�{?���%u�È?XK��(q|���þ7�<3�56�uÿ� ��.C������ �:��¿��$��%

5 V�;<=>�[VREFR���XY<(±2%��) 5 Vd4�~�C�

-���#��%#�AT��LLC�������W�XE�'�{*|�p|(� +,PFC�=��4>�?'��@X~£?(FoldR�)��LM¹Áµ5XY<d4�~�C�-���56��%

Page 37: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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�1x./A�'1�

2Çx@K��5·¸#�+���PFC�LLC�º}�*�D34� ��3P���&�'A¦�

��%

• PFC��e

• PFC�OVP2

• LLC�CS/FFR�AVCS2�y0�

NCP1910����3P�*�D34X&�'��}¶���#�$��%

• VCC�du.@?#��%P���VCC�$T�

�VCC(min)+�FB#�QV�½,VCC(on)+��

B#��%

• d&�(on/offB��du.@?#��%P���on/offR��N.�#�QV½,)��¥�|0��%

• *.�X{*|�p|(B��du.@?#��%U��ACa��[*E��Q¦$�QV�¤#§�U�5`�U�A56��%

ORDERING INFORMATION

Device Version Marking Package Shipping†

NCP1910A65DWR2G 65 kHz − A NCP1910A65 SOIC 24WB Less Pin 21(Pb−Free)

1000 / Tape & Reel

NCP1910B65DWR2G 65 kHz − B NCP1910B65 SOIC 24WB Less Pin 21(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

Page 38: 24WB Less Pin 21 DW SUFFIX CASE 752AB - onsemi · M1 M2 C14 L2 D6 D9 T1 C4 Vout R11 R30 U1 C7 R10 U2B R18.. R9 R17 R8 R16 C3 Over ... Bulk 12 V aux. on/off FB Vcc R21 Vref Power Good

NCP1910

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PACKAGE DIMENSIONS

SOIC−24 WB LESS PIN 21CASE 752AB−01

ISSUE O

b

E

����� �

SEATINGPLANE

A1 e

M

L

DETAIL A

END VIEW

h�

NOTES:1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALLBE 0.10 mm TOTAL IN EXCESS OF ’b’ AT MAXIM-UM MATERIAL CONDITION.

4. DIMENSIONS b AND c APPLY TO THE FLAT SEC-TION OF THE LEAD AND ARE MEASUREDBETWEEN 0.10 AND 0.25 FROM THE LEAD TIP.

5. DIMENSIONS D AND E1 DO NOT INCLUDE MOLDFLASH, PROTRUSIONS OR GATE BURRS. MOLDFLASH, PROTRUSIONS OR GATE BURRS SHALLNOT EXCEED 0.15 mm PER SIDE. INTERLEADFLASH OR PROTRUSION SHALL NOT EXCEED0.25 PER SIDE. DIMENSIONS D AND E1 AREDETERMINED AT DATUM H.

6. DIMENSIONS D AND E1 ARE DETERMINED ATTHE OUTERMOST EXTREMES OF THE PLASTICBODY EXCLUSIVE OF MOLD FLASH,PROTRUSIONS, TIE BAR BURRS, OR GATEBURRS BUT INCLUSIVE OF ANY MOLDMISMATCH BETWEEN THE TOP AND BOTTOM OFTHE PLASTIC BODY.

7. DIMENSIONS A AND B ARE TO BE DETERMINEDAT DATUM H.

8. A1 IS DEFINED AS THE VERTICAL DISTANCEFROM THE SEATING PLANE TO THE LOWESTPOINT ON THE PACKAGE BODY.

9. THIS CHAMFER IS OPTIONAL. IF IT IS NOTPRESENT, THEN A PIN 1 IDENTIFIER MUST BELOCATED IN THE INDICATED AREA.

L2

NOTES 3 & 4

PIN 1

121

24 13

TOP VIEW

DIM MIN MAXMILLIMETERS

A 2.35 2.65

b 0.31 0.51

e 1.27 BSCh 0.25 0.75

J 0.20 0.33

A1 0.10 0.29

L 0.40 1.27

M 0 8 ��

D

E1

SIDE VIEW

11.00

23X0.52

23X1.62

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*D 15.40 BSCE 10.30 BSC

E1 7.50 BSC

L2 0.25 BSC

RECOMMENDED

D

INDICATOR� �

NOTE 7

���� � ��� �

���� � �

NOTES 5 & 6

24X2X

2X

B

A

NOTE 7

2X

���� �

CA

NOTE 8

���� � x 45

c

NOTE 9

DETAIL A

C

H

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLCreserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for anyparticular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including withoutlimitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applicationsand actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLCdoes not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended forsurgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation wherepersonal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC andits officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufactureof the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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