automatic multi storied car parking system report

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automatic multi storied car parking

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Chapter 1Introduction

1.1 IntroductionAutomatic multi storied car parking system helps to minimize the car parking area. In the modern world, where parking-space has become a very big problem and in the era of miniaturization, it is become a very crucial necessity to avoid the wastage of space in modern, big companies and apartments etc. In places where more than 100 cars need to be parked, this system proves to be useful in reducing wastage of space. This Automatic Car Parking System enables the parking of vehicles, floor after floor and thus reducing the space used. Here any number of car scan be parked according to the requirement. This makes the system modernized and even a space-saving one. This idea is developed using 8051 Microcontroller. Here program is written according to this idea using 8051.

1.2 Basic ideaA display is provided at the ground floor which is basically a counter that displays number of cars in each floor. It informs whether the floors are fully filled with the cars or is it having place in a particular floor or not. In this project we have provided three floors of a building for car parking. Maximum storage capacity of each floor is given as five. Storage capacity can be changed according to the requirement. As soon as a car is placed in a particular floor, the display counter at the ground floor increments as to indicate the floor capacity has decreased by one. We are using two light sensors at each floor( one at the entrance and one at the exit) which sense the presence of car and tell the counter to decrease or increase.The project has been divided into following sections:-1. Display section2. Indicator & Beeper section3. Sensor section4. LCD section1.2.1 Display sectionThis section displays the floor number along with the number of cars which has been already parked in that particular floor. So whenever a car is ready to either come down or go up the program either decrements the count or increments the count automatically according to the going up or coming down of a car. Display section is done by interfacing with 8255(PPI) of 8051.Here 3 ports of 8255 are connected to three 7-segment display.

1.2.2 Indicator & beeperWhen a person tries to enter the lift irrespective of finding the display section to be 05 (means the floors are already filled), program sends a signal to Beeper and indicator section and it starts beeping indicating that he is not supposed to enter the lift since all the floors are already filled.

1.2.3 Sensor sectionHere we have used 2 light sensors (LED $ LDR) at each floor. One is for the entrance and another for exit. In normal condition the light from LED is sensed by the LDR but when a car comes in between the transmitter (LED) and receiver (LDR) the LDR does not receive any light and its output changes accordingly which is sent to the microcontroller which hence increment or decrement the value of the counter.

1.2.4 LCD SectionIn this project LCD is used to display some messages which is useful to car owners. Here 2X16LCD (Liquid Crystal Display) is used. This is used to display messages like

WELCOME TO CAR PARKING SYSTEMFLOOR IS FULL

1.3 Block Diagram

Figure 1.1Block Diagram of Project

Chapter 2Project Overview

2.1 Circuit DiagramFigure 2.1Circuit diagram4.2 Circuit DescriptionThe controlling part of the system is 8051 microcontroller. There are 6 sensors, two mounted on each floor(one for entrance and one for exit). The sensors are mounted in through bea configuration. When a car comes in between the sensor transmitter and receiver the output of the sensor becomes 0. This output is given to the microcontroller. The programming is done in such a way that whenever the output of a sensor changes from 1 to 0 the counter value gets increase or decrease (depending on where the sensor is i.e.: at entrance or at exit).The latch (74HCT373) is provided to demultiplex the higher order address lines of the microcontroller. The data lines are used to fetch data to the 8255 and the address lines (demultiplexed) are used for the chip select of the 8255. The chip selection of the 8255 is done by using an 8 input nand gate (74HC30) and a 3-8 decoder(74HC138).There are 3 seven segment display (LT542) used here, each for showing number of cars parked at a floor. The LCD is used to display some meaningful messages. The displays are connected to ane 8255 and the LCD to another one.

Chapter 3Components Description

3.1 Components ListS. NO.Name of ComponentSpecificationsQuantityPRICETOTAL COST

1Resistors330122

10 k122

8.2 k11

2Capacitors10 f112

33 pf212

3ICLM324 21020

AT89S5216060

74HCT37312020

8255A260120

74HC3012020

74HC13812020

4LDR6848

5LED12112

67 Segment DisplayLT54231030

7LCD12 X 71150150

8Crystal Oscillator24 MHz1

9Variable Resistor20 k6318

Table 3.1Components List3.2 8051 Microcontroller(AT89S52)The 8051 microcontroller generic part number actually includes a whole family of microcontrollers that have numbers ranging from 8031 to 8751.The block diagram of the 8051shows all of the features unique to microcontrollers:Internal ROM and RAM I/O ports with programmable pins Timers and counters. Serial data communication The block diagram also shows the usual CPU components program counter, ALU, working registers, and the clock circuits. The 8051 architecture consists of these specific features: 8 bit CPU with registers A and B 16 bit PC &data pointer (DPTR) 8 bit program status word (PSW) 8 bit stack pointer(SP) Internal ROM or EPROM (8751)of 0(8031)to 4k(8051) Internal RAM of 128 bytes 4 register banks, each containing 8 registers 80 bits of general purpose data memory 32 input/output pins arranged as four 8 bit ports:P0-P3 Two 16 bit timer/counters:T0-T1 Two external and three internal interrupt sources Oscillator and clock circuits

A pin out of the 8051 packaged in a 40 pin DIP is shown below

Figure 3.18051 microcontroller

3.3 8255 PPIThe 8255A programmable peripheral interface (PPI) implements a general-purpose I/O interface to connect peripheral equipment to a microcomputer system bus. The core's functional configuration is programmed by the system software so that external logic is not required to interface peripheral devices. Its has following features Three 8-bit Peripheral Ports - Ports A, B, and C Three programming modes for Peripheral Ports: Mode 0 (Basic Input/Output), Mode 1 (Strobed Input/Output), and Mode 2 (Bidirectional) Total of 24 programmable I/O lines 8-bit bidirectional system data bus with standard microprocessor interface controls

3.4 3-8 Decoder(74HCT138)The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It accepts three binary weighted address inputs (A0, A1and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7). It features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. The 74HC138; 74HCT138 can be used as an eight output demultiplexer by using one ofthe active LOW enable inputs as the data input and the remaining enable inputs as strobes. Not used enable inputs must be permanently tied to their appropriate active HIGH- or LOW-state. It ha following features:- Demultiplexing capability Multiple input enable for easy expansion Complies with JEDEC standard no. 7A Ideal for memory chip select decoding Active LOW mutually exclusive outputs ESD protection: Specied from 40 C to +85 C and from 40 C to +125 C

Figure 3.274HCT1383.5 Latch(74HC373)The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. It is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes.When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. It has following features and benefits:- 3-state non-inverting outputs for bus oriented applications Common 3-state output enable input Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573 ESD protection: Specified from 40 C to +85 C and from 40 C to +125 C

Figure 3.374HC3733.6 Nand Gate IC(74HC30)The 74HC30; 74HCT30 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC30; 74HCT30 provides a quad 8-input NAND function. It has following features and benefits:- Input levels: For 74HC30: CMOS level For 74HCT30: TTL level ESD protection: Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C

Figure 3.474HC30

3.7 ResistorsResistors are the electronic components which opposes current. Resistors obey ohm law. Different kind of result comes with respect to application of various voltages.

Figure 3.5Resistor

3.8 CapacitorsA capacitor is an electrical or electronics device that can store energy the electric field between a pair of conductors. This process of

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