application of the drs chip for fast waveform digitizing

Application of the DRS Chip for Fast Waveform Digitizing

Stefan RittPaul Scherrer Institute, Switzerland

March 14th, 2009 TIPP09 Tsukuba 2

Question ?

4 channels5 GSPS1 GHz BW8 bit (6-7)15k$

4 channels5 GSPS1 GHz BW8 bit (6-7)15k$

4 channels5 GSPS1 GHz BW11.5 bits1k$USB Power

4 channels5 GSPS1 GHz BW11.5 bits1k$USB Power


Switched Capacitor Array

Shift RegisterClock

IN

Out

“Time stretcher” GHz MHz“Time stretcher” GHz MHz

Waveform stored

Inverter “Domino” ring chain0.2-2 ns

FADC 33 MHz


Switched Capacitor Array

•Cons

• No continuous acquisition

• Limited sampling depth

• Nonlinear timing

•Pros

• High speed (6 GHz) high resolution (11.5 bit resol.)

• High channel density (9 channels on 5x5 mm2)

• Low power (10-40 mW / channel)

• Low cost (~ 10$ / channel)

t t t t t

Goal: Minimize Limitations


DRS4

• Designed for the MEGexperiment at PSI,Switzerland

• UMC 0.25 m 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard

• 8+1 ch. each 1024 cells

• Differential inputs,differential outputs

• Sampling speed 500 MHz … 6 GHz,PLL stabilized

• Readout speed 30 MHz, multiplexedor in parallel

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

WSROUT

CONFIG REGISTER

RSRLOAD

DENABLE

WSRIN

DWRITE

DSPEED PLLOUT

DOMINO WAVE CIRCUIT

PLL

AGND

DGND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8/MUXOUT

BIASO-OFS

ROFSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS


How to minimize dead time ?

• Fast analog readout: 30 ns / sample

• Parallel readout

• Region-of-interestreadout

• Simultaneouswrite / read

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

W SRO UT

CO NFIG REGISTER

RSRLO AD

DENABLE

W SRIN

DW RITE

DSPEED PLLO UT

DO MINO WAVE CIRCUIT

PLL

AGND

DG ND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OU T0

OU T1

OU T2

OU T3

OU T4

OU T5

OU T6

OU T7

OU T8/MUXOUT

BIASO-O FS

RO FSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS

AD922212 bit

8 channels


ROI readout mode

readout shift register

Triggerstop

normal trigger stop after latency

Delay

delayed trigger stop

Patent pending!

33 MHz

e.g. 100 samples @ 33 MHz 3 us dead time

300,000 events / sec.

e.g. 100 samples @ 33 MHz 3 us dead time

300,000 events / sec.


Daisy-chaining of channels

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Domino Wave

1

clock

0

1

0

1

0

1

0

enableinput

enableinput

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Domino Wave

1

clock

0

1

0

1

0

1

0

enableinput

enableinput

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling

depth

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling

depth


Simultaneous Write/Read

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

0

FPGA

0

0

0

0

0

0

0

1 Channel 0

Channel 11

Channel 0 readout

8-foldanalog multi-event

buffer

Channel 21

Channel 10

Expected crosstalk ~few mVExpected crosstalk ~few mV


Trigger an DAQ on same board

• Using a multiplexer in DRS3, input signals can simultaneously digitized at 65 MHz and sampled in the DRS

• FPGA can make local trigger(or global one) and stop DRSupon a trigger

• DRS readout (6 GHz samples)though same 8-channel FADCs

an

alo

g fro

nt e

nd

DRSFADC12 bit

65 MHzM

UX FPGA

trigger

LVDS

SRAM

DRS4

glo

bal tr

igger

bu

s

“Free” local trigger capability without additional hardware

“Free” local trigger capability without additional hardware

DRS4 Performance

Test Results


Bandwidth

Bandwidth is determined by bond wire and internalbus resistance/capacitance:

850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)

850 MHz (-3dB)

QFP package finalbus width

SimulationMeasurement


Timing jitter

t1 t2 t3 t4 t5

• Inverter chain has transistor variations ti between samples differ “Fixed pattern aperture jitter”

• “Differential temporal nonlinearity” TDi= ti – tnominal

• “Integral temporal nonlinearity”TIi = ti – itnominal

• “Random aperture jitter” = variation of ti between measurements

• Inverter chain has transistor variations ti between samples differ “Fixed pattern aperture jitter”

• “Differential temporal nonlinearity” TDi= ti – tnominal

• “Integral temporal nonlinearity”TIi = ti – itnominal

• “Random aperture jitter” = variation of ti between measurements

TD1 TI5


Fixed jitter calibration

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TDi on a statistical basis

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TDi on a statistical basis


Sine Curve Fit Method

S. Lehner, B. Keil, PSI

i

j

500

0

1024

0

22 min)))2

sin(((j i

jijj

jji of

iay

yji : i-th sample of measurement jaj fj j oj : sine wave parametersi : phase error fixed jitter

“Iterative global fit”:

•Determine rough sine wave parameters for each measurement by fit

•Determine i using all measurements where sample “i” is near zero crossing

•Make several iterations

“Iterative global fit”:

•Determine rough sine wave parameters for each measurement by fit

•Determine i using all measurements where sample “i” is near zero crossing

•Make several iterations


Fixed Pattern Jitter Results

• TDi typically ~50 ps RMS @ 5 GHz

• TIi goes up to ~600 ps

• Jitter is mostly constant over time, measured and corrected

• Residual random jitter 3-4 ps RMS

Applications of the DRS4 Chip

What can we do with this technology?


Flash ADC Technique

60 MHz12 bit

Q-sensitivePreamplifierPMT/APD

WireShaper

• Shaper is used to optimize signals for “slow” 60 MHz FADC• Shaping stage can only remove information from the signal• Shaping is unnecessary if FADC is fast enough• All operations (CFD, optimal filtering, integration) can be done digitally

• Shaper is used to optimize signals for “slow” 60 MHz FADC• Shaping stage can only remove information from the signal• Shaping is unnecessary if FADC is fast enough• All operations (CFD, optimal filtering, integration) can be done digitally

FADC

TDC

5 GHz12 bit

TransimpedancePreamplifier FADC

PMT/APDWire

DigitalProcessing

Amplitude

Time

BaselineRestoration


How to measure best timing?

Simulation of MCP with realistic noise and different discriminatorsSimulation of MCP with realistic noise and different discriminators

J.-F. Genat et al., arXiv:0810.5590 (2008)


On-line waveform display

click

templatefit

pedestalhisto

848PMTs

“virtual oscilloscope”“virtual oscilloscope”


Pulse shape discrimination

)tt[...]θ.. )tθ(td)/τt(te

/τ)t(te i/τ)t(t

eAV(t)r00

000

CsB

Leading edge Decay time AC-coupling Reflections

Example: / source in liquid xenon detector (or: /p in air shower)Example: / source in liquid xenon detector (or: /p in air shower)


-distribution

= 21 ns

= 34 ns

Waveforms can be clearly

distinguished

= 21 ns

= 34 ns

Waveforms can be clearly

distinguished


Template Fit

• Determine “standard” PMT pulse by averaging over many events “Template”

• Find hit in waveform

• Shift (“TDC”) and scale (“ADC”)template to hit

• Minimize 2

• Compare fit with waveform

• Repeat if above threshold

• Store ADC & TDC values

Experiment500 MHz sampling

Pile-up can be detected if two hits are separated in time by ~rise time of signal

Pile-up can be detected if two hits are separated in time by ~rise time of signal


Timing Big Systems I

GlobalClock

~20 MHz

ReferenceClock forDRS4 PLL2.5 MHz

ReferenceClock fortiming channel

LMK03000 Clock Conditioner(National Semiconductor)

LMK03000 Clock Conditioner(National Semiconductor)

Jitter: 400 fsJitter: 400 fs


Timing Big Systems II

Channel 0

Domino Wave

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

PLLLMK03000

Experiment wideglobal clock

DRS4Chip

•Global clock locks all Domino Wavesto same frequency and phase

•Residual random jitter: 25 ps

•Even better timing can be obtained by clock sampling

•MEG Experiment: Single LVDSclock distributed over 9 VMEcrates


Experiments using DRS chip

MAGIC-II 400 channels DRS2MAGIC-II 400 channels DRS2MEG 3000 channels DRS2upgraded to DRS4 soon

MEG 3000 channels DRS2upgraded to DRS4 soon

BPM for XFEL@PSI1000 channels DRS4 (planned)

MACE (India) 400 channels DRS4 (planned)MACE (India) 400 channels DRS4 (planned) PETPET


Availability

• DRS4 can be obtained from PSI on a “non-profit” basis

• Delivery “as-is”

• Costs ~ 10-15 USD/channel (1000-1500 JPY)

• USB Evaluation board as reference design

• VME boards from industry in 2009

32-channel 65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz

32-channel 65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz


Conclusions

• Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future

• DRS4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11.5 bit vertical resolution, 4 ps timing resolution

• ~4000 DRS channels already used in several experiments, hope that other experiments can benefit from this technology

http://drs.web.psi.ch


Datasheet

http://drs.web.psi.ch/datasheetshttp://drs.web.psi.ch/datasheets


Signal-to-noise ratio (DRS3!)

“Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA

SNR:

1 V linear range / 0.35 mV = 69 dB (11.5 bits)

“Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA

SNR:

1 V linear range / 0.35 mV = 69 dB (11.5 bits)

AN

AL

OG

OU

TP

UT

[V

]

BIN NUMBER0 200 400 600 800 1000

0.48

0.49

0.5

0.51

0.52

Crosstalk from trigger signal

OC

CU

RE

NC

E

OUTPUT VOLTAGE [V]0.48 0.49 0.5 0.51 0.520

20

40

60

80

100

120

140

160

180

200

OC

CU

RE

NC

E

OUTPUT VOLTAGE [V]0.48 0.49 0.5 0.51 0.520

20

40

60

80

100

120

140

160

180

200

OffsetCorrection


Interleaved samplingdela

ys

(167p

s/8 =

21ps)

G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)

6 GSPS * 8 = 48 GSPS

Possible with DRS4 if delay is implemented on PCBPossible with DRS4 if delay is implemented on PCB


Lat

ch

Lat

ch

Lat

ch

Lat

ch

Constant Fraction Discr.

Lat

ch

12 bit

Clock

+

+

MULT

Lat

ch

0

&<0

Delayedsignal

Invertedsignal

Sum

application of the drs chip for fast waveform digitizing

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