analog-to-digital conversion || digital-to-analog conversion

Chapter 7Digital-to-Analog Conversion

Abstract The two most important architectures for constructing a digital-to-analogconverter are the unary and binary approach. Both approaches have their merits.Next to the architecture, the second choice is the domain in which the converter isrealized: voltage, current, charge, or time.

Realizations in all these domains are discussed and their specific behavior isanalyzed. The resistor string is an important conversion element as it constitutesthe digital-to-analog function in a flash converter. Its dynamic behavior is essentialfor reaching high-speed performance. The binary counterpart of this converter isthe R-2R architecture. The current-steering topology is the dominant realization forfast stand-alone digital-to-analog conversion. The properties of this converter aredescribed and analyzed.

Charge domain converters are mostly applied in lower-performance, low-powerapplications. Various topologies allow to choose between low area or betterperformance.

A special section is dedicated to error sources and methods to improve theperformance. The dynamic element matching, current calibration and data weightedaveraging methods are explained.

A number of examples details the design considerations and choices. Lay-outexamples of commonly used structures are presented.

Digital-to-analog converters fulfill two important roles in the data conversion chain.A digital-to-analog converter is needed at the end of the chain for converting thedigital signal back into the physical domain. Next to that every analog-to-digitalconverter needs some form of digital-to-analog conversion for its operation. Thesetwo functions directly influence the requirements posed on the digital-to-analogconversion. A digital-to-analog converter that has to deliver a signal to the physicalworld needs to act in the continuous time domain, and the signal has to show a highquality at every time moment. Moreover the signal must be delivered at some powerlevel to a load impedance.

M.J.M. Pelgrom, Analog-to-Digital Conversion, DOI 10.1007/978-1-4614-1371-4 7,© Springer Science+Business Media, LLC 2013

265

266 7 Digital-to-Analog Conversion

In an analog-to-digital converter the value delivered by the digital-to-analog con-verter is relevant only at a few (perhaps only one) time moments. The performanceon other time moments is not critical. Together with a minimum demand on thedrive capabilities, the demands of this application on the converter are mostly muchless challenging.

The application constraints limit the freedom of the choice of the architectureand the physical domain. In the next section of this chapter, the architectural andphysical domain options are analyzed. Then some realizations of digital-to-analogconverters per domain illustrate the combination of these aspects.

7.1 Unary and Binary Representation

A reference quantity forms the basis for the digital-to-analog conversion. The nextstep is the subdivision of this reference in fractions that allow the generation of aquantity corresponding to an LSB. Of course it is also possible to generate directlya reference of the size of an LSB and multiply this value. However, this willalso multiply the noise and interference. A full-scale reference value reduces thesesensitivities and results in the best performance.

The two most commonly used techniques for combining elementary units createdby a reference are the unary and binary representations. Figure 7.1 shows bothtechniques.

Unary representation uses a series of 2N identical elements. A unary numericalvalue is created as:

Bu =i=2N−1

∑i=0

bi = b0 + b1 + b2 + · · ·+ b2N−1, (7.1)

where each coefficient bi equals either “0” or “1.” The analog equivalent is formedby summing copies of the physical equivalent ALSB of an LSB:

Fig. 7.1 Two basictechniques for digital–analogconversion: unary and binaryrepresentations. For bothrepresentations two signalsare shown corresponding to avalue of 15 and 16 LSBs

7.1 Unary and Binary Representation 267

A =i=2N−1

∑i=0

biALSB,i = b0ALSB,0 + b1ALSB,1 + b2ALSB,2 + · · ·+ b2N−1ALSB,2N−1.

(7.2)

A 1 LSB higher value can easily be created by adding one new element to theprevious elements. The obvious advantage of this method is, that it provides anabsolute guarantee on monotonicity (see Fig. 5.5). A practical implementation willconsists of 2N elements (resistors or current sources) attached to an extensiveswitching matrix. A converter based on unary coding will grow exponentially withN. Till N = 10 . . .12 unary coded converters will result in a good, and economicallyusable solution. This technique can be applied to resistor strings, current sourcearrays, capacitor arrays, and in timing (counting conversion).

In order to avoid the exponential growth of components in a unary architecture,the exponential behavior must be included in the representation itself. In a binarystructure the elements are chosen such that the resulting voltages or currents forman exponential series:

Bb =i=N−1

∑i=0

bi2i = b0 + b121 + b222 + · · ·+ bN−12N−1 (7.3)

or in the physical domain:

A =i=N−1

∑i=0

biALSB+i = b0ALSB + b1ALSB+1 + b2 + · · ·+ bN−1AMSB. (7.4)

As a switch has two positions, it is practical (but not necessary) to choose 2as a base. The example in Fig. 7.1 shows a series of elements with the values:ALSB,ALSB+1, . . . ,AMSB= 1, 2, 4, 8, and 16. In the first binary-coded situation, thedark-colored elements add up to the value of 15. After an increment, all elementschosen up to then must be switched off and the element of value 16 is switched on(as shown in the lower part of Fig. 7.1). The implicit disadvantage of this method isthe transition from one value to another value, at codes where many bits flip (e.g.,01111→10000). Although most transitions will result in a controlled LSB change,the midrange transition will cause the highest valued element to switch on and allother elements to switch off. Both values should differ the physical equivalent ofone LSB; however, errors in the physical quantities ALSB,ALSB+1, . . . can easilycreate deviations. If a higher exponent element is smaller than the sum of the lowerexponential elements, a non-monotonicity in the transfer curve will arise. In thiscase an increment on the digital input code will result in a decrementing analogoutput. In a control loop instability around such a non-monotonicity may occur andupset the system.

Binary-coded converters can be designed with low area and power consumption.But the problems with the transitions limit the performance. Another inherentpotential issue with binary-coded circuits arises from the nonlinear relation between


Table 7.1 Various forms of digital representation

Straight binary Two’s complement Sign+magnitude Gray coded

15 1111 7 0111 7 0111 15 100014 1110 6 0110 6 0110 14 100113 1101 5 0101 5 0101 13 101112 1100 4 0100 4 0100 12 101011 1011 3 0011 3 0011 11 111010 1010 2 0010 2 0010 10 11119 1001 1 0001 1 0001 9 11018 1000 0 0000 0 0000 8 1100

7 0111 −1 1111 0 1000 7 01006 0110 −2 1110 −1 1001 6 01015 0101 −3 1101 −2 1010 5 01114 0100 −4 1100 −3 1011 4 01103 0011 −5 1011 −4 1100 3 00102 0010 −6 1010 −5 1101 2 00111 0001 −7 1001 −6 1110 1 00010 0000 −8 1000 −7 1111 0 0000

the number of switched blocks and the output (e.g., for “15” four units are switchedon, for “16” only one unit, for “17” and “18” two units.) Switching errors have nocorrelation with the code. Dynamic errors may occur as a result.

Both techniques, unary and binary coding, are applied in practical design. In thecase of converters with a high resolution the problem with the above schemes is thelarge number of units involved in a unary design or the wide range of binary valuesfor a binary-coded DA converter. Segmentation is generally applied to circumventthese problems: a converter of N-bit resolution is subdivided into a cascade of 2sub-converters of M and N−M bits. Also partitioning in more than two segments ispossible. For converters with high resolution, segmentation allows combining unaryand binary techniques: a 16-bit converter can be build effectively by designing the6 MSBs in a 64-element unary array each with a value of 210ALSB. A 10-bit binaryarray is coupled to the unary array and will code for the lower 10 LSBs. This set-upassumes that a 10-bit accuracy in a binary architecture can be reached. Examples ofsegmentation are found in Sects. 7.3 and 7.8.1

Most digital-to-analog (sub) schemes can be classified along the above architec-tural split. There are a few deviating forms such as ternary coding (+1,0,−1), thatare sometimes used in combination with sign/magnitude representation.

Many implementations have been reported in the older literature [129–134],illustrating the basic concepts.

7.1 Unary and Binary Representation 269

7.1.1 Digital Representation

The unary and binary structures from the previous section assume a positive signal.Of course most systems use signals with negative values as well. There are severalways to represent negative signals in a conversion process. The choice how torepresent the signal will influence several aspects of the conversion and of the analogand digital processing. Table 7.1 shows various representations of digital signals.1

The straight binary code in the first column is well suited for positive signals.Negative signals can be used if the entire scale is shifted by half of the full amplitude.In this “two’s-complement” representation, the mid-level value is the virtual zero. Inthe digital domain, now the positive and negative signals can be properly handled.Addition and subtraction can be executed without prior knowledge of the signsof the operands. Multiplication requires the digital numbers to be extended tofit a format corresponding to the result. Positive numbers are extended by zerosand negative values with ones. A direct translation of a “two’s-complement” codein the analog domain requires two analog power supplies. This is mostly not aneconomical solution; therefore the code “0000” corresponds in the analog domainwith half of the reference value. Now small signals in the analog domain movearound half of the reference value. This costs power and noise and other artifactsassociated with half of the reference value deteriorate the signal-to-noise ratio.For example, in current digital-to-analog converters, half of the reference valuecorresponds to half of the maximum current. Thereby a zero-valued signal will showthermal and 1/ f noise which is associated to this current. Obtaining a good signal-to-noise ratio for small signals is made difficult by the choice for two’s-complementrepresentation.

The “sign-and-magnitude” code is linked to the design style in analog hardware.The MSB of the code is the sign and the remaining part of the code is the amplitudeof the signal. From a circuit design point of view the MSB signal can directly beused to switch e.g., a polarity switch in a digital-to-analog converter. The amplitudecomponent of a “sign-and-magnitude” code is straight binary. Consequently thiskind of code allows implementations that avoid problems with noisy half-referencevalues. In the digital domain this code is less pleasant: a circuit will be needed todecode this signal in a format that can be processed.

If a “sign-and-magnitude” signal is rounded or truncated in the digital domainwith simple rounding or truncation rules an error will occur; see Fig. 7.2. In thecase of rounding or truncation for a “straight binary” or “two’s-complement” signaltruncations of positive and negative numbers will result in a shift in the samedirection. For “sign-and-magnitude” signals the positive and the negative part of thesignal will reduce in amplitude and shift toward zero. Such straightforward roundingor truncation will give a cross-over problem near zero and a distortion component.

1Many more representations exist; this table only lists the ones used in this book.


Fig. 7.2 Basic truncation or rounding creates distortion near the zero code

Table 7.2 Various forms of analog representation and physical domains

Unary Binary

Voltage Resistor string R-2RFlash ADC Low-performance DAC

Current Current matrix Current splitting

High bandwidth DAC

Charge/ capacitor Capacitor bank Capacitor bankLow-power DAC

Time PWM, SD mod Limited by distortionLow-bandwidth DAC

In italic the main application area is indicated

7.1.2 Physical Domain

In the physical domain the output value of a digital-to-analog converter can beformed using voltages, currents, charges, or time. In each of these physical or analogdomains both unary and binary architectures can be used; see Table 7.2.

Voltages can be subdivided by means of resistors. The upper left scheme ofFig. 7.3 shows the concept: a digital decoder selects one of the switches thatdetermines the output voltage. In a similar manner a row of current sources andswitches implement a unary current source digital-to-analog converter. Convertersoperating in the charge domain use capacitor banks and unary implementations inthe time domain use pulse trains that switch on or off a physical unit.

Creating exponential sequences of physical quantities is less simple. In thevoltage domain “R-2R” structures are applied (see Sect. 7.2.4), while in the current

7.2 Digital-to-Analog Conversion in the Voltage Domain 271

a b

dc

Fig. 7.3 Unary (upper schemes) and binary forms of resistor string and current source digital-to-analog conversion

domain currents can be split by means of transistor arrays. Capacitor arrays can usethe R-2R principle as well. Using pulses of exponentially increasing lengths in thetime domain is realizable; however, it is unclear what advantage that brings.

Next to the combination of signal representation and physical domains Table 7.2shows the major application area. Except for binary-weighted timing all principlesfind usage.

7.2 Digital-to-Analog Conversion in the Voltage Domain

7.2.1 Resistor Strings

A practical example of a unary digital-to-analog converter in the voltage domainconsists of a series connection of resistors between two reference voltages, seeFig. 7.4. These structures are called resistor ladders or resistor strings. A resistorladder can be turned into a digital-to-analog converter if a selection and switchingnetwork is connected to the resistor ladder taps. A buffer is needed to lower theoutput impedance.

An important problem in this resistor string is the variation of the impedance ofthe resistor ladder: on both ends the impedance is equal to the impedance of thereference source and close to zero. At a code close to the middle of the ladder theimpedance is equal to the parallel connection of two half-ladders. If m = 0 . . .M is


Fig. 7.4 A digital-to-analog converter based on a resistive divider

Fig. 7.5 The impedance of a resistor string various with the position

the position of the nodes in a ladder with M = 2N resistors, the impedance on eachnode is:

Req(m) =

mM

Rtot × M−mM

Rtot

mM

Rtot +M−m

MRtot

=m(M−m)

M2 Rtot. (7.5)

Figure 7.5 shows the parabolic behavior of the effective impedance as a functionof the position, with a maximum in the middle. The time needed by the ladderimpedance to move charge will be position and signal-value dependent. High-frequency signals will show distortion.

The ladder impedance and its variation require buffering the output of the resistorstring. The remaining time constant of the resistor string and the capacitance at theinput of the buffer must be kept as low as possible to avoid the code-dependentdistortion.


7.2.2 Dynamic Behavior of the Resistor Ladder

The resistor string itself will show capacitive loading. This capacitive loading isdistributed over the ladder. Excitations by spurious voltages or charges will causea settling behavior. In order to facilitate an analysis, the resistor string is modeledas a continuous resistive strip, where the resistance and capacitance per unit lengthare defined by r in Ω/m and c in F/m. The voltage over this strip with length Lis described by the diffusion equation. This equation is also referred to as “heatequation”2 and describes in classical thermodynamic theory the evolution of thetemperature as a function of time and position:

∂ Temperature(x, t)∂ t

= D∂ 2Temperature(x, t)

∂x2 , (7.6)

where D is the thermal diffusion constant. This equation is used in the voltagedomain with the function v(x, t) describing the voltage in time and position overthe resistive structure:

rc∂v(x, t)

∂ t=

∂ 2v(x, t)∂x2 . (7.7)

With the boundary conditions at v(x,0) = vstart(x) and at v(0, t) = v(L, t) = 0, anexact solution can be obtained of the form

v(x, t) =∞

∑i=1

e−i2π2t/rcL2ai sin

(iπxL

). (7.8)

The solution is orthogonal for time and position, both are described by separatefunctions.

The start condition is brought into the equation by solving the equation for t = 0:

v(x,0) = vstart(x) =∞

∑i=1

ai sin

(iπxL

). (7.9)

The terms ai with the sin function are a Fourier description in a one-dimensionaldirection.

The initial condition that is defined by vstart(x) will exponentially decay. Thedecay behavior is dominated by the first term:

v(xm, t)≈ vstart(xm)e−π2t/rcL2(7.10)

with a time constant: τ = rcL2/π2.

2It is convenient to look in literature for solutions of the “heat equation” problem with your specificboundary conditions and rewrite them to voltage equations.


Fig. 7.6 In a ladder string with 256 resistors of 1.25 Ω and Ctap = 0.1 pF each, a current is injectedat the middle tap and switched off after 5 ns. The thin-line plots show the time behavior at variousnodes in the ladder. The bold line is the lumped RC approximation with τ = RtotCtot/8 = 80Ω×12.8pF

Looking at this problem from an engineering point of view, the starting obser-vation is that the largest errors due to the distributed delay line will occur in themiddle of the structure. From this point the resistive impedance towards the endsis Rtot/4 = rL/4. The capacitors at the intermediate nodes need to be charged. Thecapacitors close to the middle tap must be fully charged, and capacitors closer to theends will be charged proportional to their position. On average the total capacitanceis charged to half the value of the middle tap. That totals to a time constant onthe middle tap of: τ = RtotCtot/8 = rcL2/8, which is unequal to the solution of theheat equation, but close enough for a first order guess. Figure 7.6 compares theapproximation with the distributed line solution.

7.2.3 Practical Issues in Resistor Ladders

The actual design in the layout of a resistor ladder requires to consider variousaspects. The available resistive material must show low random variation, azero-voltage coefficient, and low parasitic capacitance. For high-speed conversion(>100 Ms/s) the time constant τ = RtotCtot must be low. As the total parasiticcapacitance is significant, extremely low values for the tap resistances are necessary.Realizing tap resistances in the order of magnitude of 1 Ω poses considerableproblems and requires sometimes to use special material layers on top of the chip.

In submicron CMOS processes a polysilicon layer has less parasitic capacitanceand a lower temperature coefficient; see Table 2.16. A diffused layer gives a better


Fig. 7.7 Due to the voltage difference over a diffused resistor, the depth of the active resistor isless at higher voltages. Placing the resistor in a well of opposite dope and biasing the well with thesame voltage difference avoids the voltage dependence

Fig. 7.8 On the left-hand side is a ladder built up with discrete resistors. On the right-hand side aladder structure is shown for high accuracy; see Sect. 11.3

matching performance; see Table 11.9. The voltage dependency of the diffusedresistor in Fig. 7.7 is canceled by placing the resistor in a well of opposite dopingand biasing this well with the same voltage difference.

Figure 7.8 shows two layout examples. The left-hand construction uses a fixedresistor lay-out connected by wiring. This is not an optimum construction. Thecurrent has to pass through contacts and contact areas show a lot of additionalvariation in resistance. On the right-hand side a construction is shown where thetap voltage connections do not carry current. Any variation in position, resistivity ofthe contact, etc. is not relevant. The current-supplying connections to the ladderare designed with sufficient contacts and are placed at some distance to reduce


Fig. 7.9 A cross-coupledladder structure

the material stress caused by the presence of aluminum wires; see also Fig. 11.20.Preferably a few dummy taps are inserted between the main connections and thefirst relevant taps.

This construction cancels a number of effects, such as contact hole resistance. Forlarge ladder structures also attention must be paid to gradients. Due to processingor heat sources the resistivity of the ladder material is not constant with distance.Gradients will create a non-linear voltage distribution over the ladder. If a ladderconsists of 2N resistors each nominally of value R with a gradient defined by adifference of ΔR between two adjacent resistors, then the ith resistor (i = 1, . . . ,2N)can be described as R(i) = R+(i−2N−1)ΔR. The current flowing through the ladderis constant, so the voltage on a node m = 0, . . . ,2N can be described by a resistorratio:

V (m) =

i=m∑

i=1R+(i− 2N−1)ΔR

i=2N

∑i=1

R+(i− 2N−1)ΔR

≈ m2−N(

1− 2N−1 ΔRR

)+m22−N−1 ΔR

R(7.11)

and V (0) = 0. This formula is of the form: y = x+ax2. Therefore the distortion andINL calculations of Sects. 2.1.3 and 5.4 apply.

Cross-coupling, as shown in Fig. 7.9, eliminates gradients. In this structure thesecond ladder is connected upside down to the first ladder. Only the two extremeconnections carry (large) currents. The currents in the intermediate connectionsare ideally zero, but will never be large. See Sects. 11.3 and 11.4 for some moretechnological background.


Fig. 7.10 A differentialladder structure and asign-and-magnitude topology

An alternative way to eliminate a first-order gradient is to use a differential signal.Figure 7.10 shows two examples: a ladder structure with full-differential decodingand a structure based on a sign-and-magnitude decoder.

Resistor ladders are crucial as building blocks in flash analog-to-digital convert-ers. When a resistor ladder converter is applied as an output device for driving anapplication, a careful design of the buffer is required; see Sect. 7.8.1. This topologyallows an excellent static performance at a limited power level. The speed is limitedby the performance of the buffer.

Example 7.1. Sixty-five current sources of 0.1 mA each are arranged in a lineand connected with their negative terminal to an aluminum return wire. This wireshows a 0.1 Ω impedance between two adjacent current sources. So the total lineimpedance is 6.4 Ω. Calculate the maximum voltage drop over this return line, if:

– The return line is connected to ground at one extreme– The return line is connected to ground at both extremes– The return line is connected to ground in the middle

Solution. This problem bears similarity to the calculation of the time constanton the distributed RC ladder. Starting at the open end of the return wire, it is clearthat the current source causes a voltage drop IR over the first segment of the returnwire. The voltage drop over the second segment is double, over the third segmenttriple, etc. The total voltage drop is therefore: (1+ 2+ 3+ · · ·+ n)IR. The sum ofthis series is found in Table 2.2: IRn(n+1)/2. With the data above the voltage dropat the open end is 20.8 mV.

If the open end is also grounded, the maximum voltage will appear in the middle.The middle current source contributes half to both sides, so the voltage drop is:32× 0.5IR+∑i=31

i=1 IR = 5.12 mV.One ground connection in the middle exactly splits the first problem in two, so

at both open ends, a voltage appears of ∑i=32i=1 IR = 5.28 mV.


Fig. 7.11 Currents can be split in binary-weighted portions (left). The constant impedance in eachbranch allows to reduce the branches of the structure

Example 7.2. Show that a perfect linear gradient in Fig. 7.10 is canceled by thedifferential readout of a single ladder.

Solution. If i = 0 . . .(2N −1) is the digital code, then a perfect ladder will producea voltage on every resistor node: Vi = VREF−+ iVLSB, where VLSB = 2−N(VREF+−VREF−). A linear gradient means that in the direction of increasing resistivity everynext LSB is slightly (ΔVLSB) larger. Now the voltage on every node is Vi =VREF−+i(VLSB + iΔVLSB)/S. The term between brackets must be scaled back with a factorS = (1+ 2NΔVLSB/VLSB) to fit to the reference voltages.

Now a differential output voltage can be formed by choosing the node voltageconnected to i and the complementary code 2N − i. This gives us a differential outputvoltage:

VOUT+−VOUT− = VREF−+ i(VLSB+ iΔVLSB)/S

−(VREF−+(2N − i)(VLSB+(2N − i)ΔVLSB)/S)

= (2iVLSB+ 2i2NΔVLSB − 2NVLSB − 22NΔVLSB)/S.

There are only linear signal components (proportional to i) left in the inputsignal. Note that the common mode signal VOUT+ +VOUT− contains the second-order distortion term. So the common mode rejection of the succeeding stages isimportant.

7.2.4 R-2R Ladders

Figure 7.11 shows on the left side a binary tree structure of resistors with value R.This tree is terminated with resistors values 2R. In every layer twice the number ofcurrents flow of half of the value of the layer above. Moreover from each nodelooking downwards the impedance equals R. This property allows to replace in


Fig. 7.12 R-2Rdigital-analog converter withdigital encoding

Fig. 7.11 (right-hand side) the branches by resistors R and thereby constructing theR−2R structure.3 Figure 7.12 shows a more abstract binary-coded digital-to-analogconverter based on the “R-2R” principle. Current entering the R-2R resistor circuitsplits at every node in two equal parts, because the impedance in both directionsequals 2R. The combination of branches therefore generates a power-of-two seriesof currents that can be combined via switches into an output current.

An analysis of the “R-2R” ladder in Fig. 7.12 is simple, provided the analysisstarts from the LSB side. The resistor network is terminated with a resistance 2R.This resistance is put in parallel to an equally sized value to generate the LSBcurrent. The combined value of the two resistors is R. If the resistor in series isadded, the total impedance of the section is back to the original 2R. This impedanceis connected in parallel with the 2R resistor for the LSB-1 and can again becombined to yield a R value.

A buffer is used to convert the current from the R − 2R ladder into a suitedoutput format. The bandwidth of the buffer is limiting the overall bandwidth ofthis converter. This technique allows to design digital-to-analog converters of areasonable quality (8 to 10 bits) at low power consumption and low area. Moreoverthe digital coding can be directly taken from a straight binary representation.

The main accuracy problem in a R-2R digital-to-analog converter is the inequal-ity in the splitting process. If the switch in the first vertical branch has a 1% largerresistance, the current will split in 0.495 and 0.505 portions, limiting the achievableresolution (for a DNL< 1) to 7 bit. The application is limited to low-resolution low-cost applications such as offset correction.

Example 7.3. In an R-2R ladder each resistor has an uncorrelated standard de-viation of 1% of its value. If a digital-to-analog converter is constructed withthese resistors, how many bits of resolution can be designed without running intomonotonicity problems?

3Explanation from Colin Lyden (ADI).


Fig. 7.13 Left: basic sectionof R-2R ladder, right: currentsplitting at the first node

Solution. Examine a basic section of the R-2R ladder in Fig. 7.13. With Eq. 2.20this yields for the variance of (Rb + Rc): σ2

b + σ2c . The equation for the parallel

resistors then yields

σ2tot =

(Rb +Rc

Ra +Rb +Rc

)4

σ2a +

(Ra

Ra +Rb +Rc

)4

(σ2b +σ2

c ).

An R-2R ladder is designed with Ra = 2R,Rb = Rc = R and Rtot = R, which reducesthe above equation to σ2

tot = (σ2a + σ2

b + σ2c )/16. The observation that replacing

Rc in the basic schematic by the same three-resistor scheme allows to expand thebasic schematic towards an R-2R ladder in an iterative way. Using 1+ r+ r2+ · · ·=1/(1− r), gives: σ2

tot = (σ2a + σ2

b )/15. With σa = 0.02R and σb = 0.01R, σtot =

0.01R/√

3.The influence of the additional sections on the splitting process of the first stage

is marginal due to the division by 16.This allows to reduce the current splitting problem to the current splitting in the

first stage, Fig. 7.13 (right) shows two equivalent input resistors, each nominal 2R.Resistor Rdown has a specified standard deviation of σRdown = 0.02R and Rright =

(Rb + Rtot) with σRright = R√

0.012 + 0.005772 = 0.0115R. Analyzing the currentsplitting of Itot = Iright + Idown:

σ2Iright−Idown

= σ2Iright

+σ2Idown

=

(dIright

dRright

)2

σ2Rright +

(dIdown

dRdown

)2

σ2Rdown

=

(d

dRright

(VREF

Rright

))2

σ2Rright

+

(d

dRdown

(VREF

Rdown

))2

σ2Rdown

=

(−VREF

R2right

)2

σ2Rright

+

(− VREF

R2down

)2

σ2Rdown

=Itot

4R

(σ2

Rright+σ2

Rdown

)=

Itot

4

√0.01152+ 0.022 = 0.0058Itot.

One σ equals 0.58% of the total current. Monotonicity means that the maximumerror in Iright − Idown is not exceeding an LSB: 2−N(Iright + Idown). For N = 6, anLSB equals 1.6%. So for a 6-bit R-2R DAC there is a 2.8σ probability or 0.5%chance that non-monotonicity will occur.

7.3 Digital-to-Analog Conversion in the Current Domain 281

7.3 Digital-to-Analog Conversion in the Current Domain

Figure 7.14 shows the block diagram of unary- and binary-coded digital-to-analogconverters in the current domain.

The buffer in Fig. 7.14 provides a low-impedance load for the current sources,avoiding modulation of the currents due to their finite output impedance. Majordisadvantage of this arrangement is the feedback stabilization of the opamp usedfor the buffer. If the buffer has to drive a load consisting of resistive and capacitiveelements, the unity gain of the buffer has to be designed at a frequency lower thanthe dominant pole of the output load in order to avoid output ringing. Consequentlythe overall bandwidth is degraded. When a choice for a buffered output is made, acapacitor array or resistor ladder solution is preferred.

7.3.1 Current Steering Digital-to-Analog Converter

The block diagram in Fig. 7.15 (upper) shows a digital-to-analog converter basedon current sources without a bandwidth-limiting buffer. The current sources aredirectly feeding the load impedance. The upper circuit shows a 3-bit unary arraysupplemented by a four-bit binary array. The currents sources are switched betweenthe output rail and the power supply. A current that is not contributing to the outputcurrent, cannot be switched off. This would inevitably lead to a discharge of theinversion layers in the (rather large) current source transistors and the parasiticcapacitors. Building up this charge after reconnection takes a lot of time and will

Fig. 7.14 Digital–analogconverter with currentsources: unary and binaryforms


Fig. 7.15 Upper: A unary array with current sources is complemented with a binary array. Lower:the binary array is replaced by a current divider

lead to linear and non-linear distortion therefore unused currents must be drained ina power rail. Consequently these converters always consume the maximum current.

The speed of this arrangement is only limited by the pole of the outputimpedance. This topology is suited for delivering a high-performance time-continuous signals into 50 to 75 Ω loads. This architecture is mostly called“current-steering digital-to-analog converter.”

These converters combine unary current sources for the MSB values, therebyensuring good DNL for the major transitions, with binary-coded current sources forthe lower bits. The total area is considerably smaller than for a completely unaryimplementation. A 10-bit converter can be built from 64 unary current sources and4 binary current sources requiring considerably less area than 1,024 sources in a fullunary implementation. The area reduction is of the order of 2Nbinary where Nbinary

represents the resolution of the binary section. The INL specification depends onthe matching and gradient of the unary current sources.

The choice between unary and binary block sizes depends on technologyand required DNL performance [135–137]. In resolution-limited converters theadvantage of using binary coding becomes marginal. If the accuracy of each currentsource is limited by random effects that are inversely related to the area (seeEq. 2.110) the total amount of gate area for a certain resolution for both architecturesis comparable. Secondary arguments such as wiring overhead will decide.

The design of the unary and binary currents sources requires some care. Theglobal variations in the currents as caused by process, voltage, and temperatureapply to all current sources and with careful design (see, e.g., Table 11.7) deviationscan be minimized. However, uncorrelated effects and gradients can cause errors at


Fig. 7.16 Ten-bit digital–analog converter: the 6 MSBs are implemented as 64 unary currentsources in a matrix configuration, while the four LSBs are designed in a binary series

all transitions, but are largest at the transitions between the maximum range of thebinary array and the step of the unary array.

A second implementation of a segmented unary-binary architecture is shown inFig. 7.15 (lower). In this circuit there is a third rail for the unary current sources.The required unary currents are switched to the output node as in the upper plot.The next current source is not connected to the power supply but feeds a binarydivider array. Although there are still DNL errors caused inside the binary divider,there is only a minor transition error at the transitions between the binary and unaryarrays. The disadvantage of this architecture is in the synchronization between theswitching of the binary and unary current sources causing timing-related errors athigh frequencies.

7.3.2 Matrix Decoding

A popular arrangement for the digital decoding of the input word into currentsource control signals is a column-row addressing scheme resembling a random-access memory, as indicated in Fig. 7.16. A straightforward selection, e.g., likesomeone reading this text, from left to right and top to bottom, will emphasizegradient effects. The current sources that form the unary part of the digital-to-analog converter are preferably selected in a way that cancels gradients [132, 138].These gradients can occur due to technological deviations such as doping or oxide


Fig. 7.17 Placement ofunary-weighted currentsources in a 64-element array.Similar colored squaresrepresent current sources thatform together one-bit level[138]

Fig. 7.18 Die photograph ofa 16-bit current-steeringdigital-to-analog converter in180-nm CMOS (courtesy: J.Briaire)

thickness variations, power supply drop due to voltage drop over current-carryinglines, clock timing gradients, and temperature gradients. In practical design thetechnological gradients are rather limited in magnitude. Especially the voltage, time[139], and temperature gradients can become rather severe.

Figure 7.17 shows a simple solution to the first-order gradient problem in anarray where the current sources are connected in a binary way: the common centroidtopology. Each group of current sources, forming the LSB up to the MSB, isarranged symmetrically around the center in both lateral dimensions. This willcancel any linear gradient.

More advanced schemes are known as Q2-walk schemes [140]. These schemesuse further subdivision of the current sources. Groups of sub-current sources arearranged to compensated for second-order components. Another approach is torandomize the current sources from one sample to the next [141]. Figure 7.18shows a die photograph of a current-steering digital-to-analog converter basedon current source sorting. An algorithm first measures the values of the currentsources and then arranges them in groups that optimize the overall performance.For example, the 2Nunary unary currents are selected by combining 2Nunary+1 current


Fig. 7.19 The basic digital-analog converter current cell and its small-signal equivalent circuit

sources in a way that one high-current source is matched by one low-currentsource. A considerable reduction of inequality can be achieved at the cost of somepreprocessing.

More points to consider with matrices of current sources are the following:

• The lines that are routed over the current source cells can interfere with these cellsdue to capacitive coupling, but also in a technological way. The metal coversthe current source transistors and affects the annealing of the underlying gatestructure causing mismatch (Sect. 11.3).

• The decoding network consumes power and increases cross talk.• Close to the final switches the selection signals must be retimed by the main clock

signal. Delays between the switching-on and off of various current sources createunequal

∫idt contributions to the output signal. Proper distribution of the clock

signal with equal traveling distances for each cell (10 μm wire causes 0.1 ps timedifference) is needed.

7.3.3 Current Cell

Figure 7.19 shows the basic current source schematic. The current source transistoris DC biased, and its size is chosen in a way to reduce mismatch effects and noisecontributions (e.g., long transistor length).

One of the main issues in this architecture is the modulation of the current sourcesby the output voltage. Depending on the effective internal impedance, this voltage


variation will result in a current modulation. When the digital signal or the fractionof current sources that is switched on, is 0 ≤ α ≤ 1, the ideal output voltage at asample moment becomes

VDD −Vdac = α2NILSBRload. (7.12)

with N as the resolution of the unary part of the digital-to-analog converter. A finiteoutput impedance of each active current source Zcur, as shown in the right-handside of Fig. 7.19, causes an additional current that is added to the digital-to-analogconverter’s output current. The total error current flowing into the finite outputimpedance is

Ierr = α2NVdac/Zcur. (7.13)

Both the fraction of active current sources α and the output voltage Vdac areproportional to the signal. This results in a second-order distortion term in thecurrent:

VDD −Vdac = Rload

(α2NILSB +

α2NVdac

Zcur

). (7.14)

Substitution of a full-swing output signal α = 0.5+ 0.5sin(ωt) results after somemanipulation in

HD2 =second-order component

first-order component=

2NRload

4Zcur. (7.15)

This signal ratio can be expressed in dBs via 2010log(HD2). The second-orderdistortion is directly related to the ratio of the output impedance of the currentsources to the load impedance.

A differential output scheme, where the complementary current also drives asimilar load, largely compensates this error.

Next to the resistive modulation Zcur also can contain capacitors, such as theparasitic capacitor on the drain of the current source transistor. The capacitivecurrent will increase with higher frequencies and so will the second-order distortion.This effect and the time deviations of the switching pulses are the root cause forperformance loss at higher signal frequencies.

If the switches are used in their conductive mode as cascode stages, the outputvoltage modulation has less effect. Also dedicated cascode stages can be used forthis purpose.

The switch transistors are optimized for fast switching and are controlled bydifferential pulses. Although the switches are in series with a current source, thevoltage drop over the switch can affect the performance, so their on-resistance ismade low. As all resistances of the current switches are in parallel, the value ofRswitch/2N must be very low compared to Rload.

Yet, the switches in current source digital-to-analog converters complicate thedesign. In contrast to the resistor ladder, where only one switch is active, in acurrent matrix a number of switches must be toggled if the signal changes from


Fig. 7.20 A current cell with quadruple switches keeps the number of transitions equal for everydata sequence [142]

one value to another value. Each switch (MOS or bipolar) needs some charge tocreate a conducting path. This charge is taken from the current source and thesignal during switching on, and is released into the output signal during switchingoff. If a current source digital-to-analog converter is used as an output device fordriving an application, this charge disturbance distorts the output signal and mustbe minimized. This disturbance is called a “glitch” and is harmful as this converteris used to produce a time-continuous output signal. The glitch produces a voltageexcursion over a certain time period. The associated area under the glitch is calledthe “glitch energy” and often expressed in picoseconds-Volt (psV). Careful designof the switches is necessary. The voltage swing on the switches must be kept at aminimum, and the clock edges must be strictly timed in order to limit the glitchenergy. Other methods try to keep the glitches constant for all codes. In Fig. 7.20 aswitching method is shown that will generate an equal number of transitions for anysequence of data bits [142] extended in [143].

Additional problems with the switches, clock, and signal lines are the timing-related errors.

• Clock jitter over the entire converter has a similar effect in the reconstruction ofthe signal as jitter in sampling. A signal frequency-dependent noise contributionwill appear in the output spectrum (compare Sect. 7.5).

• Wire length differences in clock lines (skew) or in current summing lines cancreate fixed timing errors (10 μm equals 0.1 ps). As these errors can be correlatedfor parts of the current sources, both a noise-like behavior as well as distortioncan result.

• Mismatch in transistor parameters can create random variation in switchingmoments; see Fig. 11.32.

Example 7.4. Show that a differential configuration of a current-steering digital-to-analog converter suppresses the second-order distortion.


Solution. If the constant VDD term in Eq. 7.14 is ignored, the signal terms can beevaluated as:

Vdac = −Rloadα2NILSB1

1− α2NRload

Zcur

≈−Rloadα2NILSB

(1+

α2NRload

Zcur

)

= C1α +C2α2, (7.16)

where the approximation 1/(1− a)≈ (1+ a) |a| � 1 is used. If the complemen-tary current (1−α)2NILSB is fed in a second resistor of value Rload the resultingvoltage Vdac,inv is easily found by replacing α in the equations by (1− α). Thedifferential voltage is then:

Vdac −Vdac,inv =C1α +C2α2 − (C1(1−α)+C2(1−α)2) = (C1 +C2)(2α − 1)(7.17)

which is linear with the signal term α .

7.3.4 Performance Limits

Current-steering converters without speed-limiting buffer reach high operatingfrequencies. The speed constraint at the output of these converters is limited by thetime constant of the output load, which also serves as a first alias filter. Next to thatthe speed of the digital processing and the timing inaccuracy limit the performance.The penalty for these advantages is power. For a single terminated 50 Ω cable, thisleads to 20 mA per converter. Next to that clock and decoding schemes require asignificant amount of power. Alternatively the drained current is used to implementa differential output that will cancel the second-order distortion component. Anadvantage of the constant current consumption is that the impact of power wiringimpedances and bond-wire inductance is less as there is no signal-dependent currentflowing through.

Figure 7.21 compares data from various publications [136, 139, 141, 144, 145]and data sheets on current-steering digital-to-analog converters in the time frame2000–2009. The plot suggests a first-order relation between the bandwidth and thelevel of spurious and harmonics. Another metric of comparison is a figure of meritsee Eq. 12.6.

Current-steering digital-to-analog converters are the industry’s primary choicefor output devices in demanding applications. Their dynamic performance isunmatched and the power penalty is accepted.

Example 7.5. A unary current matrix with 1,024 current sources produces amaximum current of 20 mA in a 50 Ω load. The current sources are built in 0.18 μmCMOS with an output impedance of 100 kΩ. A single-transistor cascode stage is


Fig. 7.21 Spurious-free dynamic range versus bandwidth for current-steering digital-to-analogconverters published from 2000 to 2009 (courtesy: J. Briaire)

used. What is the total output impedance of one current source if the gate cascadetransistor measures 1μm/0.18μm? What will be the distortion (THD) if a maximumamplitude sine wave is applied. What must be done to reduce the distortion to−60 dB?

If a parasitic capacitance of 100 fF is present parallel to each current source, whatwill be the frequency where the distortion is raised by 3 dB?

Solution. A minimum gate-length transistor has according to Table 2.21 a staticfeedback factor of λ = 0.05. So this cascode stage increases the output impedance ofthe current source to Zcur = r0(1+1/λ )= 100kΩ(1+20)= 2.1 MΩ; see Eq. 2.196.The dominant distortion component is the second-order term:

HD2 =2NRload

4Zcur= 6.1× 10−3

or 44.3 dB.In case of N = 10, Rload = 50Ω, and a desired −60 dB level of the second-

order distortion HD2, the effective impedance of a single current source must bebetter than 12.8 MΩ which can be achieved by choosing longer transistors or addinganother cascode stage.

If the distortion increases by 3 dB, the impedance |Zcur| must be 3 dB lower. AsZcur is formed by the resistive output impedance of the cascode stage and the loadingcapacitor of 100 fF, |Zcur| will drop 3 dB at the frequency where the capacitiveimpedance equals the resistive impedance: r0(1+ 1/λ ) = 1/(2π fC). This resultsin f3db = 0.76 MHz.


Fig. 7.22 A semi-digital filter and digital-analog converter [146]

7.3.5 Semi-digital Filter/Converters

After the conversion from the digital to the analog domain with a digital-to-analogconverter, the higher alias bands contain a lot of energy, despite some filtering bythe zero-order hold function. In many applications the high-frequency energy mustbe removed before the signal can be used.4 Su and Wooley [146] have proposed adigital-to-analog structure that converts the digital signal back into its analog formand at the same time filters the result. The digital signal is first converted in a high-frequency low-resolution data stream see Sects. 9.2 and 9.3. The semi-digital filterin Fig. 7.22 shifts the signal through a digital shift register where every output ofthe shift-register sections controls a weighted current source. The outputs of thesecurrent sources are summed.

The most simple implementation uses a one-bit digital signal that will switchon or off the weighted current sources. With the help of Sect. 3.2.1 the result iswritten as:

Iout(nTs) =k=K−1

∑k=0

akDin((n− k)Ts)ID. (7.18)

The coefficients are chosen using similar constraints as for a normal FIR filter. Thisstructure is very useful in the reconstruction of delta-modulated signals [147].

The advantage of this structure is the suppression of the alias components in thecurrent domain. Voltages will only appear after the current summation. So higher-order signal components can be effectively suppressed in the current domain and donot generate distortion when they appear as voltages over nonlinear components.

It is important to realize that errors in the coefficients in first order will affectthe filter characteristics and not the overall linearity. An error in the current sourcesthat implement a unary digital-to-analog converter will cause a linearity error atthat level with harmonic distortion. In a semi-digital converter this error modifies

4Think of all the energy your tweeter loudspeakers would have to consume.

7.4 Digital-to-Analog Conversion in the Charge Domain 291

the weighting coefficient by Δai and will result in an additional term of 1+Δaiz−i

which is a linear time-shifted signal contribution. The filtering will be less perfect,but no harmonic distortion will be generated.

7.4 Digital-to-Analog Conversion in the Charge Domain

Charge-domain converters differ from voltage-domain converters because thecharge is now the information-carrying quantity. Even in the presence of perfectlylinear capacitors, this distinction is still relevant, as, e.g., offset voltages can havedifferent effects in the charge or voltage domains.

In a first-order approach in a digital-to-analog converter the resistor circuitis replaced by switched capacitors [148]; see Fig. 7.23. Both unary and binaryconversions can be realized, depending on the choice of capacitor values. Anexample of a full-differential binary-weighted implementation is found in [149,Fig. 9]. A unary-decoding scheme with equal capacitors and switches is used toimplement the conversion.

The configuration in Fig. 7.23 does not suffer from parasitics that are attachedto the top plates of the capacitors as the virtual ground of the opamp stabilizes thisnode.

A stray-insensitive switching topology uses a standard switched-capacitor tech-nique to move charges. The parasitic capacitances connected to the switchedcapacitors in Fig. 7.24 are either charged from voltage sources or do not see anycharge change because they are connected to the (virtual) ground. In Fig. 7.24 theunit capacitors are grouped in a binary ascending scheme: 20C,21C,22C . . .2N−1C.Only one switch per group is necessary to implement a binary-coded converter. Thistopology principally suffers from the inequality of the capacitor banks at higherresolutions. However, with capacitors that can achieve matching performance thatallows 12–14-bit accuracy, the more practical limitation is in the exponential growthof the capacitor banks.

The span of capacitance values in digital-to-analog converters based on binarycapacitor arrays requires some trade-off. In some situations the choice for the unitcapacitor and the lowest capacitor value is determined by the kT/C noise. However,

Fig. 7.23 Digital-analogconverter based on unarycapacitors


Fig. 7.24 Binary-weighteddigital-to-analog converter ina stray-insensitive switchedcapacitor configuration

Fig. 7.25 Digital–analogconverter with bridgingcapacitor

also the technological realization of small capacitors can be an issue: it is difficult tofabricate accurately a 1 fF capacitor. In that case a bridging scheme can be usedsee Fig. 7.25. In this example the three MSB bits are formed in a conventionalbinary fashion. The three LSB bits use a bank with the same size capacitors butare coupled via a bridging capacitor Cbridge to the MSB side. The capacitance ofan LSB cell equals C, the LSB+1 cell equals 2C, and the largest cell uses 2k−1C.The total capacitance on the LSB side is (2k − 1)C If an amount of iC on the LSBside is switched from negative reference to positive reference while the remainingcapacitance (2k − 1 − i)C stays connected to the negative reference, the voltagechange on the left-hand side of Cbridge is

iC(Vref+−Vref−)C(2k − 1)+Cbridge

. (7.19)

This charge injection in the integration capacitor is compared to the desired chargeinjection in the summation node of the opamp:

Cbridge

Cbridge +(2k − 1)CiC(Vref+−Vref−) =

i2k

C(Vref+−Vref−). (7.20)

From this equation Cbridge =C is found.

7.4 Digital-to-Analog Conversion in the Charge Domain 293

Fig. 7.26 A charge redistribution converter [148]

Note that parasitic capacitances connected to the left side of the bridge capacitorwill affect the performance.

In first instance the capacitive schemes seem a one-to-one copy of the resistorschemes in Fig. 7.4. Yet there are some important differences. In the charge domainno constant current flow is required, except for the buffer. So a good power efficiencyis possible. A second difference is in the way jitter influences the output. If timeuncertainty occurs at the switching moments, the transfer of charge will be a bitearly or late however, the total magnitude of the packet remains intact. In a voltageor current-domain digital-to-analog converter, the overall packet consists of the timeperiod multiplied by the current or voltage amplitude. The jitter thereby changes thesignal, and jitter is directly translated into noise; see also Sect. 7.5 and Fig. 9.32.

Translation of current- and voltage-domain converters to the charge domain ispossible. The charm of the charge domain is, however, in the observation that storageis for free. A large number of interesting algorithms is possible. A basic chargeredistribution digital-to-analog converter is shown in Fig. 7.26. This converteroperates on a sequential binary principle: every bit is evaluated successively. Afterthe reset switch has discharged capacitor C2, the sequence can start. First the LSBvalue decides whether C1 is charged to the positive (via S11) or negative (via S10)reference. Then switch S2 connects the capacitors in parallel, redistributing thecharge from the reference over both capacitors, thereby halving the value. If thesecapacitors are equal, half of the charge is in either. Now the LSB+1 bit is used tocharge C1, thereby destroying the remaining charge. The sequence continues witha charge redistribution, where the new charge is added to the previous charge andhalved.

Vout(i) = biC1

C1 +C2Vref +

C2

C1 +C2Vout(i− 1), (7.21)

where bi ∈ {0,1}, with i = 0 . . .(N − 1). If both capacitors are equal, this principleis only limited by the accumulated kT/C noise and will result after N sequences inan output value of:


Fig. 7.27 An alternative implementation of an algorithmic digital-to-analog converter

Vout(N) =i=N−1

∑i=0

bi2i

2N Vref, (7.22)

where b0 is the LSB and bN−1 is the MSB. Using δ = (C2 −C1)/(C1 +C2) todescribe the error between both capacitors, an estimate of the overall error in Vout

can be made:

δVout(N) =i=N−1

∑i=0

bi2iδ N−1−i

2N Vref < δVref. (7.23)

Assuming that the error at the MSB transition must remain under the value of anLSB, sets a limit for the capacitor deviation:

δ =C2 −C1

C1 +C2< 2−N . (7.24)

An error of 0.1% in the capacitors limits the achievable resolution to N =−2 log(0.001)≈ 10 bits.

These switched-capacitor digital-to-analog converters are mostly applied inlarger system chips, where they perform low-power conversions.

Example 7.6. Figure 7.27 shows a variant on the design of Fig. 7.26. The incomingbits are added to the stored result which is then amplified by 2 and stored for the nextcycle in the capacitors. Now the operation starts with the MSB that is fed into thealgorithmic digital-to-analog converter, processed and multiplied by 2 and followedby the MSB-1. Discuss the merits of this modification.

Solution. The result of this operation bears great resemblance to Eq. 7.22:Vout(N) = ∑i=1

i=N bi−12iVref, where b0 is the LSB and bN−1 is the MSB. Thedenominator term 2N is missing. In order to keep the overall result of the additionwithin operation margins, Vref must now equal the small value of VLSB. Any erroron this quality (noise, etc.) will be amplified by the loop and result in poor signalperformance. In a preferred implementation the multiplication is with a factor 0.5

7.5 Digital-to-Analog Conversion in the Time Domain 295

and the sequence starts with the LSB. Due to the successive divisions, any error thatoccurred in the first cycles with respect to the large Vref is further reduced.

Example 7.7. Charge-domain digital-to-analog converters can suffer from capacitormismatch and from KT/C noise. At what signal level is the contribution of botheffects in terms of energy equal for a 1 pF capacitor?

Solution. A 1 pF capacitor will show a mismatch with respect to another capacitor.According to Eq. 2.91: σΔC/C = AC/

√C. With the value in Table 2.19 and C =

1,000 fF, the relative mismatch is found as: 1.6×10−4 or 0.16 fF. This same signal-to-spurious ratio can be expected for a processed signal Arms.

In Fig. 3.10 the kT/C noise equals 65 μVrms. Both contributions are equal if 1.6×10−4 ×Arms = 65× 10−6Vrms, or Arms = 0.4Vrms. This value corresponds to e.g., asine wave of 0.56 V amplitude or 1.12 Vpeak–peak. It is clear that both sources ofunwanted energy play a different role in a design. Note that, while kT/C noise actsas a noise floor from 0 to fs/2, the effects of capacitor mismatch can take manyforms: from spurious single-tone component to shaped noise after data-weightedaveraging.

7.5 Digital-to-Analog Conversion in the Time Domain

Besides subdivision in the voltage, current, or charge domain, digital-to-analogconversion can also be realized by means of time division. The signal informationis contained in the succession of switching moments; see Fig. 7.28. One of the firsttechniques to digitize information was based on the succession of pulses [105] andwas originally called pulse code modulation (PCM). This specific implementationis today referred to as pulse density modulation (PDM).

All time division schemes have in common that the output switches betweena few (two) levels of a physical medium (voltage or current). Any DC variationon these levels will manifest itself as a gain factor and will not affect the

Fig. 7.28 The low-frequency content of a pulse sequence contains the signal


Fig. 7.29 Several forms of time-domain digital-to-analog conversion

conversion quality. The linearity problems due to component inaccuracies arecircumvented. Pulse-width modulation (PWM) or PDM only uses two levels tocreate a fast-switching pulse sequence. The high and low time of the digital pulsetrain is ordered in such a way that the low-frequency component of the signal iscorrectly represented. In a simple form a pulse-width or pulse-density modulation(PWM and PDM) can be converted into the analog domain by filtering the pulses ina suitable low-pass filter.

Figure 7.29 shows four differently coded sequences. On the left side are thePWM formats. The amplitude of the signal is proportional to the width of thepulse. These pulses can be synchronized to the sample rate or free running. PWMsignals are not quantized in amplitude: the pulse width is proportional to the originalamplitude. On the right-hand side pulse-density-modulated signals are shown. InPDM the amplitude is quantized. Pulse density avoids issues with distortion due toasymmetries in falling and rising edges by using just one type of pulse. Sigma–deltamodulation and noise shaping are forms of PDM.

Whatever form of time-domain conversion is used, it is important to realize that alarge portion of the available energy in the time-domain representation is unwanted:

Energy in PWM signal ∝ (+/−A)2 = A2

Energy in maximum sine wave ∝∫(Asin(ωt))2dt = A2/2.

Even when the time-domain signal is representing a full-scale sine wave halfof its energy consists of spurious components and needs to be removed.5 Theseunwanted signal components are normally located at higher frequencies; however,if these frequency components are applied to nonlinear elements, down-mixing ofharmonics of the fundamental signal can occur.

5Compare this result to the power in the harmonics of a block wave in Eq. 2.6.

7.5 Digital-to-Analog Conversion in the Time Domain 297

Fig. 7.30 Comparison of jitter in normal sampling (dotted line) and in one-bit signals where amoderate oversampling ratio of 5 is used

The accuracy of generating time moments is limited as well. Jitter affects theactual position in time of the transitions. As jitter normally is a signal-independentprocess, the accuracy of the conversion improves at low-signal frequencies.

Any misplacement of a switching edge is directly multiplied with the maximumsignal swing. The effect of jitter on a pulse-density-coded signal is thereforeconsiderably larger than in the sampling of analog signals (compare Sect. 3.1.7).The maximum sinusoidal signal power that is contained by a pulse train switchingbetween +A and −A is the power of Asin(ωt). The time jitter is σjit which results in2Aασjit fs after multiplication with the amplitude and normalization with respect tothe sample rate.6 0 < α < 1 is an activity factor indicating the fraction of transitionscompared to the sample rate. This gives a signal-to-noise ratio of

SNR =

1Ta

∫ Tat=0(Asin(ωt))2dt

1Ta

∫ Tat=0(2Aσjitα fs)2dt

=1

8(α fsσjit)2 =

(1

4√

2OSRα fsigσjit

)2

(7.25)

with OSR= fs/2 fsig � 1 as the oversampling ratio. Comparison with the signal-to-noise ratio of sampled signals in Eq. 3.26

SNR =

(1

2π fsigσjit

)2

(7.26)

6Assuming only one edge is jittering.


Fig. 7.31 Class-D amplifierwith PWM

shows that the impact of jitter on PWM signals is related to the sample rate. There-fore jitter in time-domain digital-to-analog conversion is an order of magnitudehigher than in voltage- or current-domain converters; see Fig. 7.30.

7.5.1 Class-D Amplifiers

A well-known application of pulse-width modulation is in audio class-D amplifiersas shown in Fig. 7.31. The incoming analog signal is compared to a triangular signal(as can be generated from the integration of a block wave). At the crossings thePWM signal flips polarity. This PWM signal is used to drive the switches thatconnect to the positive and negative power. This power-PWM signal is low-passfiltered and applied to the loudspeaker. Potentially this method can result in 85%–90% efficient output stages. More advanced schemes are reported in, e.g., [150].

Example 7.8. What efficiency can be expected from a PWM class-D output stagefor 4 Ω load impedance with 0.2 Ω resistance per switch, 20 nF switch gatecapacitance, and 0.5 MHz clock frequency?

Solution. The major loss mechanisms in class-D are IR-drops, Ron of the switch,and switching losses of both switches: CV 2

DD f . For the total expected efficiency thismeans

η =Pload

Pload +Pres + 2Pcap=

I2Rload

I2Rload + I2Ron + 2CV 2DD f

substituting VDD = I(Rload +Ron) allows to eliminate the current, and an efficiencyof 88% is found.

7.6 Accuracy 299

7.6 Accuracy

7.6.1 Accuracy in Resistors Strings

The accuracy in which a quantity can be subdivided limits the obtainable perfor-mance of a digital-to-analog converter. In Fig. 7.32 a ladder of M = 256 equallydesigned resistors is connected between a reference voltage and ground. Ideally thevoltage at the mth position is:

V (m) =mM

Vref =mR

mR+(M−m)RVref =

R1

R1 +R2Vref. (7.27)

Although devices can be equally designed, some random variation is unavoidable. Ifall resistor values are subject to a mutually independent random process with normaldistributions with a mean value R and a variance σ2

R, the variance on the voltage atthe mth position can be calculated.

The resistance R1 is a string of m resistors and shows an expectation value andvariance:

E(R1(m)) = E(mR) = mE(R) = mR, σ2R1

= mσ2R. (7.28)

The other quantity involved R2(M −m) is the string of (M −m) resistors which isindependent of the complementary string R1. For the string R2 the mean and the

Fig. 7.32 A resistor string is connected between a reference voltage and ground. The simulationshows 10 instances of the effect of σR/R = 1% mismatch. In this 256-device ladder the maximumdeviation is ±0.2R


variance are found in a similar way.7 The variance of the voltage V (m) is now foundby applying the statistics formula for multiple stochastic variables (Eq. 2.18):

σ2V (m) =

(∂V (m)

∂R1

)2

σ2R1+

(∂V (m)

∂R2

)2

σ2R2

=

(R2

(R1 +R2)2

)2

σ2R1

V 2ref +

( −R1

(R1 +R2)2

)2

σ2R2

V 2ref

=m(M−m)

M3

σ2R

R2 V 2ref.

Compare to Eq. 7.5. The maximum value of the variance occurs at m = M/2 forwhich the variance is found as

σ2V (m = M/2) =

14M

σ2R

R2 V 2ref =

M4

σ2R

R2 V 2LSB, (7.29)

where Vref = M×VLSB.The position of the maximum value of the variance is not equivalent to the

position of the maximum voltage deviation of one particular string. NeverthelessEq. 7.29 can serve to estimate the INL. With the help of Table 2.11 the sigma margincan be chosen.

In the example of Fig. 7.32 the ladder contains 256 resistors with a relativeresistor mismatch of 1%. The relative sigma value in the middle of this ladder istherefore 8% and in the 10 random simulations excursions up to 20% of an LSB areseen. These values directly impact the integral linearity.

The differential linearity is given by the variation in the step size itself and equalto the expected maximum deviation of one resistor. The DNL of a resistor string isdetermined by the single resistor variance and the number of resistors. The DNL isdetermined by the largest deviating resistors amongst M random-varying resistorswith each a relative spread of σR/R. In order to guarantee the DNL for a productionlot the estimation will have to be extended to P converters times M resistors perconverter.

Example 7.9. If the resistors in a string show a relative spread of 1%, what is theprobability that one resistor in a string of 256 exceeds a deviation of 4%?

Solution. The probability p that one resistor with value Ra and σR/R= 1% deviatesmore than 4% from the average value R is:

p = P

(∣∣∣∣Ra −RR

∣∣∣∣> 4σR

R

)= P(|x|> 4σ) (7.30)

7It seems that a shortcut is possible by using the string of M resistors; however, this string shares mresistors with R1 and the covariance has to be included, which is a possible route, but not pleasant.

7.6 Accuracy 301

with Table 2.11 p = 6.3× 10−5. The yield per resistor is (1− p). The yield for aresistor string with M = 256 resistors is (1− p)M = 98.4% .

7.6.2 Accuracy in Current Source Arrays

In a similar manner the effects of random variation in a unary current source arrayor a capacitor array can be calculated. The variance in currents formed by the sumof m independent sources is σ2

mI = mσ2I . The maximum error occurs if all M current

sources are used. This scenario implies the strict definition of linearity. If the “best-fitting” straight line algorithm is used, the overall variation is better referred to thetotal current. If the current of m sources is evaluated relative to the total current:

I(m) =mI

mI +(M−m)IItot (7.31)

the mathematical description is identical to the resistor string problem and yields:

σ2MI/2 =

14M

σ2I

I2 I2tot. (7.32)

This equation allows to estimate the INL while the DNL is directly coupled tothe variance of the individual current sources. The DNL is therefore small, whichemphasizes the architectural advantage of the unary architecture.

Figure 7.33 shows the simulation of a unary array of 256 current sources witha relative current mismatch of 1%. The coding of the current sources is in athermometer manner: each sample is built up starting with source number 1 untilthe number of sources corresponding to the digital code is active. If the randomprocess creates an error in a current source then this will result in an error at a fixedvalue of the signal. This form of coding transforms random errors in the currentsources partially into distortion products of the signal and partially in a fixed-patternnoise. Data-weighted averaging techniques circumvent the occurrence of harmonicdistortion due to random errors; see Sect. 7.7.3.

Digital-to-analog converters based on a binary architecture are analyzed aftersome modifications of the above scheme. The random variation will affect thetransition between the exponentially weighted portions of the unit. In an N-bitcurrent source configuration the currents are ordered along powers of 2:

IN−1 = 2N−1ILSB, IN−2 = 2N−2ILSB, . . . , I1 = 21ILSB, I0 = ILSB. (7.33)

The major transition is at the code 011 . . .11 and 100 . . .00 where in absence ofrandom variation, the expected change in current is equal to one ILSB:


Fig. 7.33 Spectrum of a digital-to-analog converter with random mismatch. An array of 256current sources is simulated with a normally distributed mismatch of σI/I = 1%. The sig-nal frequency is 3.97 MHz at 100 Ms/s sample rate; the quantization error is removed. Thesecond-, third-, and fourth- order distortion components are labeled

ΔI = IN−1− IN−2−·· ·− I1− I0 = 2N−1ILSB−2N−2ILSB · · ·−21ILSB−20ILSB = ILSB.(7.34)

If the currents are subject to random variation, the value of ΔI will show significantvariations. These variations result in a (potentially) large DNL, the architecturalweak point of the binary coding. Depending on the implementation of the architec-ture several situations are possible:

• Every current branch is composed of a parallel connection of 2k basic currentsources as in Fig. 7.14 (lower). The current branch of weight k in the arrayis described by Ik = 2kILSB. Let each basic current source ILSB suffer from avariation mechanism characterized by a normal distribution with mean valueILSBm and a variance σ2

I . Then each branch will be characterized by a mean2kILSBm and a variance σ2

Ik= 2kσ2

I see Eq. 2.19. With the same equation thevariance for the current step on the MSB transition is:

σ2ΔI = (2N−1)σ2

I +(2N−2 + . . .+ 21 + 20)σ2I = (2N − 1)σ2

I . (7.35)

Monotonicity requires that the value of ΔI remains positive. If a 3σ probability(99.7%) is considered an acceptable yield loss, then 3×√

(2N − 1)σI < ILSB. Foran 8-bit converter this requirement results in σI < 0.02ILSB.

• In an R-2R ladder as in Fig. 7.12, the current splits at the first node in an MSBcurrent IMSB and a similar current for the remaining network. The impedances R1

and R2 are nominally equal to 2R, but the individual resistors suffer from random

7.6 Accuracy 303

variation characterized by a normal distribution with a variance σ2R1,2

. With thehelp of Eq. 2.18

IMSB =R2

R1 +R22NILSB

σ2IMSB

(2NILSB)2 =

(∂ IMSB

∂R1

)2

σ2R1+

(∂ IMSB

∂R2

)2

σ2R2

=R2

1σ2R2+R2

2σ2R1

(R1 +R2)4

≈ 2σ2R1

4(R1)2 . (7.36)

Requiring for monotonicity that 3×σIMSB < ILSB, results for 8-bit resolution inσR1/R1 = 0.002. The ten times higher precision that is needed for the resistorsplit, is due to the fact that the error is determined by the combination of justtwo resistors, whereas the MSB in the current architecture was built from 2N−1

current sources.

Digital-to-analog converter designs can be optimized based on the above analy-sis [137].

Example 7.10. Groups of 1, 2, 4, . . . unit current sources are combined to form abinary architecture digital-to-analog converter. Each unit current source shows arandom mismatch of 1σ = 1% of the LSB current. How many bits can be designedwhen a DNL of 0.5 LSB must be reached for 99.7% (or −3 to +3σ ) of the produceddevices.

Solution. The absolute mismatch of a single LSB current source is σI = 0.01ILSB.Putting n current sources parallel increases the average current to nILSB and themismatch to σnI =

√nσI =

√n0.01ILSB. The worst-case transition in an N-bit

binary digital-to-analog converter is at the switching point between the MSB current2N−1ILSB with σIMSB =

√2N−1σI and the LSB to MSB-1 currents: (2N−1 − 1)ILSB

with σIlower–bits =√

2N−1 − 1σI . The nominal difference between the groups ofcurrent sources is exactly 1ILSB. The variance of the difference between thesegroups is

σ2diff = (2N−1)σ2

I +(2N−1 − 1)σ2I = (2N − 1)σ2

I

When 3σdiff < 0.5ILSB the result is N = 8.

Example 7.11. A binary current digital-to-analog converter is build with weightedcurrent sources, each with a random mismatch of 1% of the current, independent ofthe current value. How many bits can be designed as a binary section when a DNLof 0.5 LSB must be reached for 99.7% (or −3 to +3σ ) of the produced devices?

Solution. The absolute mismatch of the ith current source (i = 0, . . . ,N − 1)is now 0.01ILSB × 2i. The worst-case transition in an N-bit binary digital-to-analog converter is at the switching point between the MSB current 2N−1ILSB

with σIMSB = 0.012N−1ILSB and the LSB to MSB-1 currents: σIlower–bits =


0.01ILSB

√22(N−2) + · · ·+ 28 + 24 + 22 + 20. The nominal difference between the

groups of current sources is 1ILSB. The variance of the difference between thesegroups is

σ2diff = 22(N−1)(0.01ILSB)

2 +(22(N−2) + · · ·+ 28 + 24 + 22 + 20)(0.01ILSB)2

When 3σdiff < 0.5ILSB the result is N = 3. The 1% relative spread in the MSBcurrent clearly dominates. If a process shows large sensitivity to relative spreads(e.g., random mask variations in the gate length) it is better to design the converterwith small current sources.

7.7 Methods to Improve Accuracy

Small variations in parameters as discussed in the previous section lead to additiveand multiplicative errors in analog circuits. In an amplifier additive errors can beregarded as a DC offset, while multiplicative errors affect the overall gain. Thedigital-to-analog converters from the previous paragraphs consist of a divisionmechanism based on multiple copies of components (e.g., a resistor string or aset of current sources) and a switching mechanism that chooses the appropriatesettings. Additive and multiplicative errors in analog-to-digital and digital-to-analogconverters where signals use different paths in the circuit, affect only a certain rangeof the signal see Fig. 7.34. These errors will generate complex and signal-dependentpatterns that result in distortions, spurious tones, or noise-like behavior. With thedesign guidelines of Table 11.7 the systematic errors in components can largely beeliminated. And large devices reduce the random error to a level that allows a 10-to 12-bit accuracy. If more accuracy is needed additional circuitry is required in thedesign.

In Fig. 7.35 the errors ε1,2,3,i affect the different paths through the analog-to-digital or digital-to-analog converter. Three classes of mitigation of additive errors

Fig. 7.34 Additive and multiplicative errors in conversion

7.7 Methods to Improve Accuracy 305

Fig. 7.35 Three methods to mitigate additive errors. Top: calibration, middle: chopping, bottom:dynamic element matching

are shown. On top is the calibration principle. This principle assumes that theadditive errors are localized and that a feedback path is available to compensatethese errors at the node or close to the node where they originate. The feedbackis generated by means of a form of measurement of the errors. The feedback loopcan take many forms. For example, a single measurement can be done during theproduction test and the feedback consists of a laser trimming some resistor value. Asecond option is a form of on-chip measurement, which runs continuously duringthe life time of the device. The advantage of calibration is that once in place theremaining circuit acts as an error-free circuit. The error is removed, not only moved.The electronic feedback path in such a system is continuously present and mayintroduce noise into the signal path. An example of the calibration of a matrix ofcurrent sources is given in Sect. 7.7.1.

The second method to mitigate additive errors was 50 years ago already in use forprecision instrumentation. The chopping technique [151], Fig. 7.35 (middle), firstmodulates the input signal to a higher-frequency band which is processed by theconverter. The error is located at DC or a low-frequency band and will not interferewith the signal. Now the processed and composite signal is modulated back withthe same frequency as used at the input. The signal is restored to its frequency rangeand the additive error is modulated to the chopping frequency. This technique relieson good quality mixers/modulators and of course requires the conversion functionto process the signal at that frequency. Although this technique is rarely used in aconverter [152], it is often implicitly present in digital radio systems. In contrast tocalibration the error is still present and its energy may come back into the signalpath after, e.g., distortion; see also Sect. 3.1.3.


Fig. 7.36 An example of a digital-to-analog converter applying current calibration [133]

The last principle addresses the error at its source, just as in calibration. Theerror is not removed but moved to a less critical frequency range. Examples of thistechnique are dynamic element matching and data-weighted averaging, Sects. 7.7.2and 7.7.3.

The discussion in this section is limited to mitigation of additive errors. Theimpact and avoidance of multiplicative and timing errors are discussed in Sect. 8.8.

7.7.1 Current Calibration

With the change from bipolar devices to CMOS techniques new forms of calibrationbecame possible. Figure 7.36 shows a unary current array with one spare currentsource. The unary row of current sources is extended by one, from 64 to 65. Thisallows to calibrate every clock cycle one of the current sources of the unary array.In Fig. 7.37 two NMOS transistor form the calibrated current source: M1 suppliesthe majority of current as a traditional current source. M1a is used to calibrate andto mitigate the inherent mismatch in these sources. During the calibration the sparecurrent source is connected as a sort of track-and-hold circuit by closing the switchbetween gate and drain. Feeding this arrangement with a reference current willforce the gate voltage of M1a to settle at the level needed to balance this current.After opening the switches the gate capacitor will hold a voltage that makes thatthe total current from M1 and M1a is a copy of the reference current. This currentsource is ready for use. Another current source is taken out of the array and will becalibrated. In this way the calibration mechanism rotates through the array tuningevery 65 cycles all current sources. The unary array of calibrated current sources


Fig. 7.37 The current calibration technique [133]

Fig. 7.38 Dynamic element matching [129]

in the digital-to-analog converter of Fig. 7.36 is completed by a 10-bit passivecurrent divider to yield a 16-bit digital-to-analog converter. The main problemin this arrangement is the sampling of noise in the calibration cycle. Unwantedlow-frequency noise as 1/ f noise is suppressed up to half of the calibrationfrequency, but the remaining contributions influence the current considerably. Thisis mainly due to the relatively low calibration frequency which is experienced bythe individual current sources. For that reason most of the current is generated bythe standard current source M1 and only a few percent is calibrated via M1a.

7.7.2 Dynamic Element Matching

An often used technique is swapping components, currents, or voltages. In Fig. 7.38the two currents I1 and I2 have been created by dividing a main current; however,


Fig. 7.39 An example of a digital-to-analog converters applying dynamic element matching [132]

these currents show a small offset with respect to each other. A switching boxalternates the connection to the outputs. The resulting currents I3 and I4 arecomposed of both I1 and I2 and average out the difference over time. The resultingerror in I3 and I4 is the product of the original inequality times the duty cycle of theswitching pulse.

I3 − I4

I3 + I4=

I1 − I2

I1 + I2× t1 − t2

t1 + t2. (7.37)

This technique is known as “dynamic element matching” [129] and is applied inmany types of converters. Figure 7.39 shows an extension of the technique togenerate three currents in the ratio 1 : 1 : 2. Cascoding a number of these stages leadsto a 16-bit current digital-to-analog converter. Unfortunately the cascoding costsvoltage head room, therefore the dynamic element technique is today more usedin order to tune a small set of devices. Note that the switching frequency will notinterfere with signal path, the signal switching can be performed after the D.E.M.procedure, and spurious frequency components can be filtered out before the signalswitching takes place.

Example 7.12. What happens to an external input signal near to the choppingfrequency? And what happens to an input signal close to the DEM frequency?

Solution. Figure 7.40 shows the chopping mechanism in comparison to thedynamic element matching. Chopping moves the signal frequency to a higherfrequency before the error is introduced. After that the error and the up-modulatedsignal frequency are modulated again, causing the signal frequency to appear at itsoriginal position and the error at the chopping frequency.

The dynamic element mechanism directly up-modulates the error, before it isadded into the signal chain.


Fig. 7.40 Comparison of chopping (above) and dynamic element matching (below)

Fig. 7.41 Data weighted averaging [154, 155]

7.7.3 Data-Weighted Averaging

The elements in the current source array in Fig. 7.14 or the resistor string are alwaysused in the same order as depicted in Fig. 7.41 (left). The signal in this digital-to-analog converter is being built up starting with the leftmost element and thesomewhat larger third element will show up at a fixed position in the signal. Thiswill result in harmonic distortion, as is shown in Fig. 7.33.

The dynamic element matching technique rotates the various components in apre-determined order and under control of an independent frequency. The idea is totransform a fixed DC error into a modulated component at a high frequency that iseither filtered out or moved to a frequency band where it causes no problem.

A different solution to the problem is to change the starting point for buildingup the signal in the array. For example, the next sample starts at an offset of oneposition. This offset is increased for every next sample. The offset can even bechosen randomly [153]. These techniques transform the error at the third position


in this example into a sort of noise as the correlation with a fixed position in thesignal amplitude is avoided. Mathematically this principle can be understood byassuming that the elements xi, i = 0, . . . ,∞ form an infinitely long line of elements.A signal sample formed with p of these elements is disturbed with an error σx

√p.

If the average value of p is around mid range E(p) = 2N/2, the long-term averagenoise per sample is σx

√2N−1. In the frequency domain this results in a white-noise

spectrum.This idea is taken one step further in the data-weighted average principle [154–

157].8 The elements are now functionally arranged in a circle; see Fig. 7.41 (right).Every next sample starts after the last element of the previous sample. If an array iscomposed of 2N elements with random-varying values xi, i= 0, . . . ,2N−1, the cyclicoperation causes that every element is used an equal amount of times in the longterm. Therefore it is useful to specify the average or mean value of every elementby means of the expected value:

mx = E(xi) =1

2N

i=2N−1

∑i=0

xi. (7.38)

A sample at time t = nT contains k elements and its output value will be:

y(nT ) =i=k−1

∑i=0

xi =i=k−1

∑i=0

mx +i=k−1

∑i=0

(xi −mx). (7.39)

The first term is the desired signal value of the digital-to-analog conversion and thelast term in the summation represents the unwanted or noisy part of the array ofelements. This formulation modifies the ideal amplitude of the actual element xi

into its mean value mx. This may (slightly) change the amplitude of the signal if therandom component has a nonzero mean value; however, in practice, the result willbe a minor change in gain.

The error signal contains spectral components. If there would be only onedeviating element xp with an error εp, Fig. 7.42, the error signal due to εp will appearin the output depending on the number of times the element xp is requested. Thisresults in an unwanted spurious contribution fp where the frequency depends on thelevel of the output signal. For example, if the average signal level is a one-quarter ofthe full scale, the error element will appear one on every four sample pulses, so theerror component will appear around fs/4. With an average signal around midrangethe error will produce tones around fs/2 and generate maximum error power. Theerror frequency and the error power associated to it are proportional:

Pp ∝ fpε2p. (7.40)

8Two sources are available as the originator of DWA: Michael Story [156] and Maloberti [157].


Fig. 7.42 A single mismatching current source will appear at a low frequency if the average signalvalue is close to the extremes of the range

Fig. 7.43 Spectrum of a data-weighted averaging digital-to-analog converter. 256 current sourcesare simulated with a normally distributed mismatch of σI/I = 1% (no quantization error). Thesignal frequency is 3.97 MHz at 100 Ms/s. In the inset a small fraction of the range is visible. Thespectrum contains a lot of tones

For a single error the energy of spurious component is proportional to the frequency.In a spectrum this leads to a first-order behavior of the error tones versus frequency.For a full error pattern the same conclusion holds [154].

If there is no dominant error source, the spectrum of the random components willshow a first-order frequency shaping, as is seen in Fig. 7.43.

A formal proof requires the introduction of some stochastic mathematics [154].The following reasoning summarizes the line of thought without pretending to be asolid mathematical proof. The second term of Eq. 7.39 defines the error for a sample


at time t = nT . As the total number of sources is bounded to 2N −1, the error of theremaining sources is given by

i=2N−1

∑i=k

(xi −mx) =i=2N−1

∑i=0

(xi −mx)−i=k−1

∑i=0

(xi −mx) =−i=k−1

∑i=0

(xi −mx). (7.41)

The remaining error has the magnitude of the error at time t = nT with an oppositesign. The DWA algorithm by its definition uses for the next samples the remainingsources. So the remaining error will show up at the next sample or at the next fewsamples, depending on the values of the succeeding signal samples. If the delay ofthe remaining error term with respect to the originating error term is estimated atαTs, with α ≥ 1, the transfer function of the error becomes

E(z) =i=2N−1

∑i=k

(xi −mx)(1− z−α). (7.42)

With a crude approximation the frequency behavior of the error is:

E(ω) ∝i=2N−1

∑i=k

(xi −mx)(2sin(ωTs/2)). (7.43)

This result for a single error can be extended to all errors that will occur duringthe conversion of a complex signal resulting in a first-order shaping of the randomerrors. Figure 7.43 shows the result of the data-weighted averaging operation.Firstly the harmonic distortion products have been considerably reduced due to therandomizing effect of the selection. Secondly the DWA algorithm has cleaned thespectrum around DC; see inset. The noise level at higher frequencies has increasedas is inevitable in “noise shaping.” The consequence is that DWA must be applied inoversampling applications: the sample rate must largely exceed the signal bandwidthin order to allow some frequency band for the excess noise. Other switchingsequences of the DWA algorithm allow to choose the frequency of maximumsuppression at arbitrary points in the spectrum [147]. Miller and Petrie [158] showsa high-speed implementation of the digital decoding.

Unfortunately the error pattern will not completely randomize the error signal.The possibility that a fair number of samples of a DWA digital-to-analog converterproduces tones is likely.9 As a result often the DWA algorithm is extended withadditional randomizing algorithms like the addition of dither; see Sect. 5.3.3 and[159].

9In Chap. 9 “idle patterns” are discussed. The patterns in data-weighted averaging bear a lot ofresemblance but come from a completely different origin.

7.8 Implementation Examples 313

7.8 Implementation Examples

7.8.1 Resistor-Ladder Digital-to-Analog Converter

In a system chip with analog-to-digital and digital-to-analog converters, it isadvantageous to have similar references for the analog-to-digital and digital-to-analog converters. The tracking of input and output ranges for processing variations,temperature, etc. is then guaranteed and the overall gain of analog-to-digital anddigital-to-analog converters is better controlled. The voltage dependence and themutual matching of large-area polysilicon resistors10 allow the design of a converterwith high integral and differential linearity. Basically, the variation in the polysiliconresistance value is determined by its geometry variations: the variations in lengthand width result in local mismatches and the variation in thickness results ingradients.

The design of a digital-to-analog converter with a single 1024-tap resistor ladderand sufficiently fast output settling requires tap resistors in the order of 6–10 Ω. Thesize of such resistors in conventional polysilicon technology is such that accurateresistor matching, and hence linearity, becomes a problem. The solution to thisproblem is to use a dual ladder [160] with a matrix organization [161].

Figure 7.44 shows the ladder structure: the coarse ladder consists of twoladders, each with 16 large-area resistors of 250 Ω which are connected antiparallelto eliminate the first-order resistivity gradient. The coarse ladder determines 16accurate tap voltages and is responsible for the integral linearity. A 1024-resistorfine ladder is arranged in a 32-by-32 matrix, in which every 64th tap is connectedto the coarse ladder taps. This arrangement makes it possible to avoid the needfor small tap resistors (see Fig. 7.6). The fine ladder tap resistance is chosen at75 Ω without loss of speed. The wiring resistances can be neglected comparedto the 75 Ω tap resistors. There are only currents in the connections between theladders in the case of ladder inequalities; this reduces the effect of contact resistancevariance. The current density in the polysilicon is kept constant to avoid field-dependent non-linearities. The coarse ladder is designed with polysilicon resistors inorder to avoid voltage dependence of diffused resistors. The fine ladder is designedin either polysilicon or diffusion, depending on secondary effects in the processimplementation. The double ladder structure is also used in all of the three A/Dconverters discussed in Sect. 8.9.

In a basic ladder design consisting of one string of 1,024 resistors, the outputimpedance of the structure varies with the selected position on the ladder andtherefore with the applied code. The varying output impedance in combination withthe load capacitance results in unequal output charging time and consequently signal

10Diffused resistors are a preferred alternative in more advanced processes.


Fig. 7.44 Resistor network for a video digital-to-analog converter [162]

distortion of high-frequency output signals. This source of varying impedance hasbeen eliminated by means of a resistive output rail. The inset in Fig. 7.45 shows partof two rows of the matrix.

The second source of the varying output impedance is the switch transistor;usually its gate voltage equals the positive power supply, but the voltage on itssource terminal is position dependent. The turn-on voltage doubles from one endof the ladder to the other. In this design an additional supply ladder is placed on topof the signal ladders to keep the turn-on voltage of the switches more constant. Theturn-on voltage of each switch transistor is effectively made to correspond to thelowest turn-on voltage of the ladder digital-to-analog structure.

The total ladder configuration can still be fed from the 3.3 V analog powersupply; the signal ladders are in the range between ground level and 40% of thepower supply; the supply ladder goes from 60% to VDD.

The core of the digital-to-analog converter is formed by the 32-by-32 fine-resistormatrix. The two decoders are placed on two sides of the matrix. The two sets of


Fig. 7.45 Block diagram of the digital-to-analog converter [162]

32 decoded lines are latched by the main clock before running horizontally andvertically over the matrix. In the matrix, the 1024 AND gates perform the finaldecoding from the 32 horizontal MSB lines and the 32 vertical LSB lines.

A voltage-domain digital-to-analog converter generates only the necessary mo-mentary current and is hence more efficient in power consumption. However,a voltage-domain digital-to-analog converter requires an on-chip buffer, whichintroduces two drawbacks: the output always needs some offset from the powersupply rail, and the opamp is inherently slower. The output buffer is a folded-cascode opamp with Miller compensation. The Miller feedback current flows viathe source of the cascode transistor to the high-ohmic node [68]. This approachavoids a stop resistor in series with the Miller capacitor. The stop resistor is notdesired because the transconductance of PMOS driver is not very constant.

The p-channel input stage operates on input voltages ranging from 0 to 2.2 V;see Fig. 7.46. The main current path through the output stage goes from the PMOSdriver (W/L = 1400) down into the output load. A resistive load is consequentlyneeded for optimum performance.

The on-chip stop resistor Rseries is on the order of 25–75 Ω; it keeps up afeedback path even at frequencies at which the bondpad capacitance shorts thecircuit output. It also serves as a line termination. The swing of the output loadresistor is consequently half of the buffer input voltage. The actual value of thestop resistor can be controlled to within 10%; the resulting gain error is no seriousdrawback in video equipment, as there is always a total gain adjustment.

The power distribution over the 10-bit digital-to-analog converter is dominatedby the output stage: with a full-swing sine wave (0.1–1.1 V on 75 Ω), the average


Fig. 7.46 Folded-cascode opamp circuit with Miller compensation used for the buffer

current through the driver transistor is 7.3 mA. The remaining part of the driverrequires 1 mA. The ladder current is 1 mA while the digital part running at 50 MHzis limited to 0.7 mA, resulting in a total power supply current of 10 mA.

Table 7.3 in Sect. 7.8.3 summarizes the performance that is more extensivelyreported for a 1 μm technology in [162]. Figure 7.47 shows a photograph of a triple10-bit converter.

7.8.2 Current-Domain Digital-to-Analog Conversion

High-speed CMOS digital-to-analog converters designed with a current cell matrixallow fast and accurate settling [130, 163].

A 100 Ms/s 10-bit digital-to-analog converter was designed with an array of 64current sources for the 6 MSBs. This structure was completed with a 4-bit binary-coded LSB section. Figure 7.16 shows the block diagram of a 10-bit design. Themajor design issue in this circuit is the switching of the 64 current sources. Decodingdelays in the 64 current sources are reduced by an additional latching stage justbefore the current switch. The current switch itself is designed with a low-swing(1 V) differential pair. This measure results in a low clock feed-through on theoutput line, while in this case the switch transistors also act as a cascode stage, thusreducing the modulation of the output current by the output voltage. Figure 7.48shows the chip photograph of this design.


Fig. 7.47 This 10-bit triple digital-analog converter based on voltage dividers is used forapplications in the video domain for the basic video colors: red, green, and blue

Fig. 7.48 Chip photograph of a 10-bit current digital-to-analog converter


Table 7.3 Comparison of measured specifications of a ladder and a currentdigital-to-analog converter, both loaded with 75 Ω and 25 pF

Digital-to-analog converter type Ladder Current

Process 1.0 μm CMOS 1.0 μm CMOSDC resolution 10 bit 10 bitSample frequency >100 MHz >100 MHzArea 1 μm CMOS 1.05 mm2 0.7 mm2

Differential linearity error < 0.1 LSB < 0.6 LSBIntegral linearity error < 0.35 LSB < 1 LSBGlitch energy 100 psV 100 psVRise/fall time (10%–90%) 4 ns 1 nsSettling time (1 LSB) 20 ns 5 nsSignal bandwidth (−1 dB) 20 MHz >20 MHzMinimum power supply (THD<−40 dB) 3 V 3 VOutput in 75 Ω 1 V 1 VOutput at minimum code 100 mV <1 mVAverage current (50 MHz, 75 Ω) 10 mA 15 mAAverage current (50 MHz, 2×75Ω) 10 mA 28 mATHD fsignal=1 MHz, fclock=27 Ms/s −58 dB −60 dBTHD fsignal=5 MHz, fclock=100 Ms/s −50 dB −44 dB

7.8.3 Comparison

Table 7.3 compares the specifications of the two 10-bit video digital-to-analogconverters.

Remarkable differences are the differential linearity error and the distortion. TheDNL error in the current digital-to-analog is a direct effect of the current sourcemismatch: especially between the coarse and fine sections. In the voltage digital-to-analog this problem is circumvented by a fully unary approach: 1024 resistors inseries are used. The consequences are of course seen in a larger area. The harmonicdistortion has different origins in the two converters: in current digital-to-analogconverters the non-linear behavior of the large output diffusion node and the outputtransconductance of the current sources is important. The distortion in the voltagedigital-to-analog converter is caused by the limited performance of the driver stagein the output buffer. The modulation of the switch resistance in the resistive digital-to-analog is effectively canceled by the ladder organization, while the reduced swingscheme of the current source switching limits the switch distortion in the currentdigital-to-analog converter.

The dynamic behavior of the digital-to-analog converter is determined by theoutput pole: in the current digital-to-analog converter this is the dominant polewith a 25 pF/75 Ω load. The opamp that implements the buffer of the resistivedigital-to-analog converter sees this pole as its second pole because the internalMillercompensation is the dominant pole. The buffered output is consequentlyslower than the current output, which is seen in differences in the rise/fall time.In most systems the values reported here will be sufficient.


The minimum value for the output code is significantly larger than 0 V for abuffered output because a minimum saturation voltage is needed in the output stage.

The difference in power dissipation is less pronounced because there is moreoverhead for ladders and biasing in a voltage domain. Even so, a factor of 1.5 to 2.8remains.

Voltage domain digital-to-analog converters route about 75% of their averagecurrent into the 75 Ω output load; with those (system-determined) output loads thepotential for further power reduction seems to be low on an implementation level.

A high-speed digital-to-analog converter can be chosen if system requirementsare mapped onto these specifications.

7.8.4 Algorithmic Charge-Based Digital-to-Analog Converter

Algorithmic principles [49, 164, 165] allow to realize digital-to-analog convert-ers for high-resolution application in CMOS switched-capacitor technology. Themajor problem which has to be solved in many high-resolution converters basedon switched-capacitor techniques, is performance loss due to opamp offset andmismatching in capacitor values. This digital-to-analog converter is based on analgorithm which ensures monotonicity despite offset and capacitor mismatch.

For the implementation of an N-bits converter the basic digital-to-analog conver-sion formula is rewritten:

Vout =VLSB(a020 + a121 + · · ·+ ap2p + · · ·+ aN−12N−1) =VLSB(WLSB +WMSB2p),

(7.44)

where WLSB denotes the digital word formed by the p least significant bits:(a0 . . .ap−1) and WMSB is the digital word formed by the (N − p) most significantbits (ap . . .aN−1). Under the constraint that coefficients ai, WLSB, and WMSB arenonnegative integers this equation belongs to the class of “diophantic equations.”Diophantic equations are composed of polynomials with only integer coefficientsand integer variables. Direct implementation in CMOS switched-capacitor tech-nique could be done in a two-stage schematic as in Fig. 7.49 by generating theanalog value of an LSB at the output of section A. This VLSB is WLSB timestransferred to section B: Vout = VLSB ×WLSB. Now the output of section A israised to 2pVLSB and WMSB transfers take place to section B, resulting in Vout =(WLSB + 2pWMSB)VLSB. This implementation leads however to a signal-dependentoffset at the output. The offset of section B Voff,B is transferred (WMSB+WLSB) timesinto the output signal:

Vout = (WLSB + 2pWMSB)VLSB +(WMSB +WLSB)Voff,B (7.45)

thereby creating a nonlinear dependence and signal distortion.


Fig. 7.49 Basic switched-capacitor network with the timing diagram for converting “1011010”[164]

The contribution of the offset of section B at the output is made constant bykeeping the number of charge transfers of section B constant for the conversion ofany code. This can be obtained by rewriting the last part of Eq. 7.44 in:

Vout =VrefC1C3

C2C4(WMSB(2

p −WLSB)+ (WMSB+ 1)WLSB). (7.46)

If M1 through M4 are the sequential numbers of transfers, where M1 and M3 denotethe number of transfers of section A and M2 and M4 are the transfers of section B,then the choice:

M1 = WMSB,

M2 = 2p −WLSB,

M3 = 1,

M4 = WLSB

results in M2+M4 = 2p transfers of the offset of section B, which is no longer signaldependent. In the lower part of Fig. 7.49 the transfers for N = 7 and p = 4 have beenindicated. Equation 7.46 can be interpreted as an interpolation algorithm: sectionA forms voltages which are proportional to WMSB and WMSB + 1, while section B


Table 7.4 Measuredperformance of thealgorithmic digital-to-analogconverter

DC resolution (monotonicity) 15 bitS/(N+THD) 74 dBDynamic range 87 dBSample frequency 44 kHzClock frequency 5.6 MHzPower consumption (2.5 μm CMOS) 22 mW

interpolates in 2p cycles between these values according to the value of WLSB. Themaximum number of charge transfers is 2p + 2N−p. The fixed offset of section A isadded to VLSB, resulting in a gain error, and the offset of section B is multiplied by2pC3/C4 which is signal independent and added to the output voltage. The capacitorratios form a multiplication factor for the complete conversion, thereby influencingonly the absolute gain. With a capacitor ratio of 2−p a maximum swing at all opampoutputs is obtained.

The principle described by Eq. 7.46 has been the basis of the implementation ofa 15-bit CMOS digital-to-analog converter with three sections of 5 bits. During thefirst half of the conversion period, Eq. 7.46 is used to form the value represented bythe 10 most significant bits then Eq. 7.46 is once more used to obtain the resolutionfor the 5 least significant bits.

Two important phenomena that influence the performance of the device are thelimited DC gain and the settling of the charge transfer. In switched-capacitor filterapplications the finite gain is merely a constant factor for the transfer characteristicsfrom the input voltage to the output. In this device the input is the number oftransfers for a section. Now non-linearity occurs because the size of the transferredcharge packet changes with the gain-error voltage between the opamp inputs. Thiserror voltage is again proportional to the number of previous charge transfers. Thenon-linear transfer is mainly generated in the first section while the error magnitudein the other sections is reduced by 2−p, because the number of transfers in thesesections has been made constant:

Vout ≈VLSB(WLSB + 2pWMSB)C1C3

C2C4

(1− WMSBC1

2ADCC2

). (7.47)

With 80 dB opamp gain this effect is sufficiently reduced.The settling of the charge transfer is important as it transforms clock jitter into

output noise: the magnitude of the transferred charge from C1 to C2 is determinedby the moment where the discharging of C1 stops. With a limited unity gain of6 MHz and the second pole of the opamp at 30 MHz the charge fraction which is nottransferred is 5×10−4 after 100 ns. With an average of 80 transfers per conversion,the contribution to the noise of clock jitter to the total S/N ratio is in the order of−90 dB if the clock jitter is below 1 ns. The gain and settling requirements of theopamp have been realized by means of a folded-cascode configuration followed bya Miller stage. The input stage and the current source transistors contribute to thenoise and have to be designed carefully.


The results of the implementation are summarized in Table 7.4. Measurementshave been performed with an external sample-and-hold circuit. The DC measure-ments show the inherent monotonicity of the 15-bit digital-to-analog converter. Thenoise and distortion figures of Table 7.4 include the sample-and-hold contributions.

The main drawback of this approach is that after the converter an additionalsample-and-hold has to be used in order to create a full-time signal.

Exercises

7.1. If the 10-bit digital-to-analog converter of Fig. 7.44 is constructed from a 4-bit coarse ladder with 16 resistors of 300 Ω and 16 6-bit fine ladder sections with64 resistors of 50 Ω each, calculate the maximum resistance in this ladder to thegrounded reference terminals.

7.2. In a resistor string digital-to-analog converter all resistors are 10% larger. Whatis the change in INL? What other changes must be expected?

7.3. In a resistor string digital-to-analog converter all even-numbered resistors are2% larger, while the odd numbered are on spec. What is the change in INL and inTHD? What other changes must be expected?

7.4. Show that a differential read-out of a ladder with a second-order gradient as inFig. 7.10 (left) shows third-order distortion.

7.5. In a resistor string digital-to-analog converter all resistors are randomly 1%larger or smaller. What is the change in INL, THD, and SNR? What other changesmust be expected?

7.6. The divider in the lower schematic of Fig. 7.15 has a redundant transistor “1T,”What are the consequences if this transistor is removed?

7.7. Compare the binary sections of Fig. 7.15 (upper and lower). Make an estimateof the DNL difference for an equal number of bits in the binary sections.

7.8. A 5-bit fine-resistor string is directly via switches connected to a 5-bit coarseresistor string. As a consequence current from the coarse string will run via the fine-resistor string. The resistors of the coarse string are 100 Ω each. What should be thevalue of the fine resistors if the maximum DNL due to the resistive loading of thecoarse string must be less than 0.5 LSB?

7.9. Connect in the previous example a current source to both ends of the fineladder. Does this resolve the DNL problem? Is this solution free of other DNLproblems?

7.10. An 8-bit unary current-steering digital-to-analog converter is driving a 1 kΩload. Each current source has a parallel impedance of 5 MΩ and 0.2 pF. Sketchthe resulting distortion behavior over frequency. Now the unused current is fed

Exercises 323

in a second 1 kΩ load allowing differential operation. There is a mismatch of 1%between both load resistors. Sketch the distortion.

7.11. An 8-bit digital-to-analog converter based on a resistor string, suffers from alinear gradient of 1% over the entire structure. What is the INL, DNL, and THD?

7.12. Replace in an R-2R ladder the resistors by MOS transistors. Under whatcircumstances can this MOS-2MOS ladder be used as a digital-to-analog converter?Estimate in a 0.18 μm technology the performance for a 0.5 V reference voltage.

7.13. In a current-steering digital-to-analog converter the current sources sufferfrom 5% random mismatch. What DNL can be achieved for a 12-bit unaryarchitecture? How much resolution can be implemented in binary format if aDNL≤ 0.5 LSB must be achieved for 99.7% of the samples?

7.14. The current sources of a current-steering digital-to-analog converter mustachieve a random mismatch of σI/I < 1%. What are the W,L values for a CMOS65transistor if VGS −VT < 0.3 V? Use the technological data from Table 2.20.

7.15. Due to mismatches the INL pattern of an 8-bit binary architecture digital-to-analog converter shows steps of 1 LSB at 1/8, 2/8,. . . ,7/8 of the scale. Calculate thedistortion.

7.16. How much distortion is caused by a gradient of 2%.

7.17. Due to unpredictable wiring patterns, the top-plate connections of the capac-itors in Fig. 7.23 and 7.25 can experience a 1% additional parasitic capacitance toground. What will be the consequence for the achievable resolution?

7.18. A spurious level of −80 dB is required for a digital-to-analog converter. Whatis the maximum gradient that can be tolerated and what is the maximum randommismatch?

7.19. A digital-to-analog converter uses an output buffer. What is the maximumfrequency sine wave of 1 Vpeak–peak that can be delivered to a 3 pF capacitor if theoutput current is limited to 100 μA? What changes if a 10 kΩ resistor is connectedparallel to the capacitor?

7.20. A data-weighted averaging algorithm is used to eliminate conversion errorsin a bandwidth located around fs/8. Construct a sample sequence that will reducethe errors in that bandwidth; use [147].

7.21. Modify Example 7.4 by expanding the approximation to 1/(1−a)≈ (1+a+a2) |a| � 1. Show that an odd distortion component remains.

analog-to-digital conversion || digital-to-analog conversion

Documents