analog-to-digital conversion btech iii

8/2/2019 Analog-To-Digital Conversion Btech III

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Introduction

Signals in real world: light, sound,temp,pressure,

-When you scan a picture with a scanner what the scanner isdoing?? (ADC)

It is taking the analog information provided by the picture (light)and converting into digital .

A digital signal is superior to an analog signal because it is morerobust to noise and can easily be recovered, corrected andamplified. For this reason, the tendency today is to change an

analog signal to digital data.


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Introduction

An analog to digital converter converts analog voltages to digitalinformation that can be used by a computer, Microprocessor,microcontroller

The digital data produced by an analog to digital converter is onlyapproximately proportional to the analog input.

That's because a perfect conversion is impossible due to the factthat digital information changes in steps, whereas analog is virtuallycontinuous.

An analog-to-digital converter (abbreviated ADC, A/D or A to D)isan electronic circuit that converts continuous signals to discrete

digital numbers.-The digital output may be using different coding schemes, such as

binary and two's complement binary. However, some non-electronicor only partially electronic devices, such as shaft encoder, can alsobe considered as ADCs.


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Introduction

Consists of

Amplifier, Filters

Sample and Hold Circuit, Multiplexer

ADC


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Types of data

Analog data (All values on the time and amplitude are allowed).

Digital data (Only a few amplitude levels are allowed).


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Analog-to-Digital Converter (How it work)

Before we sample, we have to filter the signal to limit themaximum frequency of the signal as it affects the sampling rate.

Filtering should ensure that we do not distort the signal, ie removehigh frequency components that affect the signal shap Sampling.

What the ADC circuit does is to take samples from the analogsignal from time to time. Each sample will be converted into anumber, based on its voltage level (as in the figure).


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Resolution.The resolution of the converter indicates the number of discrete values it can produceover the range of analog values. The values are usually stored electronically in binaryform, so the resolution is usually expressed in bits. In consequence, the number ofdiscrete values available, or "levels", is usually a power of two. For example, an ADCwith a resolution of 8 bits can encode an analog input to one in 256 different levels,since 28 = 256. The values can represent the ranges from 0 to 255 (i.e. unsignedinteger) or from 128 to 127 (i.e. signed integer), depending on the application.

Resolution can also be defined electrically, and expressed in volts. The minimumchange in voltage required to guarantee a change in the output code level is calledthe LSB(least significant bit, since this is the voltage represented by a change in theLSB). The resolution Qof the ADC is equal to the LSBvoltage. The voltage resolutionof an ADC is equal to its overall voltage measurement range divided by the numberof discrete voltage intervals:
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Terminologies

Converter Resolution

The smallest change required in the analog input of an ADC tochange its output code by one level

Converter Accuracy

The difference between the actual input voltage and the full-scale weighted equivalent of the binary output code

Maximum sum of all converter errors including quantization error

Conversion Time

Required time (tc) before the converter can provide valid outputdata

Converter Throughput Rate

The number of times the input signal can be sampledmaintaining full accuracy

Inverse of the total time required for one successful conversion

Inverse of Conversion time if No S/H(Sample and Hold) circuit is

used


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All ADCs work by sampling their input at discrete intervals of time. Their output istherefore an incomplete picture of the behaviour of the input. There is no way ofknowing, by looking at the output, what the input was doing between one samplinginstant and the next. If the input is known to be changing slowly compared to thesampling rate, then it can be assumed that the value of the signal between twosample instants was somewhere between the two sampled values. If, however, theinput signal is changing rapidly compared to the sample rate, then this assumption isnot valid.

If the digital values produced by the ADC are, at some later stage in thesystem, converted back to analog values by a digital to analog converter orDAC, it is desirable that the output of the DAC be a faithful representation ofthe original signal. If the input signal is changing much faster than the samplerate, then this will not be the case, and spurious signals called aliaseswill beproduced at the output of the DAC. The frequency of the aliased signal is thedifference between the signal frequency and the sampling rate. For example,

a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed as a500 Hz sine wave. This problem is called aliasing.

To avoid aliasing, the input to an ADC must be low-pass filtered to removefrequencies above half the sampling rate. This filter is called an anti-aliasingfilter, and is essential for a practical ADC system that is applied to analogsignals with higher frequency content.
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1. DAC

In an electronic circuit, a combination of high voltage (+5V) and low voltage(0V) is usually used to represent a binary number. For example, a binary

number 1010 is represented by

Weighting 23 22 21 20

Binary Digit 1 0 1 0

State +5V 0V +5V 0V

DACs are electronic circuits that convert digital, (usually binary) signals (forexample, 1000100) to analog electrical quantities (usually voltage) directlyrelated to the digitally encoded input number.


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DACs are used in many other applications, such as voice synthesizers,automatic test system, and process control actuator. In addition, they allowcomputers to communicate with the real (analog) world.

R

egister

VoltageSwitch

Resistive

Summing

Network

Amplifier

Input Binary

NumberAnalog Voltage

Output


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Register: Use to store the digital input (let itremain a constant value) during the conversion

period.

Voltage: Similar to an ON/OFF switch. It isclosed when the input is 1. It is opened when

the input is 0.

Resistive Summing Network: Summation of the

voltages according to different weighting.

Amplifier: Amplification of the analog accordingto a pre-determined output voltage range. For

example, an operation amplifier


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The two most popular types of resistive summing networks are:

Weighted binary resistance type, and

Ladder resistance (R-2R) type

A i l DAC b i l t d i i it k
http://www.siliconfareast.com/opamps.htmhttp://www.siliconfareast.com/opamps.htmhttp://www.siliconfareast.com/opamps.htmhttp://www.siliconfareast.com/opamps.htm


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A simple DAC may be implemented using an op-amp circuit known as a

summer, so named because its output voltage is the sum of its inputvoltages.

Each of its inputs uses a resistor of different binary weight, such that ifR0=R, then R1=R/2, R2=R/4, R3=R/8,.., RN-1=R/(2

N-1).

The output of a summer circuit with N bits is: Vo = -VR (Rf / R) (SN-12

N-1 + SN-22N-2+...+S02

0)

where VR is the voltage to which the bit is connected when the digital inputis '1'. A digital input is '0' if the bit is connected to 0V (ground).

A 4-bit summer circuit is shown in Figure

An Op Amp Summer Circuit Used as a DAC; whereR0 = 2 R1 = 4 R2 = 8 R3
http://www.siliconfareast.com/opamps.htmhttp://www.siliconfareast.com/opamps.htmhttp://www.siliconfareast.com/opamps.htmhttp://www.siliconfareast.com/opamps.htm


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One problem with this circuit is the wide range of resistor values needed to build aDAC with a high number of digital inputs.

Putting thin-film resistors that come in a wide range of values (e.g., from a few ksto several Ms) on a single semiconductor chip can be very difficult, especially if high

accuracy and stability are required.

A better-designed and more commonly-used circuit for digital-to-analog conversionis known as the R-2R ladder DAC, a 4-bit version of which is shown in Fig.

It consists of a network of resistors with only two values, R and 2R.

The input SN to bit N is '1' if it is connected to a voltage VR and '0' if it is grounded.

Thevenin's Theorem may be applied to prove that the output Vo of an R-2R ladderDAC with N bits is:

Vo = VR/2

N (SN-12N-1 + SN-22

N-2+...+S020).


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A 4-bit R-2R Ladder DAC

Thus, the output of the R-2R ladder in Figure 2 is Vo = VR/24 (S32

3+S222+S12

1+S020)

or Vo = VR (S3/ 2 + S2/ 4 + S1 / 8 + S0/ 16) .

In effect, contribution of each bit to the analog output is proportional to its binary

weight.


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Since Analog-to-Digital converters were invented, differentdesigns were made to fabricate them. The most five knowndesigns are:

Parallel design (Flash ADC). Digital-to-Analog Converter-based design.

Integrator-based design.

Sigma-Delta design.

Pipeline design.


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Parallel design (flash ADC)

Vref is a stable reference voltage provided by a precision voltage regulator as part ofthe converter circuit, not shown in the schematic. As the analog input voltageexceeds the reference voltage at each comparator, the comparator outputs willsequentially saturate to a high state. The priority encoder generates a binary numberbased on the highest-order active input, ignoring all other active inputs.

It works by comparing the input voltage of the analog signal to a reference voltage,which would be the maximum value achieved by the analog signal.

For example, if the reference voltage is of 5 volts, this means that the peak of theanalog signal would be 5 volts.

On an 8-bit ADC when the input signal reached 5 volts we would find a 255(11111111) value on the ADC output, i.e. the maximum possible value.

ADCs of this type have a large die size, a high input capacitance, and are prone toproduce mistakes on the output (by outputting an out-of-sequence code).

They are often used for video or other fast signals.


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As the counter (CTR in figure) counts up with each clock pulse, theDAC outputs a slightly higher (more positive) voltage.

This voltage is compared against the input voltage by thecomparator.

If the input voltage is greater than the DAC output, the comparator'soutput will be high and the counter will continue counting normally.

Eventually, though, the DAC output will exceed the input voltage,causing the comparator's output to go low.

This will cause two things to happen: first, the high-to-low transition

of the comparator's output will cause the shift register (SRG) to"load" whatever binary count is being output by the counter, thusupdating the ADC circuit's output;


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secondly, the counter will receive a low signal on the active-low LOAD input, causing itto reset to 00000000 on the next clock pulse.The effect of this circuit is to produce a DAC output that ramps up to whatever level the

analog input signal is at, output the binary number corresponding to that level, andstart over again.


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Plotted over time, it looks like this:Note how the timebetween updates(new digital outputvalues) changesdepending on how

high the input voltageis.For low signal levels,the updates are ratherclose-spaced.For higher signallevels, they arespaced further apartin time:


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For many ADC applications, this variation in updatefrequency (sample time) would not be acceptable.

This, and the fact that the circuit's need to count all theway from 0 at the beginning of each count cycle makes

for relatively slow sampling of the analog signal, placesthe digital-ramp ADC at a disadvantage to other counterstrategies.


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Successive approximation ADC

One method of addressing the digital ramp ADC's shortcomings is the so-calledsuccessive-approximationADC.

The only change in this design is a very special counter circuit known as asuccessive-approximation register.

Instead of counting up in binary sequence, this register counts by trying all values ofbits starting with the most-significant bit and finishing at the least-significant bit.

Throughout the count process, the register monitors the comparator's output to see ifthe binary count is less than or greater than the analog signal input, adjusting the bitvalues accordingly.

The way the register counts is identical to the "trial-and-fit" method of decimal-to-binary conversion, whereby different values of bits are tried from MSB to LSB to get abinary number that equals the original decimal number.

The advantage to this counting strategy is much faster results: the DAC outputconverges on the analog signal input in much larger steps than with the 0-to-full countsequence of a regular counter.


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The way successive approximation works is through constantlycomparing the input voltage to a known reference voltage until thebest approximation is achieved.

At each step in this process, a binary value of the approximation isstored in a successive approximation register (SAR).

the SAR uses a reference voltage for conversion.


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Integrator-based design

There are few ways of designing analog-to-digital converters using anintegrator. We will discuss one of them: the single-slope ADC.

We can see a single-slope ADC in the figure. We can note that it is very similar to a ramp counter ADC, as it uses a

counter, but instead of using a DAC, it uses a circuit called integrator, which

is basically formed by a capacitor, a resistor and an operational amplifier.

The MOSFET transistor makes the necessary control circuit.


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An op-amp circuit called an integrator is used to generate a sawtoothwaveform which is then compared against the analog input by acomparator.

The time it takes for the sawtooth waveform to exceed the input signalvoltage level is measured by means of a digital counter clocked with aprecise-frequency square wave (usually from a crystal oscillator).

When the comparator output is low (input voltage greater than integratoroutput), the integrator is allowed to charge the capacitor in a linear fashion.Meanwhile, the counter is counting up at a rate fixed by the precision clockfrequency.

The time it takes for the capacitor to charge up to the same voltage level asthe input depends on the input signal level and the combination of -Vref, R,and C. When the capacitor reaches that voltage level, the comparator

output goes high, loading the counter's output into the shift register for afinal output. The IGFET is triggered "on" by the comparator's high output, discharging

the capacitor back to zero volts. When the integrator output voltage falls tozero, the comparator output switches back to a low state, clearing thecounter and enabling the integrator to ramp up voltage again.


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Sigma-Delta ADC In a converter, the analog input voltage signal is connected to the input of an

integrator, producing a voltage rate-of-change, or slope, at the output correspondingto input magnitude.

This ramping voltage is then compared against ground potential (0 volts) by acomparator.

The comparator acts as a sort of 1-bit ADC, producing 1 bit of output ("high" or "low")depending on whether the integrator output is positive or negative. The comparator'soutput is then latched through a D-type flip-flop clocked at a high frequency, and fedbackto another input channel on the integrator, to drive the integrator in the directionof a 0 volt output. The basic circuit looks like this:


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If the integrator output is positive, the first comparator will output a"high" signal to the D input of the flip-flop.

At the next clock pulse, this "high" signal will be output from the Qline into the noninverting input of the last comparator.

This last comparator, seeing an input voltage greater than thethreshold voltage of 1/2 +V, saturates in a positive direction, sendinga full +V signal to the other input of the integrator. This +V feedbacksignal tends to drive the integrator output in a negative direction.

If that output voltage ever becomes negative, the feedback loop willsend a corrective signal (-V) back around to the top input of theintegrator to drive it in a positive direction.

This is the delta-sigma concept in action: the first comparator

senses a difference() between the integrator output and zero volts.The integrator sums() the comparator's output with the analoginput signal.


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ADC0808/ADC08098-Bit P Compatible A/D Converters with 8-Channel

Multiplexer

Features Easy interface to all microprocessors

Operates ratiometrically or with 5 VDC or analog span

adjusted voltage reference

No zero or full-scale adjust required 8-channel multiplexer with address logic

0V to 5V input range with single 5V power supply

Outputs meet TTL voltage level specifications

Standard hermetic or molded 28-pin DIP package

28-pin molded chip carrier package

successive approximation as the conversion technique.

The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperaturedependence, excellent long-term accuracy and repeatability, and consumes minimalpower.

applications from process and machine control to consumer and automotiveapplications.


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Basic Successive Approximation ADC(Feedback Subtraction ADC)


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It performs conversions on command.

In order to process ac signals, SAR ADCs must have an input sample-and-hold (SHA) to keep the signal constant during the conversion cycle.

On the assertion of the CONVERT START command, the sample-and-hold(SHA) is placed in the holdmode, and the internal DAC is set to midscale.

The comparator determines whether the SHA output is above or below theDAC output, and the result (bit 1, the most significant bit of the conversion)is stored in the successive approximation register (SAR).

The DAC is then set either to scale or scale (depending on the value ofbit 1), and the comparator makes the decision for bit 2 of the conversion.

The result is stored in the register, and the process continues until all of thebit values have been determined.

When all the bits have been set, tested, and reset or not as appropriate, thecontents of the SAR correspond to the value of the analog input, and theconversion is complete.


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Functional Description

Multiplexer.

The device contains an 8-channel single-ended analog signal multiplexer.

A particular input channel is selected by using the address decoder.

Table 1 shows the input states for the address lines to select any channel.

The address is latched into the decoder on the low-to-high transition of the

address latch enable signal.


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The first output transition occurs when the analog signal has reached +12 LSB and

succeeding output transitions occur every 1 LSB later up to full-scale. The successive approximation register (SAR) performs 8 iterations to approximate the

input voltage.

For any SAR type converter, n-iterations are required for an n-bit converter.

The A/D converters successive approximation register (SAR) is reset on the positive edge

of the start conversion (SC) pulse.

The conversion is begun on the falling edge of the start conversion pulse.

A conversion in process will be interrupted by receipt of a new start conversion pulse.

Continuous conversion may be accomplished by tying the end-of-conversion (EOC) outputto the SC input.

If used in this mode, an external start conversion pulse should be applied after power up.

End-of-conversion will go low between 0 and 8 clock pulses after the rising edge of startconversion.


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At the beginning of the conversion interval, the signal goes high (or low) andremains in that state until the conversion is completed, at which time it goeslow (or high).

The trailing edge is generally an indication of valid output data, but the datasheet should be carefully studiedin some ADCs additional delay is

required before the output data is valid.

An N bit conversion takes N steps. In an 8 bit converter, the DAC must settle to 8 bitaccuracy before the bit decision is made, whereas in a 16 bit converter, it must settleto 16 bit accuracy, which takes a lot longer.

In practice, 8 bit successive approximation ADCs can convert in a few hundred

nanoseconds, while 16 bit ones will generally take several microseconds.


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overall accuracy and linearity of the SAR ADC is determined primarily by the internalDAC.

Until recently, most precision SAR ADCs used laser-trimmed thin-film DACs toachieve the desired accuracy and linearity.

The thin-film resistor trimming process adds cost, and the thin-film resistor valuesmay be affected when subjected to the mechanical stresses of packaging.

For these reasons, switched capacitor (or charge-redistribution) DACs have becomepopular in newer SAR ADCs.

The advantage of the switched capacitor DAC is that the accuracy and linearity isprimarily determined by high-accuracy photolithography, which in turn controls thecapacitor plate area and the capacitance as well as matching.

In addition, small capacitors can be placed in parallel with the main capacitors whichcan be switched in and out under control of autocalibration routines to achieve highaccuracy and linearity without the need for thin-film laser trimming.


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Timing Diagram

analog-to-digital conversion btech iii

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