digital-to-analog & analog-to- digital conversion anuroop gaddam
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Digital-to-Analog & Analog-to-Digital ConversionAnuroop Gaddam
DAC and ADC
Digital-to-Analog Conversion (DAC) Converts a binary value to a scaled ‘analog’ voltage Used for controlling systems that require an analog input.
DC servo motor
Resistive heater, etc.
Analog-to-Digital Conversion (ADC) Converts a continuous analog voltage into discrete binary
values Used to translate continuous physical phenomena into a language the
computer understands.
Analogue Digital Conversion
Analog and digital data were briefly mentioned at the start
A digital signal is an approximation of an analog one
Levels of signal are sampled and converted to a discrete bit pattern.
Digital signal processing is used, for example, to enhance and compress images, to process sounds to generate speech, etc, etc.
Step (discrete) Approximation
time
level
sample
“stair-step” approximation of original signal
hold time for sample
more samples give greater accuracy
Objectives To understand how a digital value can be converted to an
analogue value To draw circuits and explain the operation of two digital to
analogue converters: the binary weighted resistor network and the R-2R ladder network
To draw the block diagram and explain the operation of three analogue to digital converters: flash, counter ramp and successive approximation
To be able to calculate the conversion time for an analogue to digital converter
To be able to explain the sampling rule To be able to describe the basic design of a sample and
hold circuit and explain how it works
Buffering the resistor network Best solution is to follow the resistor network with a buffer amplifier
Has high impedance, practically no current flows
All input currents sum at S and go through Rf
Vo = -IfRf
MSB
LSB 4-bi
t re
gist
er
-
+
R
2R
4R
8R
I1
I2
I3
I4
Rf
If
IS
Vo
Vo= - If ´ Rf = -(I1+ I2 + I3+ I4) ´ Rf
Digital-to-Analogue Example
Calculate the output voltage for an input code word 0110 if a logic 1 is 10V and a logic 0 is 0V, and R = RF=1k
I1 = I4 = 0
I2 = 10v / 2R = 10 / 2k = 5 mA
I3 = 10v / 4R = 10 / 4k = 0.25 mA
Vo = -If x Rf = -(0.0075) x 1000 = -7.5 volts
Vo= - If ´ Rf = -(I1+ I2+ I3+ I4) ´ Rf
The binary weighted resistor network
Seldom used when more than 6 bits in the code word
to illustrate the problem consider the design of an 8-bit DAC if the smallest resistor has resistance R
what would be the value of the largest resistor?
what would be the tolerance of the smallest resistor?
Very difficult to manufacture very accurate resistors over this range
R-2R Ladder DAC (4-bit)
2R 2R
R
2R
R
2R
R
+-
R
Vref
Vout
MSB LSB
2R
bit 3
bit 2
bit 1
bit 0
a b c d
“switches”
What are the voltages at nodes a - d?
Develop a general expression for Vout
Use the general expression to determine Vout if the switch associated with bit 2 is connected to the amplifier.
Digital to Analog Converter (DAC)
R-2R Ladder DAC is widely used
It’s a programmable summing amplifier
The smallest change in voltage (the ‘resolution’) that can be output by the DAC is determined by the number of bits:
Resolution = Vref / 2N , where N is the number of bits
Given Vref = 5 V, and a 10-bit DAC, what is the smallest change in voltage that the DAC can output?
The R-2R Ladder Resistor Network Has a resistor network which requires resistance values that differ 2:1 for any sized
code word
The principle of the network is based on Kirchhoff's current rule
The current entering N must leave by way of the two resistors R1 and R2
I N R2
R1
•
The R-2R Ladder Resistor Network
Works on a current dividing network
Resistance to right of B = 1/(1/2R + 1/2R) Resistance to right of A = R +2R/2 = 2R Current divides I1 = I/2 I2 = I/4 divides again
A BI I1
I1 I2
R
2R 2R 2R
The R-2R Ladder Resistor Network The network of resistors to the right of A have an equivalent resistance of 2R,
and so the right hand resistance can be replaced by a copy of the network
2R
I1=I/2
RI/2
2R
I2=I/4
RI/4
2R
I3=I/8
I/8
2R
I
Bit Current3 I/22 I/41 I/80 I/16
bit 3 bit 2 bit 1 bit 0
The R-2R Ladder Resistor Network
2R
I/4
2R 2R
I
MS
B
LSB
4-bit register
I/8 I/16I/2
2RVs
-
+
Rf
Vo
2R
RRR
Vo =-R f(b3I 2+ b2 I 4+ b1I 8+b0I 16)
The state of the bits is used to switch a voltage source
Example
For the circuit shown above with I = 10 mA and Rf = 2k, calculate the output voltage V0 for an input code word 1110.
2R
I/4
2R 2R
I
MSB
LSB
4-bit register
I/8 I/16I/2
2RVs
-
+
Rf
Vo
2R
RRR
Vo =-R f(b3I 2+ b2 I 4+ b1I 8+b0I 16)
Example
I = 10mA
Rf = 2k
input code word 1110
Vo = -2000( 0.01/2 + 0.01/4 + 0.01/8 + (0 x 0.1)/8 )
= - 2000 * (0.04 + 0.02 + 0.01) / 8
= 17.5 volts
Quantisation
Suppose we want to use a D-A converter to generate the sawtooth waveform (graph shown on the left)
End up with stair-case waveform (graph shown on the right)
The 16 possible values of the D-A converter output are called the quantisation levels
The difference between two adjacent quantisation levels is termed a quantisation interval
voltage
time
0000
0001
0010
1111
0000...
voltage
time
Quantisation Error Difference between the two waveforms is the quantisation error
Maximum quantisation error is equal to half the quantisation interval
One way to reduce the quantisation error (noise) is to increase the number of bits used by the D-A converter
111
110
101
100
011
010
001
000
samples
bands or quanta1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
quantisation interval
Quantisation NoiseThe voltage produced by the DA convertor can be regarded as the original signal plus noise:
This is the quantisation noise.
Successive Approximation ADC
http://upload.wikimedia.org/wikipedia/en/6/61/SA_ADC_block_diagram.png
A successive approximation ADC is like a beam balance
Stiffler, A.K. (1992). Design with microprocessors for mechanical engineers. McGraw-Hill, NY.
8-bit Successive Approximation ADC
From Necsulescu, D., (2002). Mechatronics, Prentice-Hall, New Jersey.
ATmega ADC system• Clock input of 50
kHz to 200 kHz for maximum resolution
• Voltage reference (AVCC) (input voltage range) is selectable
• Default is to Vcc=5 V
• 1.1 V • Something
else on AREF• Be careful!
• See http://arduino.cc/en/Reference/AnalogReference
It takes time to complete an ADC conversion
First takes 25 ADC clock cycles
Subsequent, 13 ADC clock cycles
Source: ATmega328 data sheet, p. 251