586 ieeetransactionsonreliability,vol.64,no.2,june2015...

586 IEEE TRANSACTIONS ON RELIABILITY, VOL. 64, NO. 2, JUNE 2015

A 3 Dimensional Built-In Self-Repair Scheme forYield Improvement of 3 Dimensional Memories

Wooheon Kang, Changwook Lee, Hyunyul Lim, and Sungho Kang, Member, IEEE

Abstract—A 3-dimensional Built-In Self-Repair (3D BISR)scheme is proposed for 3-dimensional (3D) memories. Theproposed 3D BISR scheme consists of two phases: a paralleltest-repair phase, and a serial test-repair phase. After all memorydice are simultaneously tested, only the faulty memory diceare serially tested and repaired using one Built-In RedundancyAnalysis (BIRA) module. Thus, it is a faster test-repair with lowarea overhead. The proposed BIRA algorithm with a post-shareredundancy scheme performs exhaustive searches for all combi-nations of spare rows and columns. Experimental results showthat the proposed 3D BISR is up to two times faster than the 3Dserial test-serial repair BISR when seven 2048 2048 bit memorydice are stacked. The proposed 3D BISR requires 44.55% of thearea in comparison to a 3D parallel test-parallel repair BISR forfour stacked memory dice (one 128 K RAM, two 256 K RAMs,and 512 K RAM). The yield of 3D memories is the highest dueto the exhaustive search BIRA algorithm with the post-shareredundancy scheme as shown in various experimental results.Index Terms—3D memory, 3D built-in self-repair, area over-

head, built-in redundancy analysis, built-in self-test, repair rate,yield.

ACRONYMS AND ABBREVIATIONS

2D Two Dimensional3D Three DimensionalBIST Built-In Self-TestBIRA Built-In Redundancy AnalysisBISR Built-In Self-RepairCAM Content Addressable MemoryCRESTA Comprehensive Real-time Exhaustive Search

Test and AnalysisESP Essential Spare PivotingIS Intelligent SolveISF Intelligent Solve First

Manuscript received March 24, 2014; revised May 27, 2014, June 19, 2014,August 17, 2014, and September 16, 2014; accepted March 02, 2015. Date ofpublication March 16, 2015; date of current version June 01, 2015. This workwas supported by a National Research Foundation of Korea (NRF) grant fundedby the Korea government (MEST) (No. 2012R1A2A1A03006255). AssociateEditor: W.-T. Chien.W. Kang, H. Lim, and S. Kang are with the Department of Electrical and

Electronic Engineering, Yonsei University, Seoul, Korea (e-mail: [email protected]; [email protected]; [email protected]).C. Lee is with the Probe Test Engineering Team, SK Hynix, Inc., Icheon-si,

Gyeonggi-do, Korea (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TR.2015.2410274

KGD Known-Good-DiceLRM Local Repair MostRA Redundancy AnalysisRM Repair MostPTPR Parallel Test-Parallel RepairSFCC Selected Fail Count ComparisonSTSR Serial Test-Serial RepairTSV Through-Silicon-Via

NOTATIONS

Number of rows of memoryNumber of columns of memoryNumber of diceNumber of spare rowsNumber of spare columns(Spare) row(Spare) columnThe average number of faultsA parameter of the fault density variation

I. INTRODUCTION

T HREE DIMENSIONAL (3D) memory using Through-Silicon-Via (TSV) has been regarded as a good design

to overcome the limitations of Two Dimensional (2D) memorytechnology. There are many benefits of TSV technology in-cluding small latency, high density, high bandwidth, and lowpower consumption [1]–[3].A DDR3 DRAM using TSV technology is proposed because

homogenousmemories are good for 3Dmemory technology [4].To make good 3D memories, 3D memory is typically composedof known-good-dice (KGD), which are repaired with self-con-tained spare memories. When the number of stacked memoriesincreases, the yield loss of 3D memories becomes more critical.If there is an irreparable memory die in a 3D memory unit, the3D memory is also irreparable, and other repairable memorydice stacked in the 3D memory are wasted. In addition, 3D pro-cessing might lead to new inter-die and TSV-related defects.Thus, yield improvement is one of the major concerns with 3Dmemory. Efficient tests and repair methods are being studied toguarantee the yield and quality of 3D memories.Before memories are stacked, they are tested and repaired to

be KGD. There are many Built-In Self-Repair (BISR) schemes,which consist of Built-In Self-Test (BIST) and Built-In Re-dundancy Analysis (BIRA), and are proposed to test-repair

0018-9529 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

KANG et al.: 3D BUILT-IN SELF-REPAIR SCHEME FOR YIELD IMPROVEMENT OF 3D MEMORIES 587

memories [5]–[9]. Comprehensive Real-time ExhaustiveSearch Test and Analysis (CRESTA) focuses on the optimalrepair rate, which is the ratio of memories repaired by BIRA toall repairable memories of the total tested memories, and fastanalysis speed [5]. It simultaneously analyzes entire cases ofpossible solutions with several parallel sub-analyzers. Its areaoverhead increases with an increasing number of redundancies.Local Repair Most (LRM) and Essential Spare Pivoting (ESP)mainly focus on reducing the area overhead in terms of storagerequirements with a simple RA algorithm [6]. Although theirrepair rates are not optimal, these two BIRAs have inspiredthe creation of other algorithms due to simplicity, and smallarea overhead. Intelligent Solve (IS) and Intelligent SolveFirst (ISF) algorithms achieve both low area overhead, and anoptimal repair rate which is defined as the ratio of the numberof repaired memories to the number of repairable memories [7].However, these two algorithms take a lot of time to completethe RA in cases with complex fault distributions. Selected FailCount Comparison (SFCC) [8] achieves a low area overheadand an optimal repair rate, and it also reduces the search spaceby building a search tree based on the line faults. BRANCH [9]analyzer analyzes all nodes concurrently within a branch forcombinations of 2D spares.There are three bonding technologies used in 3D integrated

circuit (IC) fabrication: wafer-to-wafer (W2W), die-to-wafer(D2W), and die-to-die (D2D). Wafers with the same size of diceare directly bonded together in the W2W method. The W2Wmethod offers the highest throughput, and a high TSV den-sity. However, it can result in yield loss because a bad die canbe bonded to a good die. On the other hand, D2W and D2Dmethods allow the use of different wafer and die sizes becausethe dice are bonded after dicing. The D2W and D2D methodscan improve the yield of 3D memories because of high flex-ibility. Dice are diced and tested in advance, and only gooddice are stacked. However, these methods require a more com-plex manufacturing process because dice must be aligned andintegrated with each other. This complexity results in a lowthroughput and a low TSV density. Thus, the stacking of wafersor dice heavily influences the yield of 3D memories. To solvethe matching problem, there are efficient matching algorithms[10]–[14].Even when good dice are matched and bonded to each other,

there may exist newly detected faulty cells after stacking. Thesefaulty cells are repaired using a BISR scheme for 3D memories.There are various BISR schemes for 3D memories. Among 3DBISR schemes, there are 3D BISR schemes with an inter-dieredundancy scheme, which can use redundancies betweenadjacent die with TSVs [10]–[14]. Three stacking methodswith different bonding technologies and a BISR scheme for3D memory with inter-die redundancy have been proposed[12]. The matching problem for die stacking can be convertedinto a bipartite graph describing a maximal matching problem;corresponding built-in self-repair architectures for yield en-hancement of 3D memories are proposed in [13], and [15]. In[15], each memory die has a dedicated BISR module. If oneof the BISR modules is faulty, the roles of the BISR modulescan be interchanged. A BISR scheme for 3D memories usingglobal redundancy and a remapping mechanism is designed inthe logic die [13]. Another global 3D BISR scheme parallelizesthe BISR procedure by incorporating all the stacked layers of

3D memory [16]. Because these schemes use a dedicated BISRmodule for each memory die, the area overhead for 3D BISRbecomes large.In this paper, a 3D BISR scheme is proposed for 3D memory

to improve the yield of 3D memories. The proposed 3D BISRscheme consists of two phases: a parallel test-repair phase, anda serial test-serial repair phase. Compared with the 3D ParallelTest-Parallel Repair (PTPR) BISR scheme, this scheme can re-duce the area overhead. Compared with the 3D Serial Test-Se-rial Repair (STSR) BISR scheme, this scheme can reduce thetest-repair time.

II. BACKGROUND

A. Various 3D BISR SchemesThere are two BISR methods for 3D memory: a 3D PTPR

method, and a 3D STSR method. The 3D PTPR method re-quires BIST modules and BIRA modules. The BIST andBIRA modules are proportional to the number of memory dice.Each memory die has dedicated BIST and BIRA modules. Allthe memories are concurrently tested by each BIST module. Ifthe fault is detected by BIST, the fault information is sent toBIRA because each memory die has a dedicated BIRA module.After the test is completed, RA is performed by analyzing faultinformation. Because this method requires BIST and BIRAmodules, the area overhead is the largest. However, this methodcan offer the shortest test-repair time because of the concurrenttest-repair process.The 3D STSR method requires one BIST module and one

BIRA module. Because all the memories are serially testedand repaired, there is only one BIST and one BIRA module.This method requires the smallest area overhead. However,this method has the longest test-repair time due to its serialtest-repair process.

B. Performance Criteria of 3D BISRPerformances of BISR consist of performances of BIST and

performances of BIRA. BIST performances, such as test time,fault coverage, and area overhead, depend on the test algorithm.BIRA performances, such as repair rate (i.e., yield), repair time,and area overhead, depend on the RA algorithm. The proposed3DBISR focuses on the improvement on performances of BIRAin terms of the yield, area overhead, and test-repair time.There are three main performance criteria of BISR: area over-

head, yield, and test-repair time. The area overhead of a typical2D BISR is important because BISR circuitry is embedded inthe chip, and the size of the chip is limited. Similarly, the areaoverhead of 3D BISR is significant. If each memory die has adedicated BISR module for the pre-bond test-repair, this BISRmodule is used in the post-bond test-repair. However, the sizeof the BISR module can be excessively large for the post-bondtest-repair because the number of spares in the pre-bond test-re-pair is larger than that of the post-bond test-repair. On the otherhand, all memory dice share the proposed 3D BISR, so the areaoverhead is greatly reduced compared to previous 3D BISRschemes.The yield of 3D memories is affected by the repair rates of

2D memories, and the utilization of redundancies of 3D mem-ories. If one of the stacked memory dice is not repairable, the3D memory is bad. Therefore, good memory dice, which are


bonded to the irreparable memory die, are wasted. Therefore,the optimal repair rate is required. Because the RA algorithmcomplexity for memory repair using 2-D spare cells is NP-com-plete [17], an exhaustive search is used to achieve an optimalrepair rate. In addition, because the proposed 3D BISR canachieve the optimal repair rate using exhaustive search, andadopts the post-share redundancy scheme, the yield of 3Dmemories is improved.The test-repair time of 3D memories is related to the number

of memory dice and the strategy to perform test-repair. The testtime is much longer than the repair time because the numberof memory cells is larger than the number of faulty cells. Thus,the test-repair time depends on the test methods which are theparallel test and serial test. Because all memory dice are tested atthe same time during the parallel test, the test time is the shortest.On the other hand, because each memory die is tested during theserial test, the test time is the longest. In the proposed 3D BISRscheme, it has a medium test time because the parallel test andserial test are combined.

C. Redundancy Schemes for 3D Memories

According to the time before and after a bonding procedure,the test-repair for the 3D stacked memory is classified into twotests-repairs: pre-bond, and post-bond test-repair. Because thereare differences between pre-bond and post-bond test-repair,there are four redundancy schemes: fixed redundancy scheme,inter-die redundancy scheme, all-share redundancy scheme,and post-share redundancy scheme [18]. The fixed redundancyscheme partitions the total redundancies for each repair pro-cedure according to the fault probabilities of the pre-bond andpost-bond repair processes. The inter-die redundancy schemecan use redundancies from its vertical memory die throughTSVs. Thus, bad memory dice become good 3D memoriesbecause the former can be repaired with redundancies presentin the adjacent memory dice. The all-share redundancy schemeshares all redundancies between pre-bond and post-bondrepair in a die. The post-share redundancy scheme sharesredundancies only during post-bond repair in a die. In thisscheme, limited redundancies are used in the pre-bond repair.If there are remaining redundancies after pre-bond repair, theseremaining redundancies can be used in the post-bond repair.Thus, the yield of 3D memories can be improved using variousredundancy schemes.Fig. 1 shows examples of four redundancy schemes. There

are five spare rows and five spare columns for all redundancyschemes. For the fixed redundancy scheme, there are three sparerows and three spare columns for pre-bond, and two spare rowsand two spare columns for post-bond, as shown in Fig. 1(a). Theinter-die redundancy scheme partitions the total redundanciesfor each test step the same as in the fixed redundancy scheme.The inter-die redundancy scheme then shares the given redun-dancies using TSVs between adjacent dice in each test step, asshown in Fig. 1(b). As shown in Fig. 1(c), all spare memoriesare used for pre-bond and post-bond for the all-share redun-dancy scheme. Fig. 1(d) shows the example of the post-share re-dundancy scheme. In pre-bond, only three spare rows and threespare columns are used. In post-bond, two spare rows and twospare columns are used, and the remaining spares after pre-bondare used.

Fig. 1. Examples of four redundancy schemes. (a) Fixed redundancy scheme.(b) Inter-die redundancy scheme. (c) All-share redundancy scheme. (d) Post-share redundancy scheme.

III. 3D BISR FOR 3D MEMORIES

A. Proposed 3D BISR SchemeThe proposed 3D BISR adopts a post-share redundancy

scheme to improve the yield of 3D memories. To use thepost-share redundancy scheme, each memory die should reportits available redundancies to the 3D BISR in the base die.The 3D BISR mainly consists of a BIST module and BIRAmodule located in the base die. In the base die, functional logic,peripheral circuit, and memory are also present. In the pre-bondtest-repair, the memory or memories in the base die are testedand repaired using the 3D BISR module in the base die. Also,the memory dice are tested and repaired using external au-tomatic test equipment (ATE) because the stacked memorydice do not have BISR modules. The ATE detects faulty cells,and analyzes faulty information to search for the repair solu-tion. Irreparable memory dice are discarded through pre-bondtest-repair before stacking, and only repairable memory diceare stacked [19].Fig. 2 shows an overall block diagram of the proposed

3D BISR architecture. After all memory dice are stacked, allmemory dice are tested and repaired using the BISR modulein the base die in the post-bond test-repair procedure. Becausethe memory dice can be tested in parallel, the proposed schemeuses TSVs as a bus which reaches the top die in Fig. 2.The BIST module consists of a test pattern generator, a test

address generator, and a controller. The wrapper, which isdedicated to the memory, consists of a comparator, and a faultnumber register. The test address generator and test patterngenerator generate test patterns and test addresses for executing


Fig. 2. Overall block diagram of the proposed 3D BISR architecture.

the test algorithm. The response from the memory and expecteddata are compared to detect faults by the comparator. Becausethere is one BIRA module, memory can be repaired by BIRAsequentially. The fault information from the first fault memoryis sent to the BIRA because one of the faulty memories can berepaired.The BIRA module consists of a multi-fault detector, a

counter, fault storing Content Addressable Memories (CAMs)as introduced in [20], repair registers, and a controller. Becausethe spare memory is tested to use a post-share redundancyscheme before testing the memory, the available spare infor-mation is obtained. When the test is finished, the RA algorithmbased on the exhaustive search for all combinations of sparerows and columns is executed according to the information inthe fault storing CAMs. If the memory under test is irreparable,the test-repair procedure is finished. If the memory under testis repairable, the repair solutions can be found, and the repairsolution is stored in the repair registers.

B. Test-Repair Flow of 3D MemoriesFig. 3 shows the test-repair flow of 3D memories. In the par-

allel test-repair phase (i.e., first test and repair), the first faultinformation from the first faulty memory is sent to BIST, andthe rest of the faulty memories store the number of faults inthe fault number registers. The is the th faulty memory die.After the repair procedure is done, the rest of the memories areclassified as faulty memory or fault free memory. For the faultymemories, the test order is sorted in descending order of thenumber of faults. If there are more faults, the probability thatthe memory is irreparable can be high. If one of the memorydice is irreparable, the 3Dmemory is faulty due to the one faultymemory die. Therefore, the memory is tested and repaired in de-scending order of the number of faults to reduce the test time.In the serial test-serial repair phase (i.e., second test and re-

pair), the faulty memory under test is re-tested and repaired ac-cording to the test order. Whenever a fault is detected from thetarget memory die, the fault information is sent to BIRA. Whenthe detected number of faults is equal to the number of faultsstored in the first test, the test is stopped to reduce test time whilethe test algorithm is being completed in the second serial test.The test time is greatly reduced because most of the faults aredetected by the first few read operations of a March test [21].

Fig. 3. Test-repair flow of 3D memories.

When the post-share redundancy scheme is adopted, thenumber of available redundancies is always equal to or largerthan the number of spares for post-bond test-repair. Also,because the proposed 3D BISR scheme uses only one 3D BISRmodule in the base die, the stacked memory dice have an areaoverhead competitiveness. Thus, it is possible that the yieldof 3D memories can be improved with an adequate 3D BISRscheme and post-share redundancy scheme.

IV. PROPOSED BIRA SCHEME

A. Fault CollectionFig. 4 is an example of a faulty memory that is 8 8 using

a 2D spare architecture with two spare rows and two sparecolumns.Fig. 5 shows the fault storing CAM structure of the proposed

BIRA for a 2D spare architecture. Because each memory hasdifferent numbers of spare rows and columns from other mem-ories, and are the maximum numbers of spare rows andcolumns from stacked memory dice.The fault storing CAMs are classified into two CAMs: parent

address CAMs, and child address CAMs. The enable flag isused to recognize the valid information. The row and columnaddresses store the row and column address fields. The row orcolumnmust flag whether its address is a must-repair faulty line.If the number of faults in a column (row) is greater than

, then the faulty column (row) line becomes the must-re-pair column (row). This situation is called must-repair analysisbecause this faulty column (row) line must be repaired with a


Fig. 4. Example of faulty memory using 2D spare architecture.

Fig. 5. Fault storing CAMs structure.

spare column (row) line to have a solution [22]. The maximumnumber of parent address CAMs is the same as the sum of thetotal spares. The maximum number of child CAMs is

The size of the CAMs to restore the child faults has alreadybeen introduced in [6]–[9], [23]. Because the child faults sharerow or column addresses with the parent faults, the parent CAMpointers and new addresses are stored in the child CAM in SFCCand [9]. On the other hand, the row and column addresses ofall child faults are stored in the proposed scheme. Because thenumber of bits of the parent CAM pointer is smaller than thenumber of bits of the address of the memory, the size of thefault storing CAM is larger than the SFCC [9]. However, theproposed fault storing CAM structure and the fault collectionare simple. Therefore, the fault storing CAM structure can beadequate for the proposed 3D BISR scheme.When the faults are detected by BIST, the faulty information

is sent to BIRA. The proposed BIRA compares the newly de-tected fault address and all stored fault addresses in the faultstoring CAMs. The addresses are stored in the parent addressCAMs and child address CAMs according to their character-istics. Parent faults, like the leading elements or spare pivotsintroduced in [6], [8], and [9] have different row and columnaddresses. If the row or column address is the same as that of

Fig. 6. Example of the fault collection of the proposed BIRA. (a) The faultdetection order. (b) Status of the parent address CAM after fault collection.(c) Status of the child address CAM after fault collection.

any of the other parent faults, then the fault is classified as achild fault.Fig. 6 shows an example of fault collection of the proposed

BIRA for the faulty memory as shown in Fig. 4. Fig. 6(a) repre-sents the fault detection order of the incoming fault addresses.The first fault (1, 2) is a parent fault because it does not share rowand column addresses. Because the second fault (1, 5) shares arow address with the fault (1, 2), it is stored in the child addressCAM. The third fault (2, 0), and the fourth fault (3, 3) are clas-sified into the parent faults, and they are stored in the parentaddress CAMs as shown in Fig. 6(b). The fifth fault (3, 6) isstored in the child address CAM because it shares row addresswith the parent fault (3, 3), as shown in Fig. 6(c). The sixth fault(5, 5) is a parent fault because it does not share row and columnaddresses. The last fault (6, 0) is classified into the child faultbecause the column address is the same as the column address ofthe parent fault (2, 0). After the fault collection, the parent faultsare stored in the parent address CAMs as shown in Fig. 6(b), andchild faults are stored in the child address CAMs as shown inFig. 6(c).

B. Redundancy AnalysisThe RA algorithms are based on a binary search tree, such

as IS, ISF, or SFCC. Because each branch of the binary searchtree can be a repair solution, and these RA algorithms comparea faulty address with every node in the branch, a considerableamount of time is required to find a repair solution. Reference[9] analyzes all nodes in a branch concurrently for combina-tions of 2D spares to reduce the time needed for finding a repairsolution. Because of the parallel analysis, the proposed RA al-gorithm is faster than other algorithms based on a binary searchtree, such as IS, ISF, and SFCC. The number of branches in abinary search tree for a memory is

For example, if there are two spare rows and two sparecolumns, the number of solution candidates is six, and eachbranch is a set of solution candidates. Each branch has a dif-ferent order for the row and column address combinations, suchas , , , , , and .After completing the fault collection, the proposed BIRA

starts RA based on the BRANCH algorithm proposed in [9],and the RA algorithm proposed in [23]. According to the order


Fig. 7. Example of the fault collection of the proposed BIRA with other faultdetection order. (a) The fault detection order. (b) Status of the parent addressCAM after fault collection. (c) Status of the child address CAM after faultcollection.

of the repair solution candidate, the row or column addressesof the parent faults are selected as a repair signature. Then, therepair signature is compared with only the child addresses tocheck whether it can be a repair solution because it is derivedfrom the parent faults. This procedure is repeated for all thesolution candidates.For the same faulty memory, there can be different fault col-

lection results depending on the fault detection order. For ex-ample, the fault collection result in Fig. 7 is different from thefault collection result in Fig. 6, even though both fault collectionresults are from the faulty memory in Fig. 4. For this reason,there are two cases after the fault collection. In the first case,the number of parent faults is equal to the number of availablespare memories. In the second case, the number of parent faultsis smaller than the number of available spare memories.For the first case, the number of solution candidates is the

number of combinations of the parent faults choosing the avail-able spare rows. It is clear that there are solutions in the solutioncandidates because all of the parent faults are covered by somesolution candidates, and all of the child faults are covered be-cause of their address dependency as well. If there is no solution,however, the memory is not repairable.After the repair solution candidates are generated, the faults in

the parent address CAMs and the child address CAMs are com-pared with the repair solution candidates. If the address chosenfor spare rows is matched to the row address of faults, the en-able flag of both CAMs becomes zero. Similarly, if the addresschosen for spare columns is matched to the column address ofthe faults, the enable flag of both CAMs becomes zero. Afterthe comparison process is done, the repair solution candidate isdecided if all enable flags in both CAMs are zero. Otherwise,the next repair solution candidate is picked, and the proposedBIRA repeats the comparison process until all the enable flagsof CAMs are zero.For the second case, it is possible that there is no solution

among the combinations of the parent faults that uses the avail-able spare rows even though the memory is repairable. In thiscase, the solution candidates are expanded to the child faultsin two steps. In the first step, enable flags in both CAMs arezero when the fault address is matched to the repair solutioncandidate. In the second step, the repair solution candidates areexpanded to the combinations of the remaining child faults be-cause there remain one or more spare memories. Then the pro-



posed BIRA repeats the comparison process until all the enableflags of CAMs are zero.

C. Examples of the Proposed BIRAFig. 8 shows a repair procedure that selects the repair solution

candidate . According to the order of the repair solutioncandidate , the row, column, row, and column addressesin parent CAMs are selected. Thus, (R1, C0, R3, and C5) isthe repair signature. The repair signature then is compared withthe child addresses to check whether it can be a repair solution.As shown in Fig. 8, because the repair signature (R1, C0, R3,and C5) can cover all child addresses, it is decided as a repairsolution.The case in which the number of parent faults is smaller than

the number of spare memories is shown in Fig. 7. Because thereare two spare rows and two spare columns, 6 repair solutioncandidates are generated. Fig. 9 shows a repair procedure thatselects the repair solution candidate . According to theorder of the repair solution candidate , the row, column,and row addresses in parent CAMs are selected. Thus, (R1, C0,and R3) is the repair signature. The repair signature then is com-pared with the child addresses to check whether it can be a re-pair solution. After child addresses are compared to the repairsignature (R1, C0, and R3), the third child fault (5, 5) remains.Because the fault can be repaired by the spare column, C5 isadded to the repair signature (R1, C0, and R3). Consequently,the repair signature is updated to (R1, C0, R3, and C5), and it ischosen as a repair solution.

V. EXPERIMENTAL RESULTSTo estimate the performance of the proposed 3D BISR, we

implemented the 3DBISR schemes. 3D BISR schemes were de-signed in RTL with Verilog HDL, and were synthesized using


Fig. 10. Polya-Eggenberger distributions for the cases with cluster faultsand evenly distributed faults .

Synopsys Design Vision with a Synopsys 90 nm generic library.A different number of faults are injected into each memory atrandom locations using a Polya-Eggenberger distribution be-cause it well models the real faults distribution [24]–[26]. Afterthe experiments using the implemented 3D BISR schemes andthe Polya-Eggernberger distribution are performed, the repairefficiency in terms of the repair rate and the yield of 3D memo-ries, test-repair time, and area overhead are analyzed.

A. Analysis of Repair EfficiencyThe repair efficiency of the proposed BIRA algorithm is esti-

mated in terms of the repair rate. For the 3D memory, the yieldis estimated, and defined as the ratio of the number of good 3Dmemories to the number of tested 3D memories.A different number of faults are injected into each memory

at random locations using the Polya-Eggenberger distribution[24]–[26]. The Polya-Eggenberger distribution is widely usedfor modeling integrated circuit yields [24]–[26]. Fig. 10 showsthe six distributions that represent the cases with cluster faults

, and evenly distributed faults . Theaverage numbers of faults are ten, eight, and four. The case inwhich is used to estimate the repair rates of the proposedBIRA regardless of the bonding procedure. The cases in which

for pre-bond, and for post-bond, are used becausethe number of faults for the pre-bond is larger than the numberof faults for the post-bond. The x-, and y-axes in Fig. 10 arethe numbers of faults, and the probability of a fault occurring,respectively.Table I summarizes the repair rates of an exhaustive search

algorithm by CRESTA, and the proposed BIRA algorithm forboth cases. First of all, the repair efficiency in terms of therepair rate of the proposed BIRA algorithm is verified by theexperiments regardless of the bonding procedure. The averagenumber of faults is ten to obtain various results because thesmall number of faults can be easily repaired by a small numberof spares. Because the case that one spare row and one sparecolumn are prepared is simple, it is omitted. As Table I shows,the repair rates of the exhaustive search (CRESTA) and theproposed BIRA algorithm increase as the number of sparesincreases. For both cases, the repair rates for the clustered faultscase are higher than the repair rates for the distributed faults.According to the distributions, the repairable memories for theclustered fault case are more than the repairable memories forthe evenly distributed faults case. The proposed RA algorithm

TABLE IREPAIR RATE FOR THE EXHAUSTIVE SEARCH

AND THE PROPOSED BIRA ALGORITHM

TABLE IIYIELDS FOR FOUR REDUNDANCY SCHEMES

Case1: and (pre-bond), and (post-bond)Case2: and (pre-bond), and(post-bond).

performs for all combinations of the spare rows and sparecolumns, as verified through the simulations.As Table II shows, the yields using four redundancy schemes

are presented after the pre-bond and post-bond repair. Assumethat the number of stacked memory dice is two. The number offaults for the pre-bond test-repair is larger than the number offaults for the post-bond test-repair. For this reason, the averagenumbers of faults are eight, and four for pre-bond, and post-bond, respectively.To check the performance of various redundancy schemes,

the proposed BIRA algorithm is used for all schemes. Becausethe number of spares (i.e., ) is small com-pared with the number of faults (i.e., ) in the post-bondrepair, the yields of fixed and inter-die redundancy schemesare low. In other words, although the memories in the pre-bondrepair are repairable, they cannot be repaired by spares for thepost-bond. However, the yields of the all-share and post-shareredundancy schemes are high because they can use the re-maining spares after pre-bond repair in the post-bond repair.


When is four and is four for the pre-bond, and istwo and is two for the post-bond, the yield of the inter-dieredundancy scheme is higher than the yield of the all-share re-dundancy scheme. Because the maximum number of spare rowsis six, and the maximum number of spare columns is six for theall-share redundancy scheme, the repairable memories increasein the pre-bond repair. However, because the available sparescan be small after pre-bond repair, there are more irreparablememories in the post-bond repair.For all cases, the yields of the proposed 3D BISR scheme are

the highest. Because the proposed BIRA algorithm can find therepair solutions which have the smallest number of spares, thepost-share redundancy scheme can use more spares in the post-bond repair. Thus, the proposed 3D BISR scheme can improvethe yield of 3D memories by guaranteeing an exhaustive searchand increasing flexibility of spares.

B. Analysis of Test-Repair Time

The test time is measured according to the test complexityof the applied test algorithm, and the size of the memory undertest. Three 3DBISR schemes are considered for comparison: the3D STSR method, the 3D PTPR method, and the proposed 3DBISR method. To compare the test-repair time under the samecircumstances, the same BIRA algorithm as the proposed RAalgorithm is used along with the March C- test algorithm [27].The March C- test has test cycles, where isthe number of memory cells. Each simulation is repeated 10,000times.The simulations are performed following the two distribu-

tions: the cluster faults ( , and ), and the evenlydistributed faults ( , and ). To investigate theimpact of the fault free memories, the various probabilities offault free memories from 0 to 50% are assumed. In addition, toinspect the impact of the test stop at the stop condition, the var-ious probabilities of detected faults by the second, third, fourth,and fifth read operations are assumed to be 40%, 30%, 20%, and10%, respectively.Table III summarizes the test-repair time of four 3D BISR

schemes. The memory sizes varied from 128 128 bits to 20482048 bits, and the number of stacked memory dice varied

from 2 to 7. Because the test time is greater than the repairtime, the test time dominates the test-repair time. For the 3DSTSR scheme, the test-repair time increases proportional to thenumber of memory dice. However, for the 3D PTPR scheme,the test-repair time slightly increases according to the number ofmemory dice because all the memory dice are tested in parallel,and the repair time is very small compared with the test time.For the proposed scheme, the results of the test-repair time varyaccording to the probabilities of the fault free memory dice andthe probabilities of detecting all faults. Therefore, there are twoproposed 3D BISR schemes: 3D BISR without BIST stop, and3D BISR with BIST stop. The first one completes the test al-though all faults are detected during testing. On the other hand,the second one stops BIST when all faults are detected.According to the table, the more fault free memories that

exist, the more test time is reduced because it is not necessaryto re-test the fault free memories in the proposed method. In ad-dition, when the number of faults reaches the stored number offaults, the test is stopped, and the repair procedure can be ex-ecuted to reduce test time. The time reduction ratio is defined

TABLE IIIRESULTS OF TEST-REPAIR TIME (CYCLES)

Proposed (1): Proposed 3D BISR without BIST stopProposed (2): Proposed 3D BISR with BIST stop

as the ratio of the reduced test-repair time of the proposed 3DBISR scheme to other 3D BISR schemes.Compared to the 3D STSR BISR scheme, the proposed 3D

BISRwithout BIST stop can reduce the test-repair time by about12.50% to 20.84%. If the proposed scheme with BIST stopis considered, the proposed 3D BISR with BIST stop requirestest-repair time by about 52.85% to 72.50% of the time of 3DSTSR BISR. The time reduction ratio depends on the probabil-ities of the fault free memories and the probability of detectingall faults. The worst case scenario of the proposed 3D BISR isthat there is no fault free memory, and the test algorithm is per-formed to the end for all faulty memory dice. This condition isthe same as the 3D STSR scheme. Thus, the test time can besignificantly reduced, and it is always smaller than or equal tothe test time of the 3D STSR scheme.Compared with the 3D PTPR scheme, the proposed 3D BISR

spends more test-repair time than the 3D PTPR method be-cause there is a difference between the numbers of memorytests of these two schemes. However, the time reduction ratiois revealed through comparing results of the proposed 3D BISRwithout BIST stop to the proposed 3D BISR with BIST stop.When there is no fault free memory, and the number of mem-ories is seven, the test-repair time of the proposed 3D BISRwithout BIST stop is 1.75 times to 5.50 times that of the 3DPTPR scheme. The test-repair time of the proposed 3D BISRwith BIST stop is 1.45 times to 3.70 times that of the PTPRscheme. In addition, the test-repair time reduction increases ifthe number of fault free memories increases. For these reasons,


TABLE IVIMPLEMENTATION RESULTS OF AREA AND TIMING

the proposed 3D BISR scheme can reduce the test-repair timecompared to other 3D BISR schemes.

C. Analysis of Area OverheadWe use a 3D memory configuration including four memory

dice: 8 K 16 bits, 8 K 32 bits, 16 K 16 bits, and 16 K 32bits. 8 K 16 bits and 8 K 32 bits memories have three sparerows and three spare columns for the pre-bond repair, and haveone spare row and one spare column for the post-bond repair.16 K 16 bits and 16 K 32 bits memories have four sparerows and four spare columns for the pre-bond repair, and haveone spare row and one spare column for the post-bond repair.Table IV shows results of area overhead and timing informa-

tion. The area overhead is expressed as the number of NANDgates. For all 3D BISR schemes, a Finite State Machine (FSM)based March C- test algorithm is used, and the same BIRA al-gorithm introduced in this paper is used. To prevent loss of in-formation on faulty bits, the 3D BISR circuits are implementedfor handling the largest size of memory (i.e., 16 K 32 bits) forall 3D BISR schemes.The proposed 3D BISR requires a BISR circuit that is 25.23%

larger than the 3D STSR BISR scheme based on the data shownin Table IV. Because the proposed 3D BISR scheme performsparallel tests, the area of the BIST module increases due to in-ternal wire and more complicated routing than that of the serialtest method. Although the proposed 3D BISR scheme consumesmore area overhead than the serial test and 3D STSR scheme,the test-repair time of the proposed 3D BISR scheme is fasterthan the 3D STSR scheme with regards to the verification pro-cedure. In the verification procedure, all memories are testedwhether the memory is faulty or not faulty, and is properly re-paired or not. For the 3D STSR scheme, because all the mem-ories are serially tested, the additional test time is the numberof memories multiplied by one memory test time. However, be-cause the test for the verification is executed in parallel withthe proposed 3D BISR scheme, the additional test time is theamount of time required to conduct one memory test.When the proposed 3D BISR scheme is compared to the 3D

PTPR scheme, the proposed 3D BISR requires a BISR circuitthat is 44.55% of the area of the 3D PTPR BISR scheme asshown in Table IV. To satisfy the PTPR requirements, the 3DPTPR scheme uses more storage elements, such as registers andCAMs, because the faulty information from many memoriescan be handled simultaneously. Because the storage elements

TABLE VSUMMARY OF THE PERFORMANCE COMPARISON WITH AREA OVERHEAD,

TEST-REPAIR TIME, AND YIELD

dominate the area of the BIRA module, the area overhead ofthe 3D PTPR scheme becomes large. Therefore, the proposed3D BISR has excellent overall performance, including optimalrepair rate, fast test-repair time compared with increasing areaoverhead, and low area cost compared to increasing test-repairtime, as shown in the experimental results.Table V summarizes the performance as a function of the

area overhead, test-repair time, and repair rate. Because the areaoverhead is affected by the number of BISR modules, the areaoverhead of the proposed BISR is between the 3D PTPR and3D STSR BISR levels. However, the proposed 3D BISR is im-plemented in the base die, and the burden for the area overheadis less than the 3D PTPR BISR schemes. In terms of the test-re-pair time, the proposed 3D BISR scheme can greatly reduce thetest time although it serially executes test-repair memories. Inthe first parallel test phase, faulty memories are classified, andthe numbers of faults are recorded. In the second serial test-re-pair phase, the fault free memories are not tested. Also, if thedetected faults are the same as the stored number of faults, theBIST operation is finished, and the BISR starts testing the nextfaulty memory. For these reasons, the proposed 3D BISR pro-vides reasonable area overhead and test-repair time comparedwith 3D PTPR and 3D STSR BISR.In terms of the repair rate, the proposed 3D BISR scheme can

achieve a high repair rate by performing an exhaustive search,and optimizing the utilization of the limited redundancies. Be-cause the proposed BIRA algorithm can use minimal spares,the chance of having remaining spares after pre-bond repair in-creases. Therefore, the proposed 3D BISR scheme is the mostpractical method because it can be implemented with acceptablearea overhead in the base die, and it has a fast test and repair timewith the highest repair rate.

VI. CONCLUSIONA 3D BISR technique with a post-share redundancy scheme

for 3D memory is proposed. The proposed 3D BISR techniqueconsists of two phases: a parallel test-repair phase, and a se-rial test-repair phase. After all the memory dice are concur-rently tested, and one faulty memory die is repaired, only thefaulty memory dice are serially tested and repaired. The pro-posed 3D BISR scheme greatly reduces the test-repair time byapproximately 50% compared with the 3D STSR BISR schemewhen the ratio of the fault free memories is 50%. In the verifica-tion procedure, whether or not the 3D memory is repaired, thetime reduction substantially increases. Because the proposed 3DBISR tests and repairs serially, the number of BIRA modules isone. Thus, the storage elements are reduced, and the proposed3D BISR scheme greatly reduces the area overhead, by 44.55%in comparison to the 3D PTPR scheme. When the number of


memory dice increases regardless of the size of the memory,the time reduction will be higher because of the lower numberof test-repair and verification procedures, and the area reductionwill be higher because of the lower number of BIRA modules.Therefore, the proposed 3D BISR scheme is a solution consid-ering trade-off between test-repair time and area overhead, im-proving the yield of 3D memories.

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Wooheon Kang received a B.S. degree in electrical and electronic engineeringfrom Yonsei University, Seoul, Korea, in 2009. He is currently working towardthe combined Ph.D. degree from the Department of Electrical and ElectronicEngineering, Yonsei University, Seoul, Korea.His current research interests include built-in self-repair, built-in self-testing,

built-in redundancy analysis, redundancy analysis algorithms, reliability, andvery large scale integration design.

Changwook Lee received a B.S. degree in information and telecommunicationengineering from Korea Aerospace University, Goyang-si, Korea, in 2005. Hereceived a M.S. degree in Electrical and Electronic Engineering from YonseiUniversity, Seoul, Korea, in 2014.He has been a product engineer with the DRAM test engineering group, SK

Hynix Semiconductor, Inc., Icheon-si, Gyeonggi-do, since 2005. His currentresearch interests include memory testing, BIST, BISR, design for testability,and product reliability.

Hyunyul Lim received a B.S. degree in electrical and electronic engineeringfrom Yonsei University, Seoul, Korea, in 2013. He is currently working towardthe combined Ph.D. degree from the Department of Electrical and ElectronicEngineering, Yonsei University, Seoul, Korea.His current research interests include built-in self-repair, built-in self-testing,

built-in redundancy analysis, low power testing, reliability, and very large scaleintegration design.

Sungho Kang received a B.S. degree from Seoul National University, Seoul,Korea, and M.S. and Ph.D. degrees in electrical and computer engineering fromthe University of Texas at Austin in 1992.He was a Research Scientist with the Schlumberger Laboratory for Computer

Science, Schlumberger Inc. and a Senior Staff Engineer with the SemiconductorSystems Design Technology, Motorola Inc. Since 1994, he has been a Professorwith the Department of Electrical and Electronic Engineering, Yonsei Univer-sity, Seoul, Korea. His main research interests include VLSI/SOC design andtesting, design for testability, and design for manufacturability.

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