xfel timing system status 11 - ucl hep group

XFELThe EuropeanX-Ray Laser Project X-Ray Free-Electron Laser

Kay Rehlich 12.11.2008

XFEL Timing System

Status 11.2008

Attila HidvégiPatrick GeßlerChristian BohmKay Rehlich

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Kay Rehlich12.11.2008

2


The Front-end: XFEL Example

ADC

ADCFront-endelectronics FPGA

FPGA

CPU

Sw

itch

Hub

, PC

Ie

Timing

BPM

FPGA

ADC

DAC

xTCACrate

Feedback

Central Timing1.3GHz

CPU

Ethernet

MPS

FPGA Giga Link

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Data Acquisition

xTCA

CPUEthernet

Tunnel

Middle layerserver

CPU

FPGA

ADC FPGA

RF/Diag

Timing

Hardware: receives clocks or patterns, triggers

to synchronize the bunches (ps stability)

clock trigger

PCIe

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Data Acquisition

xTCA

CPUEthernet

Tunnel

Middle layerserver

CPU

FPGA

ADC FPGA

RF/Diag

Timing

CPU: receives event numbers, interrupts, modes

to synchronize the macro pulses for DAQ

clock trigger

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Possible Bunch Patterns

Max: 5 Mhz, 3000 bunches

Pre bunch

1 Mhz or lower frequencies

Arbitrary patterns

Different patterns @ different beamlinesin one macro pulse

or varying patterns from shot to shot

}

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6


Timing System Blocks

1.3GHzMasterOscillator Timing

TransmitterTimingReceiver

Line lengthcompensation

Clock&DataRecovery

50Hz

Fiber linkswith clock & data

up to 3km1.3GHz telegrams

Clocks, patterns,triggers, telegrams

Event Number,Time, mode,

Interrupts

Clock & delaycontrol

Pattern & triggercontrol

Control System

MachineProtectionSystem

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Timing System Requirements

1.3GHz telegrams With clock recovery, few ps jitterEvents and data for triggers, event number, modes, bunch pattern, (bunch charge?), ...Sender compensates cable length, drifts and measures time delay from sender to receiver

Timing receiver outputs (hardware)Raw telegramsClock (and gated clocks) on front and backplanetriggersLevel (LVDS, LVPCL,..) to be definedConnectors to be defined (e.g. infiniband)

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Star Topology to Distribute TimingM

CH C

PUM

PSTi

min

g

Cou

pler

Inte

rlock

AD

CC

oupl

er In

terlo

ck

ADC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

MC

H

CPU

Preliminary!

Experiments

Tim

eGen

Machine ProtectionSystem: Op Mode ................................................

Tim

eGen

Tim

eGen

Tim

eGen

Tim

eGen

Tim

eGen

Tim

eGen

Tim

eGen

Tim

eGen

Tim

eGen

Tim

eGen

ED

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Geographical Layout of RF Stations

CPUNetwork

MC

H CPU

MPS

Tim

ing

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

AD

CC

oupl

er In

terlo

ck

ADC

Cou

pler

Inte

rlock

AD

C

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

MC

H CPU

MPS

Tim

ing

Cou

pler

Inte

rlock

AD

CC

oupl

er In

terlo

ck

ADC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

MC

H CPU

MPS

Tim

ing

BPM

Inte

rface

BPM

Inte

rface

CPUCPU

ADC ADC ADCADC ADC ADCADC ADC ADC

DAC Timing

ADCTiming

MCH ADCKly Interf

ATCA and µTCA Crates to Control one RF Section of the XFEL

XFEL: Super conducting Linac (22GeV)

Preliminary!

Experiments

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Possible Local Distribution

CPUNetwork

MC

H CPU

MPS

Tim

ing

Cou

pler

Inte

rlock

AD

CC

oupl

er In

terlo

ck

AD

CC

oupl

er In

terlo

ck

AD

CC

oupl

er In

terlo

ck

AD

C

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

MC

H CP

UM

PSTi

min

gC

oupl

er In

terlo

ck

AD

CC

oupl

er In

terlo

ck

AD

CC

oupl

er In

terlo

ck

AD

CC

oupl

er In

terlo

ck

AD

C

Cou

pler

Inte

rlock

AD

C

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

A

DC

Cou

pler

Inte

rlock

AD

CC

oupl

er In

terlo

ck

ADC

MC

H CPU

MPS

Tim

ing

BPM

Inte

rface

BPM

Inte

rface

CPUCPU

ADC ADC ADCADC ADC ADCADC ADC ADC

DAC Timing

ADCTiming

MCH ADCKly Interf

ATCA and µTCA Crates to Control one RF Section of the XFEL

Preliminary!

Fiber opticfrom centraltiming generator

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Possible AMC – Timing Receiver Module

PCIe interface

IPMI board management

clock + trigger,outputsplug TBD

SFP

SFPSFPSFPSFP

Optionalrear

transitionplug

Optional Double Module extension

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Preliminary: output block

SFP CDRVirtex 5

Fanout

1.3GHz clk

MP

X N/MPLL

&∆t

LVDS

LVPECL

/n

/ne.g. AD9514

Clk n Out

ICS854058

Bac

kpla

ne

AMCclk

Clock with 1ps shift

Clock burst, eg bunch pattern

Trigger with/wo synch to 1.3GHz

?

Clock with encoded data

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Preliminary: sender block

Virtex 5

SFPΔt

Δt

compare

1.3GHzfrom MO

data

PCIeTrigger

Stabilized psdelay

Evaluation board ready, tests started this weekShould demonstrate the achievable performance of the clock chips and FPGA

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Specs PRELIMINARY

Trigger:timing resolution: 1.54ns (0.769ns)

Programmable with 32 bits (up to 6s (3s))Clocks:

Jitter: < 5ps RMS (goal)Constant or burst (e.g. bunch clock)Automatic adaption of location/beam mode

Raw 1.3GHz telegrams with encoded dataData format is not yet fixed (number of filler words for the clock recovery to be defined)

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3 Test Boards connected to a Virtex 5

Contains:

fiber optic IOdelay chipsclock data recoveryphase comparatorsADCs and DACsFPGA interface

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Outlook

First prototypeDesign ready 2008Tests in January 2009

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xfel timing system status 11 - ucl hep group

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