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29 January 2007 H. Leich, DESY Zeuthen 1

Von AMANDA zu ICECube -die Weiterentwicklung des

Detektors

V. Drozdov, H. Leich, T. Schmidt, C. Spiering, K.H. Sulanke


Outline

• The Amanda Experiment

• Optical Module Concepts

• dAOM Architecture

• dAOM Control System at the Surface

• dAOM++

• DOM Architecture

• Possible Contributions to ICECube Hardware Design

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The AMANDA detector in the ice at the Southpole


Optical Module Concepts

During the lifetime of AMANDA 3 different types of OMs have been developed:

•• TheThe AAnalog nalog Opticalptical Module: AOModule: AOM

•• TheThe digitallyigitally controlledcontrolled Analog nalog OpticalpticalModule: odule: dAOMdAOM

•• TheThe Digital igital Opticalptical Module: DOModule: DOM

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AMANDA: Analog Optical Modules


Optical Modules with new Technology

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dAOM - Design Motivation:• Active, analog optical PMT pulse transmission via fiber driven

by a LED/laser diode

• Additional active, analog electrical PMT pulse transmission via

twisted pair cable in case of fiber damages (at PMT gains ≤

108)

• start with a conservative/’primitive’ dAOM deployed in

1999/2000 in small number to check whether inteligent designs

are working in the ice at all

• do a transition towards the ‘more advanced’ dAOM++ later

Design Goals:Design Goals:

•• ReliabilityReliability

•• CostCost EfficiencyEfficiency, , FlexibilityFlexibility

•• Easy to Easy to deploydeploy and to and to exploitexploit

•• Low power Low power consumptionconsumption


dAOM Architecture

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dAOM - Surface CommunicationThe implemented solution for communication uses the

following protocols:

–– PhysicalPhysical layerlayer::•• Manchester Manchester codedcoded digital digital signalsignal transfertransfer basedbased on a on a

carriercarrier of 320 kHzof 320 kHz

–– Data link Data link layerlayer::•• selfself defineddefined ASCII ASCII basedbased frameframe structurestructure protocolprotocol

–– Network Network layerlayer::•• half duplex half duplex datadata transfertransfer withwith a a clearclear defineddefined

mastermaster--slaveslave relationshiprelationship

TransformerDriver

LineReceiverMicro

Controller

TxD

RxD

ManchesterCoder/

Decoder

TelecomTransformer

TxDm

RxDm

AMANDAcable


Remote Power Supply & HV

DC/DCConverter

DC Power Source60 Vdc

PowerOn/off

Surface StationdAOM

2,5 km cable

Telecomtransformer

Telecomtransformer

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The dAOM Surface DAQ System


Deployed dAOM by numbers:

LED-dAOMs:11 LED-dAOMs built (six 8 inch PMTs, five 10 inch PMTs)11 LED-dAOMs tested at Pole for deployment10 LED-dAOMs deployed at String 17, 18, 1910 LED-dAOMs are fully operating (except for fiber damages)

LD-dAOMs:21 LD-dAOMs built21 LD-dAOMs tested at Pole for deployment13 LD-dAOMs deployed at String 17, 1910 LD-dAOMs were fully operating (except for fiber damages)

1 LD-dAOM: anode HV not working ← ???1 LD-dAOM: dynode/anode HV instable ← sparking ← bad PMT

soldering1 LD-dAOM: no signals, but full functionality ← connection between

base and dAOM board damaged

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The Optical Receiver Module (ORM):

--> Optical Receiver for LD OMs (but also working with LED)

• Problem: fast LD pulses do not pass the 2 μs delay line• General rule: FWHMinput pulse ≈ 10% delay time• Solution: pulse shaping (not trivial!!!)


Line DriverPIN diodeDelay Line 2μs

Shaping amplifier

FADC Driver

Adjustable Gain Amplifier

DAC

DAC

CHANNEL 1

CHANNEL 2,3,4

RS-232μC C515C

nvSRAM 32Kx8EEPROM 32Kx8

TransimpedanceAmplifier

Slowoutput

Fastoutput

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Received optical power with 10 dB fiber attenuation using theUW LED Piggy Pack and UCI LD Piggy Pack :


Requirements on IceCube technologiesdictated by science

The requirements can be summarized as follows:

time resolution of ≤ 5 nsec rms,waveform digitization with 200-320 Msps,dynamic range of ≥ 200 PE/15 nsec,dead time of ≤ 1%,gain variation of ≤ 2% per week.

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dAOM++ design motivations:

• Extend dynamic/PE range (> 200 PE/15ns)• Extend dAOM with features for automatic calibrationprocedures• calibration of non-linear components• interstring calibration• T0-calibration • Use full duplex standard communication protocol withthe possibility of connecting several dAOMs to onetwisted pair cable• Reduce part counts by higher integrated components• Explore new technologies like VCSELs


Transimpe-dance Amplifier

Transconduc-tance Amplifier Fibe

r

Vin VOUT

PIN-diodeLD/LED

ILD IPD

The Optical Transmitter Module (OTM):Fiber optic interface basics:

The max. needed optical power for the transmitter depends on theattenuation of the fiber link and dynamic range and the sensitivityof the receiver:

Fiber attenuation/loss:• Connector loss: 0.2 dB• Splice loss: 0.2 dB• Fiber loss: MM fiber: 3 dB/Km @ 850 nm or 1 dB/Km @

1300 nm• SM fiber: 0.4 dB/KM @ 1300 nm

Using a 3 Km fiber with one splice and 4 connectors @ 1300nm: 4 dB

Dynamic range: 1 : 1000 → 30 dBSensitivity: > 30 dBm

4 dBmopticaltrans-mittedpower

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Parameter LEDLytel259012-2

VCSELHFE 4080-321 XBA

VCSELHFE 4080-321

LD OECALQ5 – 1310– 3.0f withML725 B8F

LDFU-17SLD-F1

Opticaloutputpower [mW]

0.08 0.4 1.8 3.0 2.5

Operatingcurrent [mA]

< 150 < 20 < 20 < 35 < 28

Thresholdcurrent [mA]

< 6 < 6 < 15 <15

Differentialefficiency[mW/mA]

0.25 0.25 0.07

Centralwavelength[nm]

1290 850 850 1310 1300

Fiber MM MM MM MM SMRise and falltime [ns]

< 4 < 0.3 < 0.3 < 0.5


-The dual slope Optical TransmitterModule for LDs and VCSELs:

Double slopeamplifier

Bias and power control

PMT signal

Vcc

BiasCtrl/Mon

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The calibration circuit:

To correct for non-linearities of the active, analog optical/electrical pulse transmission weneed a calibration circuit producing ‘PMT-like’ fast pulses:

Calibrationpulser

Laser DiodeDriver

DAC

PMT

CONTROL

Calibration circuit produces negative ‘triangular’ pulses with 10 ns FWHM between 1 mV and 1500 mV!


The dAOM++ design overview:

HV Base

LEDFlasher

Laser diode

AnalogMUX

Line Rx

Dual Slope Amplifier & Laser Diode Driver

DC – DCConverter

CalibrationPulser

Line Tx

DAC

Bias Current Ctrl. and Mon., Gain Ctrl.

High Pass

Low Pass

HDLC ProtocolDecoder

HDLC ProtocolEncoder

NVRAM

TXCO

ADC

16 Bit ProcessorPeriph. Devices

Internal RAM

ALTERA APEX Device+5VGND-5V

ElectrCable

OpticalCable

425 ... 640 kBit/s

9600 ... 38400 Bit/s

PMT

Line Amp

Xformer

HV SettingsMonitoring

On / OffStatus

TDC

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Power supply, HV, FPGA, CPU and digital communication:

• Input power supply via the same TP cable used for data transmission• Galvanic separation with telecom technology transformer• VAC transformer can handle upto 160 mA DC current → upto 4 W for two dAOMs• Input voltage 60 VDC• Using telecom technology DC/DC converter• Ericsson DC/DC converter has high efficiency (83%), and high MTBF (4.9 Mh)• HV: ISEG base

• Digital communication is duplex transmitted using different carrier frequencies• Digital communication has been successfully tested via 2.7 Km TP cable at a rate of 625 Kbit/s• Communication protocol: High level Data Link Control (HDLC)• HDLC controller + coder/decoder implemented in FPGA using core from Innocor Ltd.

• FPGA: ALTERA APEX• CPU: 16-bit integer RISC processor embedded in FPGA as softcore (NIOS)


dAOM DAQ System with PCI Interface

fast DAC

PCIInterfaceControl

FADC2 x 250 MSPS8 Bit

Ring Buffer Memory

(10 ... 20 us)

P

C

I

Read-Out&

Trigger

to other‘on board’ Channels(local trigger)

Trigger/ ScalerBoard

Trigger Input

Gain

Fast output

PIN diodeO/E Converter

AnalogMUX

global test pulse input

+ -60 V

Digital Slow Control

LineEqual.

Line Rx

Line Tx

‘multiplexed’dAOM channel

Power Switch

&MonitorOMPowerSupply

El. Quad

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dAOM DAQ System with PCI Interface


Digital Optical Module(First Prototype, Deployed 2000)

TemperatureSensor

ATWDCPU

LookbacK

SRAM

FPGA

FASTADC CPU

SRAM

Application Flash

Boot Flash

PLDPMTBase

Power Supply

High Pass Filter

TwistedPair

(to Surface)Low Pass

Filter

Communication

s ADC

Communication

s DAC

Communications Disc.

SPE/MPEDisc.

8b

8b

10b

10b

Flashers

DAC

DAC

Bus: 32b data, 21b addr

ADC

DACAnode, First

Dynode

ToyocomOscillator(16.8 MHz)

PLL(frequencydoubling)

Digital Clock Signalsto Multiple Components

Delay Line

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DOM-HUB: A Preliminary ProposalK.-H. Sulanke, H. Leich, C. Spiering

3 ways of Implementation

• Standard Compact PCI Solution

plus:off the shelf standard CPU’s, good possibilty to tune the needed computing poweroptional less communication latency by using CPU‘s with Gigabit ethernetethernet boot capabilityhot swap capability allows to mount DOM-HUB’s under powerhigh data rate (120 MBytes/sec) between DOM-HUB and CPU memoryfast trigger decision in between up to 4 stringsbased on existing custom boards the development of a LINUX driver could start immediatly

minus:for the DOM-HUB a LINUX driver is needed


•Embedded PC

CPU AMD ELAN SC520 133 MHZDRAM 16, 32 or 64 MByte onboard (128 MByte announced)Ethernet 10/100BaseTCompactFlash socket, easy upgradeable IDE flash disk5V power only, max. 6W power consumptionPCI and ISA businterfaceIDE, USB, COMn, LPT

plus:off the shelf standard CPU’s, good possibilty to tune the needed computing powerethernet boot capabilityhigh data rate (120 MBytes/sec) between DOM-HUB and CPU memory

minus:only up to 128 MByte DRAM availableadditional cost per DOM-HUB of about 350 US$, (sample: CPU 667.-DM, 64 MB DRAM 84.-DM)

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•FPGA-only solution

plus:low latency, no operating system-overheadno special device driver neededethernet boot capabilityonly some knowledge of C is sufficient to change the DOM-HUB firmwarelow power consumption due to the missing of superfluous components

minus:less experience with the NIOS softcoreTCP/IP protocol has to be programmed


DOM - Hub, Blockdiagram, V.1

• 6 U CPCI board, 8 channels, 4 DOM’s per channel

FPGA

PCI Bus

Local Bus

Digital part #0

32

FPGA

EEPROM

Bus-Control

PCI coreDMA / IO

DQ0..31

Req0

R/W

Sel0

Add On Bus control

DQ0..31

Req0..7

R/WSel0..7

2

2

DOM - Cable

Time-Sync

FPGA

Digital part #7

DQ0..31Req7

R/WSel7

2

2

DOM - Cable

FIFO

Par/Ser

STM’s

FIFO

Par/Ser

STM’s

2 Analog part #0

RxD0..1

TxD0..1

Sync_In2

2 Analog part #7

RxD0..1

TxD0..1

Sync_In2

32

32

32AD0..31

Ctrl32

FPGA

PCI BusCPCI crate

Local PCI Bus

Digital part #0

32

FPGA, optional

EEPROM

Bus-Control

PCI coreDMA / IO

DQ0..31

Add On Bus control

DQ0..31

Ctrl

4

4

DOM - Cable

Time-Sync

FPGA

Digital part #3

DQ0..31

4

4

FIFO

Par/Ser

STM’s

FIFO

Par/Ser

STM’s

2 Analogue part #0

RxD0..3

TxD0..3

Sync_In2

32

32

AD0..31

Ctrl

Ctrl

Ctrl

ETX-PCI connector32

2

2

DOM - Cable

2 Analogue part #3

RxD0..3

TxD0..3

Sync_In2

2

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