INTRODUCTION

Complementary MOS offers an inverter with near-perfect characteristics

such as high, symmetrical noise margins, high input and low output impedance,

high gain in the transition region, high packing density, and low power dissipation.

Speed is the only restricting factor, especially when large capacitors must be

driven. In contrast, the ECL gate has a high current drive per unit area, high

switching speed, and low I/O noise. For similar fanouts and a comparable

technology, the propagation delay is about two to five times smaller than for the

CMOS gate. However, this is achieved at a price. The high power consumption

makes very large scale integration difficult. A 100k-gate ECL circuit, for instance,

consumes 60 W (for a signal swing of 0.4 V and a power supply of 4 V). The

typical ECL gate also has inferior dc characteristics compared to the CMOS gate—

lower input impedance and smaller noise margins.

In recent years, improved technology has made it possible to combine

complimentary MOS transistors and bipolar devices in a single process at a

reasonable cost. A crosssection of a typical BiCMOS process is shown in Figure 1.

A single n-epitaxial layer is used to implement both the PMOS transistors and

bipolar npn transistors. Its resistivity is chosen so that it can support both devices.

An n+-buried layer is deposited below the epitaxial layer to reduce the collector

1

resistance of the bipolar device, which simultaneously increases the immunity to

latchup. The p-buried layer improves the packing density, because the collector-

collector spacing of the bipolar devices can be reduced. It comes at the expense of

an increased collector-substrate capacitance. This technology opens a wealth of

new opportunities, because it is now possible to combine the high-density

integration of MOS logic with the current-driving capabilities of bipolar

transistors. A BiCMOS inverter, which achieves just that, is discussed in the

following section. We first discuss the gate in general and then provide a more

detailed discussion of the steady-state and transient characteristics, and the power

consumption. The section concludes with a discussion of the usage of BiCMOS

and the future outlook. Most of the techniques used in this section are similar to

those used for CMOS and ECL gates, so we will keep the analysis short and leave

the detailed derivations as an exercise.

Figure 1 Cross-section of BiCMOS process

2

BICMOS GATE AT A GLANCE

As was the case for the ECL and CMOS gates, there are numerous versions

of the BiCMOS inverter, each of them with slightly different characteristics.

Discussing one is sufficient to illustrate the basic concept and properties of the

gate. A template BiCMOS gate. When the input is high, the NMOS transistor M1 is

on, causing Q1 to conduct, while M2 and Q2 are off. The result is a low output

voltage. A low Vin, on the other hand, causes M2 and Q2 to turn on, while M1 and

Q1 are in the offstate, resulting in a high output level. In steady-state operation, Q1

and Q2 are never on simultaneously, keeping the power consumption low. An

attentive reader may notice the similarity between this structure and the TTL gate,

described in the addendum on bipolar design. Both use a bipolar push-pull output

stage. In the BiCMOS structure, the input stage and the phase-splitter are

implemented in MOS, which results in a better performance and higher input

impedance.

3

The impedances Z1 and Z2 are necessary to remove the base charge of the

bipolar transistors when they are being turned off. For instance, during a high-to-

low transition on the input, M1 turns off first. To turn off Q1, its base charge has to

be removed. This happens through Z1. Adding these resistors not only reduces the

transition times, but also has a positive effect on the power consumption. There

exists a short period during the transition when both Q1 and Q2 are on

simultaneously, thus creating a temporary current path between VDD and GND.

The resulting current spike can be large and has a detrimental effect on both the

power consumption and the supply noise. Therefore, turning off the devices as fast

as possible is of utmost importance.

The following properties of the voltage-transfer characteristic can be derived

by inspection. First of all, the logic swing of the circuit is smaller than the supply

voltage. Consider the high level. With Vin at 0 C, the PMOS transistor M2 is on,

setting the base of Q2 to VDD. Q2 acts as an emitter-follower, so that Vout rises to

VDD – VBE(on) maximally. The same is also true for VOL. For Vin high, M1 is on.

Q1 is on as long as Vout > VBE(on). Once Vout reaches VBE(on), Q1 turns off.

VOL thus equals VBE(on).1 This reduces the total voltage swing to VDD –

2VBE(on), which causes not only reduced noise margins, but also increases the

power dissipation. Consider for instance the circuit of Figure 0.2, where the

BiCMOS gate is shown with a single fan-out for Vin = 0. The output voltage of

4

VDD – VBE(on) fails to turn the PMOS transistor of the subsequent gate

completely off, since VBE(on) is approximately equal to the PMOS threshold. This

leads to a steady-state leakage current and power consumption. Various schemes

have been proposed to get around this problem, resulting in gates with logic swings

equal to the supply voltage at the expense of increased complexity. Some of these

schemes will be discussed later. Aside from this difference, the VTC of the

BiCMOS inverter is remarkably similar to that of CMOS.

5

STATIC BEHAVIOR AND ROBUSTNESS ISSUES

The use of resistive elements makes the BiCMOS gate of Figure 0.1

unattractive for real designs. A number of slightly modified, more popular circuits.

In the first circuit (a), the impedances Z1 and Z2 are replaced by active impedances

(or transistors) that are only turned on when needed. It still has the unfortunate

property that a diode voltage drop is lost at the high end of the output range and to

a lesser degree also at the low end. Circuit (b) has similar properties. The main

difference between the two topologies resides in the transient behavior. Circuit (c)

remedies the voltage-drop problem.

Deriving the other parameters of the VTC of the BiCMOS inverter manually

is truly complex due to the large number of devices and their interplay. We restrict

ourselves to SPICE simulations.

6

The voltage-transfer characteristic of the inverter of Figure 1b is simulated

using SPICE. A contrived BiCMOS process is employed that merges the MOS

devices and bipolar transistors described by the models of Chapter 2. The NMOS

and bipolar transistors are minimum size, while the PMOS transistors are made

twice as wide as the NMOS devices. The supply voltage VDD is set at 5 V. The

resulting VTC is shown in Figure 0.3. The complex shape of the curve is caused by

the complex interactions among the large number of active devices present in the

circuit.

To clarify the behavior, we have also plotted the dc transfer characteristics

for the base voltages of transistors Q1 and Q2. In the transient region between 2 V

7

and 3.5 V, none of the bipolar transistors are really on. Also, the PMOS device M1

only turns on after M3 turns off and when Vbase2 is sufficiently below Vout. This

causes Q1 to turn on and creates an additional drop in the output voltage around

Vin 3.5 V. Notice, furthermore, that VOH is higher than expected. This results

from the fact that Q2 still carries some emitter current when the baseemitter

voltage is smaller than VBE(on). The following dc parameters can be extracted:

VOH = 4.64 V; VOL = 0.05 V

VIL = 1.89 V; VIH = 3.6 V

VM = 2.34 V

NML = 1.84 V; NMH = 1.04 V

An example of a BiCMOS inverter that does not suffer from a reduced

voltage swing is shown in Figure 1c. The resistor R1 (in combination with M2)

provides a resistive path between VDD and Vout and slowly pulls the output to

VDD once Q2 is turned off. Full-rail BiCMOS circuits are the subject of active

research.

8

PERFORMANCE OF THE BICMOS

INVERTER

The BiCMOS inverter exhibits a substantial speed advantage over CMOS

gates when driving large capacitive loads. This results from the current-multiplying

effect of the bipolar output transistors. As in the ECL case, deriving accurate

expressions for the propagation delay is nontrivial. The gate consists of a large

number of active devices (up to six) and contains a number of internal nodes, each

of which could have a dominant effect on the transient response. Although detailed

studies have been presented in the literature (e.g., [Rosseel88]), we restrict

ourselves to a simplified analysis. This establishes a firstorder model for the delay.

SPICE simulations can then be used to establish a more quantitative result.

Consider first the low-to-high transition in the circuit of Figure 0.1a.

Assume that the input signal is switching very fast and that its rise/fall times can be

ignored. After turning off M1, the impedance Z1 allows the base charge of Q1 to

drain to ground. Since the transistor was operating in forward-active mode, the

stored charge is small, and Q1 turns off fast. To a first order, we can therefore

assume that this has no impact on the propagation delay and that Q1 is turned off

9

instantaneously. Under those conditions, the transient behavior can be modeled by

the equivalent circuit of Figure 1a.

The propagation delay consists of two components. First, the capacitor Cint

has to be charged to VBE(on) through M2 to turn on Q2. Once this point is

reached, Q2 acts as an emitter- follower, and CL gets charged. Approximative

expressions can be derived for both time intervals:

with Icharge1 the average charging current.

10

As Z2 is normally a large resistor, the latter component of the charging

current can be ignored. The PMOS device operates in saturation mode in this time

interval, providing ample current; therefore, tturn-on is small. To compute the

second component of the propagation delay, where Q2 acts as an emitter-follower,

we can use the reflection rule (similar to the analysis of the ECL gate) to merge the

internal and external circuit nodes into a single node. CL now appears in par- allel

with Cint, but its value is divided by (F + 1). This is equivalent to stating that the

base current of Q2 is multiplied by that factor. The corresponding delay is now

readily computed:

Icharge2 equals the average charging current during that interval. This consists

primarily of the current through M2 (ignoring the current loss through Z2). The

value of Vswing is determined by gate topology, but normally equals VDD – 2

VBE(on), as was apparent from the dc analysis. The value of Icharge2 is

comparable to the average PMOS charging current, as observed in a CMOS

11

inverter with similar-size devices. The overall value of the low-to-high propagation

delay is obtained by combining Eq. (0.2) and Eq. (0.3).

This delay consists of two components:

1. A fixed component that is proportional to Cint and is normally small. Cint is

a lumped capacitance, composed of contributions of the PMOS device

(diffusion capacitance) and the bipolar transistor (be- and bc-junction

capacitance and base-charge capacitance).

2. The second component is proportional to the load capacitance CL. The

loading effect is substantially reduced by the (F + 1) current multiplier

introduced by the bipolar transistor.

It is interesting to compare this result with the delay of a CMOS inverter,

assuming similar-size MOS transistors. The following linear approximation of the

delay of the CMOS inverter is valid.

12

In comparing Eqs. (0.4) and (0.5), we realize that the values of the

coefficients are approximately equal (a c and b d), as determined by the

current through the PMOS and the voltage swing, which are of the same order in

both designs. Cint is substantially larger in the BiCMOS case due to the

contributions of the bipolar device. These observations allow us to draw an

approximate plot of tpLH versus the load capacitance CL for both the CMOS and

BiCMOS gates ( Figure 0.4).

For very low values of CL, the CMOS gate is faster than its BiCMOS

counterpart due to the smaller value of Cint. For larger values of CL, the bipolar

output transistors easily provide the extra drive current, and the BiCMOS gate

13

becomes superior. Although the cross-over point Cx is technology-dependent, it

typically ranges from CL 50 to 250 fF.

As a result, BiCMOS inverters are normally used as buffers to drive large

capacitances. They are not very effective for the implementation of the internal

gates of a logic structure (such as an ALU), where the associated load capacitances

are small. One must also remember that the complexity of the BiCMOS gate incurs

an important area overhead. Consider carefully when and where to use BiCMOS

structures. A similar analysis holds for the high-to-low transition. It is assumed that

Q2 turns off instantaneously, as its base charge is quickly removed through Z2.

The resulting equivalent circuit is shown in Figure 1b. Once again, the delay

consists of two contributions:

1. Turning on Q1. This requires the charging of the internal capacitance Cint

through the NMOS device.

2. Discharging CL through the combined network of NMOS and bipolar

transistor. Ignoring the current loss through Z1, all the drain current of M1

sinks into the base.

Hence, the following approximative expression is valid

14

Eq. (0.6) closely resembles the one derived for the tpLH. It is worth

mentioning that Cint is not constant and changes between turn-on and discharge

modes. An average value over the complete operation range produces acceptable

first-order results.

15

PROPAGATION DELAY OF A BICMOS

INVERTERThe propagation delay of the BiCMOS buffer of Example 0.1 is simulated

using SPICE for a load of 1 pF. The result is plotted in Figure 2 and compared with

the performance of a CMOS inverter (for a similar load). The propagation delay of

0.86 nsec for the BiCMOS gate compares favorably to the 6.0 nsec of the CMOS

inverter. Notice the reduced voltage swing of the BiCMOS gate. The loss at both

the high and low levels is, however, substantially smaller than the 0.7V (VBE(on))

suggested by the first-order model and is approximately equal to 0.4 V. For very

low capacitive loads, the CMOS gate is approximately 5.5 times faster than its

BiCMOS counterpart. This is illustrated in Figure 0.5, where the propagation

delays of the CMOS and BiCMOS gates are plotted as a function of CL. The cross-

over point, where BiCMOS becomes faster than CMOS, is situated around 100 fF.

Notice that for CL values below 1 pF the propagation delay of the BiCMOS gate is

virtually independent of the load capacitance. For those load values, the

capacitance of the internal nodes (Cint) dominates the performance, and the factor

attributable to CL is negligible.

16

The measured slope of the CMOS curve is approximately 64 times steeper,

which is somewhat lower than the expected value of F + 1 (or 101). The

discrepancy is due to a number of inefficiencies in the BiCMOS gates, such as the

VBE losses.

Collector Resistance Rc—The equivalent circuits of Figure 1 ignore the presence

of the collector resistance rc between the extrinsic collector contact and the

intrinsic collector-base junction. The voltage drop over rc causes the transistor to

saturate even though the extrinsic VCE is larger than 0.7 V, as is guaranteed by the

BICMOS buffer design. For instance, a collector resistance of 100 ohms

conducting a transient current of 1mA causes a voltage drop of 0.1 V. When

driving large capacitive loads, currents in excess of 5 mA are regularly observed.

17

The transistor accordingly saturates, causing a deterioration of the propagation

delay; tp is then composed of the time to get the transistor into saturation, followed

by a discharging of the load capacitance with a time constant rCCL (Eq. (0.7)).

This problem can be avoided by increasing the size of the transistor, decreasing rC.

High-Level Injection—This effect occurs when the density of electrons

transported across the collector-base space is comparable to the doping of the

collector. The resulting base push-out effectively increases the width of the base

and degrades the switching performance of the transistor. A typical parameter to

quantify the onset of high-level injection is the knee current Ik, which is (in

practice) the value of the collector current at which the forward current gain F is

reduced to 50% of its value.

Similar to the degradation caused by the collector resistance, high-level

injection effects can be avoided by increasing the emitter area of the transistor.

18

POWER CONSUMPTION

The BiCMOS gate performs in the same manner as the CMOS inverter in

terms of power consumption. Both gates display almost no static power

consumption, while the dynamic dissipation is dominated by the (dis)charging of

the capacitors. When driving small loads, the latter factor is slightly larger for the

BiCMOS gate, due to the increased complexity of the gate. On the other hand,

when driving very large capacitors, BiCMOS becomes favorable.

To achieve comparable performance, CMOS drivers consist of a cascade of

gradually increasing inverters (discussed in Chapter 8). The power dissipated in

charging the internal capacitances becomes an important fraction of the overall

consumption. This cascading is, generally, not needed in BiCMOS.

The short-circuit currents during switching might be smaller or larger for

BiCMOS, depending upon the level of circuit optimization. The superior current-

driving capabilities of the bipolar transistors produce steeper signal slopes and,

consequently, a faster transition through the transition region. This potential

advantage is, however, easily annihilated by intrinsic RC delays in the gate. A

small differential delay might cause the bipolar transistors to be on simultaneously

19

for a longer time, causing a large direct current to flow (remember the high

transconductance of the bipolar transistors). All in all, only precise simulations that

include parasitic capacitances and resistances can tell exactly which gate is more

power efficient.

20

CONCLUSION

Presented an overview of a SiGe modular BiCMOS process technology.

Through the use of add-on modules compatible with the core CMOS process

technology, large-scale chips combining digital, analog, and RF technologies can

be produced. Modules are added as required by the chip under development. By

using the core process with added modules, the economies of scale associated with

large-volume CMOS production are maintained without compromising the

performance of the analog or RF circuits. By enabling higher-speed devices and

increased device density levels, these exciting advances in process technology will

decrease the number of ICs and discrete (passive) components required by

complex optical, wired and wireless communication systems. As process

technology advances, we will see SOC systems with millions of digital gates

combined with RF circuits operating in the tens of GHz. This will be made

possible through enhanced photolithographic scaling and, potentially, SOI

technology that could result in faster devices and better isolation between circuit

blocks. The ability to easily connect to the bodies of the MOS device remains a

problem for SOI technology when the MOS devices are used in analog or RF

circuits.

21

BIBLIOGRAPHY

Kiat-seng Yeo ,.et.al “CMOS/BiCMOS ULSI” Pearson Education Asia

http// www.ieee.org

22