Voltage Transfer Characteristic

CONCORDIAVLSI DESIGN LAB

The simulated Inverter

Inverter layout

TPLH TPHL Tr Tf NML NMH Average power Area(um2)

103.4ps 80.63ps 166.3ps 96.6ps 0.82v 1.76v 1.14e-06w 47.7*32.4

Inverter Characterization

TPLH TPHL Tr Tf NML NMH Average power

Area(um2)

103.4ps 80.63ps 166.3ps 96.6ps 0.82v 1.76v 1.14e-06w 47.7*32.4

.

VTC of Seven Inverters, WP = WN to WP = 7 WN.

The threshold voltage for each of the seven inverters ideal threshold voltage Vth = VDD/2 = 1.65 V

WP/WN Ratio Inverter's Vth Percentage Error

1 1.22 26%

2 1.34 19%

3 1.43 13%

4 1.5 9%

5 1.55 6%

6 1.6 3%

7 1.64 1%

Determination of the optimum VTC

Optimum VTC Wp=7Wn=Vdd/2 VTC with Vth, VIL, and VIH for Inverter for (WP/WN) = 7

Input Waveform

Output Response

Inverter’s Transient response

The pMOS

The nMOS

The Inverter

Laying out an inverter

Static

Vth = 1.64 V

VIL = 1.4 V

VIH = 1.91 V

NMH = VOH - VIH = 1.39 V

NML = VIL - VOL = 1.4 V

Transient

TPHL = 0.09 ns

TPLH = 0.1 NS

TP = (TPHL+TPLH)/2 = 0.095 ns

Tfall = 0.1 ns

Trise = 0.2 ns

Power Pavg= 21.85 pw

Inverter Characterization

DDOH VV (min)

0(max) OLV

(max)ILL VNM

(min)IHDDH VVNM

Noise Margins

n n nOX n N

n n n nr R

p p ppOX p P

p p p

W W WC K

L L LK

W W WC K

L L L

1

nN

n n nr R

pp pP

p

WK

L WK

W WKL

Design Parameter-r

Parasitic Capacitances in an inverter

Step Input Response