ucsb silicon workshop: svx3d

UCSB Silicon Workshop: SVX3DAnkush Mitra

Academia Sinica

SVX3D Introduction Initialisation Front-End / Acquisition Digitisation Readout Using the chip Summary

11 May 06 UCSB Silicon Workshop: SVX3D 2

Warning!!!!!!

This talk is based on the chip manual, other (sparse!) chip documents and my intuition

6 Years old with no update


SVX3D Introduction


Where is the SVX3D?

SVX3D reads out the charge from the Silicon sensor

Each chip (+hybrid) is attached to the Silicon sensors

There are ~5,000 chips in SVX-II


SVX3D

128 Analog Integrators

47 Deep Analog Pipeline X 128

Digitisation & Sparsification

53 MBytes/s Data Out

Analog (Front End) Digital (Back end)

128 Silicon Strips

“2 Chips” in one Analog Front EndDigital Back End

Many programmable features Can read out N and P type Silicon stripsMultiple chips can be daisy-chained

7.56MHz (132ns period) FECLK

53MHz (19ns period) BECLK


SVX3D Daisy Chain

TNBR/BNBR allow inter-chip communicationHas multiple roles

Data Lines and Control lines share a common busData Lines have multiple roles

Bus 0 – Bus 7 + OBDV

Chip Control Lines


Chip ModesInitialisation : Front-End & Back-End

Setup SVX3D SET DEFAULTS in SVXDAQCONFIG in Run Control

Acquisition : Front-EndCollect charge from the sensor

and store it on the pipelineDigitisation : Back-End

Digitise the channelsReadout : Back-End

Send data out of chip

Acquisition AcquisitionAcquisition Acquisition

Digitisation DigitisationReadout Readout

time

Initialisation

Initialisation

Front EndBack End

SVX3D can collect charge and digitise simultaneously


Initialisation


Initialisation: Single Chip

SVX3D has many programmable featuresNeed to initialise chip before it can be used for data takingSent as a 197 bit serial bit streamData is sent in through TNBR and clocked on FECLKUse CALSR to latch in shadow register

197 Bit Serial Shift RegisterTNBR BNBR

FECLK Shadow Register

Test Inputs

128 CALSR

Adjustable Chip Parameter

69


Initialisation: Daisy Chain

In daisy chain, TNBR/BNBR link shift registers of all chips together

For a daisy chain of chip, send Nchip x 197 bits

So first bit sent ends up in last chip in chain (chip 0)

Chip 3 Chip 2 Chip 1 Chip 0


Initialisation: What can be set

Read Neighbours (163)Read All (164)ADC Ramp Dir (165)ADC Comp Dir(166)Ramp Slope Trim (167-174)Threshold (175-182)Counter Modulo (183-190)RDriver (191-193)ADC Ramp Pedestal (194-197)

Channel Mask (1-128)CAL Direction (129)FE Polarity (130)Bandwidth (131-133)Pipeline Depth (134-139)ISEL (140-150)Readout Order(151)Chip ID (152-158)DPS (159)Bias Ratio (160)Driver Bias (161)Last chip (162)


Front End / Acquisition


Front EndAll 128 channels acquire charge simultaneously

Each channel implements same circuitCollected charge is transferred onto analog pipeline

Integrator

Analog Pipeline

X128 for 1 chip


Front End: Integrator

Charge from sensor

Test Charge: Polarity set by CALDIR

Integrator reset:Controlled by PARSTOnly applied in abort gap

During bunch crossings, charge on integrator capacitor is allowed to build up

cf

Charge on cf

time

Bunch traincollision

Bandwidth set by initialisation bits


Acquisition: Pipeline

c1

c2

c47

Read Amp

Write Amp

Pipeline logic controls pipeline switches

This capacitor store the charge on cf from previous bunch crossing

Only difference of charge on cf and cc is transferred to pipeline cell cn

cc

47 Cells in pipeline• 42 cells for L1A latency• 4 L1A buffers• 1 Reference capacitor(only filled in abort gap)

Initialisation bits set Pipeline operating currents, polarity and pipeline depth


Acquisition: Pipeline logicAll pipeline capacitor cells are filled in a round-robin fashion Advanced by FECLK

If a L1A is received pipeline cell n-(L1 latency) is reserved This cell is skipped over and only returned to pipeline after it is digitised (done by PRD2 signal)Only 4 cells can be tagged (4 L1 buffers)

During abort gap, pipeline cell 47 is set

Pipeline circular buffer

Writ

e po

inte

r

Tagged Cell


Back End / Digitisation


Digitisation: Subtraction of Pedestal

Write Amp

Read Amp

c1

c2

c47 PRD1 used to transfer charge from pipeline

If READOUT ORDER=0First PRD1 puts cell 47 on cs (pedestal)Second PRD1 reads out cn (signal+pedestal)pedestal – (signal+pestal) transferred

For READOUT ORDER=1, the order is reversed

cs

To ADC


Digitisation: Wilkinson ADCConversion of analog charge to digitised value is performed by Wilkinson-type ADC

VIN1

VIN3

VIN2

RAMP-RST starts a common voltage ramp

CNTR-RST starts a common 8 bit counter

Incremented by both edges of BECLK

When voltage-ramp=VIN,m comparator fires

Latch locks current counter value


Digitisation: ADC SettingFrom the initialisation, many of the ADC parameters can be

adjusted

Direction of ramp set by ADC RAMP DIRECTIONRamp Reference is set by Ramp Pedestal + ADC RAMP PEDESTAL

(can be +ve or –ve)Slope of ramp can trimmed by ADC SLOPE TRIMComparator can trigger off rising or falling edges: Set by ADC COMPARATOR DIRECTIONMaximum value of counter is set by COUNTER MODULOBias current of comparator and voltage ramp op-amp can be adjusted by BIAS RATIO

Ramp Pedestal

Ramp Reference

t

V Start counter

0 signal level

signal level

Digitised value

Latch counter

Position of start counter determines where 0 ADC counts sits


Digitisation: Dynamic Pedestal Subtraction

Method to calculate common mode pedestal in real time by delaying start of counter. DPS works if:

Low hit occupancyUniform pick up across all 128 channels

Once N comparators have fired, counter startsChannels near pedestal will fire firstVThreshold set externally via resistor

External resistor set to 7k35 Channels need to fire

CDF Note 4852

All channels are capacitively coupled


Digitisation: Threshold & Sparsification

If in NN or Sparse mode, channels with ADC value > Threshold are read out

If Threshold > COUNTER MODULO: No channels read out

In NN mode adjacent channels are read outIf channel 0 or 127 are hit, neighbour information is passed via TNBR & BNBR respectively

Before Readout, each hit channel is stacked into asynchronous FIFO for fast readout

~600ns needed for FIFO to collapse


Front End / Readout


Readout: Data Format

Data is transmitted in 1 Byte chunks.

Always accompanied with Odd-Byte-Data-Valid (OBDV) Signal

Chip ID

Cap-ID (Only lower 6 bits used)

Channel (Binary)

Data (Gray)

Channel (Binary)

Data (Gray)


Readout: Multiple ChipsPriority of chip readout is passed down via TNBR/BNBR lines

In this example, Chip 3 is read out first and then the others

First channel, first chip and last chip, last channel are always read out

Q: How does the chip do this ? Not mentioned in chip manual

Readout token passed along chip chain

Chip 3 readout first

Chip 0 readout last


Experience with SVX3D


Chip FeaturesDuring detector commissioning, a number of features were

found

Keep AliveEvery 270s, PRD2 and BE Clock has to be sent, if no other command has been sentNo keep alive: chip goes into high current state and trips off

Mini DigitiseAt end of readout, send extra BE Clocks (& maybe other signals?)Why? Works better if you do it (Tom Zimmerman – SVX3D father)

Abort Digitise disabledWas implemented to stop digitisation early. Found to make chip go into a high current state. Now SRC & FIB protect against this

Need to reinitialise from time to time1 chip consumes 80-100mA on AVDDSometimes AVDD drops 1 chip of current spontaneously during data takingNeed to reinitialise chip chain (HRR)


Chip Problems: AVDD2 Failure

CAP-ID is sometime indicator an impending AVDD2 failure

Behaviour can be reproduced by removing AVDD2 bond

Chips draws power parasitically from DVDD

“Finger” connects hybrid and chip via silver epoxy joint

Some AVDD2 Failures do recover

Observed Symptoms1. Loss of communication to chip front-

end2. Increase in DVDD current3. Chip chain broken after affected chip4. Failure observed after beam incidents

(or when ladder temperature changes)

bonds

epoxy

finger


SVX3D SummaryAll Silicon ladders readout by SVX3D chip

Integrated Analog Front-End and Digital Back-End

Dead-timeless: Can collect charge and digitise simultaneously

Honeywell Rad-Hard CMOS 0.8m Process4 MRads with Co60 Source15 MRads with 55MeV Proton Source

Fast: Capable of running at 132ns clock rates

Dynamic Pedestal SubtractionSubtracts common mode noise

SparsificationRemoves channels below programmable thresholdReduces data-rate and readout time

128 Analog Integrators

47 Deep Analog Pipeline

Digitisation & Sparsification

53MBytes/s Data Out

Ana

log

(Fro

nt E

nd)

Dig

ital (

Bac

k en

d)128 Silicon Strips


Backup


SVX3D Floor plan

128 Inputs

Analog Power

Calibration Voltage

Digital Power

8 Bit Data Bus + OBDV

Chip control lines

Bottom Neighbour

Top Neighbour

A number of lines have multiple roles


Acquisition: Pipeline Timing

FECLK clock used to advance pipeline

FECLKcoincides with beam-crossing Difference of cf and cc is transferred to pipeline cell cn

FECLKAdvance pipeline

Pipeline cell cn+1 is reset

cc stores charge from previous bunch crossing


Initialisation: SVXDAQ

Chip ID (152-158)Threshold (175-182)Pipe Depth (134-139)Ramp Trim (167-174)Bandwidth (131-133)Counter Mod (183-190)Ramp Pedestal (194-197)



Pipe Sel (130)Cal Dir (129)Readout Order (151)Comp Dir (166)Ramp Dir (165)Last Chip (162)Readout Mode (163,164)

Predefined settings for polarity



Calibration Masks for each channel

Set bit to 1 for channel to be readout for calibration



ISEL Bits (140-150)

Program currents for FE Op-Amps



Driver Com Mode (161)Bias Ratio (160)Dynamic Threshold (159)Resistor Driver (191-193)


ReadoutData is output via tri-stated 8 bit parallel bus

Can operate in Current driver or Resistor driver mode

The resistors in the driver are switch on/off via the RDriver values

MSB: Adds 6.3mAMid Bit: Adds 3.3mALSB: Adds 1.7mA

Driver Com Mode adjusts VRef


SVX3D Radiation Hardness test

Rad test withCo60 source up to 4MRad55MeV proton beam to 15MRad

Chip noise increases (30+3.2*Cap) electrons per Mrad

Bare chip noise vs rad Cap dep. noise vs rad


Chip Problems: Wirebond Resonance

Observed loss of data & power to Z sides of ladders

Found to correlate with high trigger rates

Failure due to wirebond resonances

Wires orthogonal to magnetic fieldWires feels Lorentz force during readoutIf frequency is right, wires resonate and break

I

Wire Motion

BMore details in resonance talk!!


Chip Noise @ 8fb-1

Layer0 of SVX has chips with smallest radius from IPWith init chip noise 1,600e and 18.3 pF load, the estimation is 5.5% noise increase per MRadExpect 17% of noise increase with 8fb-1

The S/N degradation will have large contribution by sensor shot noise.

Layer Chip R (cm)

Expected dose

Noise increase

L00-1 3 2.4 Mrad 13.5%

L0(SVX) 2.5 3.1 Mrad 17%

L1(SVX) 4.1 1.4 Mrad 8%

Expectation at 8fb-1


How many chipsSVX

L0: 2 R & 2 Rz 4 TotalL1: 3 R & 3 Rz 6 TotalL2: 5 R & 5 Rz 10 TotalL3: 6 R& 4 Rz 10 TotalL4: 7 R & 7 Rz 14 Total

ISLEach Ladder has 4(R) + 4(Rz) 8 chipsEach DAQ Layer is 2 ladders 16 chips

L00Narrow: 1 chipWide: 2 chips

ucsb silicon workshop: svx3d

Documents

chipucsb silicon workshop

silicon sensorsthere

svxiiucsb silicon workshop

chain chip

chip documents

chip manual

daisy chain of chip

end128 silicon strips2