theoretical study of the steinmetz circuit design

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Theoretical Study of the SteinmetzCircuit DesignLl. Monjo a , L. Sainz a , S. Riera a & J. Bergas aa Electrical Engineering Department, Universitat Politècnica deCatalunya, Barcelona, Spain

To cite this article: Ll. Monjo , L. Sainz , S. Riera & J. Bergas (2013): Theoretical Study of theSteinmetz Circuit Design, Electric Power Components and Systems, 41:3, 304-323

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Electric Power Components and Systems, 41:304–323, 2013

Copyright © Taylor & Francis Group, LLC

ISSN: 1532-5008 print/1532-5016 online

DOI: 10.1080/15325008.2012.742944

Theoretical Study of the Steinmetz Circuit Design

Ll. MONJO,1 L. SAINZ,1 S. RIERA,1 and J. BERGAS 1

1Electrical Engineering Department, Universitat Politècnica de Catalunya,

Barcelona, Spain

Abstract In several three-phase installations, such as electrothermal and tractionsystems, single-phase loads are sometimes delta connected with reactances to reduce

voltage unbalances. This delta-connected set is called the Steinmetz circuit. This workstudies the design of this circuit to balance line currents consumed by single-phase

loads. In contrast to the simplified conditions considered in the conventional Steinmetzcircuit design, the supply voltage unbalance and the resistance of the Steinmetz induc-

tor are used to obtain more general analytical expressions. The differences betweenthese expressions and those obtained from the simplified conditions are analyzed, and

a numerical example based on PSpice simulations is provided to compare results.

Keywords electric traction systems, power quality, energy infrastructure, unbalancedline currents, Steinmetz circuit

1. Introduction

Balanced three-phase conditions are expected and desirable in electrical power systems.

Nevertheless, several high-power single-phase loads (such as electrothermal installations

[e.g., induction melting surfaces, welding transformers, etc.] [1–4]; traction systems

[5–11]; heating, ventilation and air-conditioning systems; and electric vehicle-charging

installations) are closely connected to the utility power supply system. These loads

consume unbalanced line currents and cause unequal voltage drops in distribution lines

and, therefore, unbalanced load bus voltages. This results in several phenomena, including

transformer saturation, increased vibrations and losses in electric machines, under- and

overvoltages at appliance terminals, interferences, etc. [1–3]. To limit these effects,

standards dictate the compatibility level for voltage unbalance [12, 13].

Several methods have been developed to reduce unbalance in the above systems

and avoid voltage asymmetries [6, 7]. For example, single-phase traction loads (see

the railroad substation in Figure 1(a)) are connected in high-power short-circuit supply

systems and fed at different phases alternatively, special transformer connections are used

(e.g., Scott connection), or external balancing equipment is connected with the load.

External balancing equipment, which is sometimes used in traction systems, consists

of suitably connecting reactances (usually an inductor and a capacitor in delta con-

figuration), with the single-phase load representing the railroad substation. This delta-

connected set, more commonly known as the Steinmetz circuit, allows the network to be

loaded with balanced currents [1–4, 9–11, 14]. The Steinmetz circuit design aims to

Received 25 June 2012; accepted 19 October 2012.Address correspondence to Prof. Lluis Monjo, Electrical Engineering Department, Universitat

Politècnica de Catalunya Av. Diagonal 647, Barcelona, 08028, Spain. E-mail: [email protected]

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Theoretical Study of the Steinmetz Circuit Design 305

Nomenclature

eb;a error of Steinmetz circuit reactance expressions (%)

h D hr C jhi parameter that characterizes three-phase supply voltage

unbalance

I 0, I 1, I 2 symmetrical components of line currents (A)

I F line currents (A)

k harmonic order

mi magnitude of line current unbalance factor

mi D mi∠�i complex unbalance factor of line currents

mu magnitude of supply voltage unbalance factor

mu D mu∠�u complex unbalance factor of supply voltages

R1 resistance of Steinmetz circuit inductor (�)

RL resistance of single-phase load (�)

V 0, V 1, V 2 symmetrical components of three-phase supply voltages (V)

VF magnitude of three-phase supply voltages (V)

V F D VF ∠�F three-phase supply voltages (V)

X1 reactance of Steinmetz circuit inductor (�)

X2 reactance of Steinmetz circuit capacitor (�)

X1;A1, X2;A1 approximation 1 of Steinmetz circuit reactances (�)



XL reactance of single-phase load (�)

Y 1 admittance of Steinmetz circuit inductor (S)

Y 2 admittance of Steinmetz circuit capacitor (S)

Y L admittance of single-phase load (S)

Z1 impedance of Steinmetz circuit inductor (�)

Z2 impedance of Steinmetz circuit capacitor (�)

ZL impedance of single-phase load (�)

Greek Letters

�L power factor of single-phase load

�LC single-phase power factor limit

�i phase angle of line current unbalance factor (deg)

�u phase angle of supply voltage unbalance factor (deg)

�1 R1=X1 ratio of Steinmetz circuit inductor

�L XL=RL ratio of single-phase load

�F phase angle of three-phase supply voltages (deg)

Subscripts

a reference to three Steinmetz circuit reactances approximations

(a D A1, A2, or A3)

b reference to Steinmetz circuit reactances: inductor (b D 1) or

capacitor (b D 2)

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306 Ll. Monjo et al.

determine the reactance values (capacitor and inductor values) to balance the currents

consumed by the single-phase load. Balanced and sinusoidal supply voltages and a

pure Steinmetz inductor (in other words, the resistance associated with the inductor

is neglected) are usually considered to find analytical expressions for the reactances that

balance single-phase load currents [1, 9–11]. However, these approximations can lead to

considerable errors. In [2], the influence of unbalanced and distorted supply voltages on

the Steinmetz circuit design was analyzed from measurements and software simulations.

In [3], the resistance of the Steinmetz inductor and the presence of harmonics on the

Steinmetz were considered, and the symmetrizing reactance values were obtained by

optimization methods. In [4], reactances were determined with the usual expressions from

the fundamental waveform component of the supply voltage. Moreover, the performance

of the Steinmetz circuit under waveform distortion is analyzed by proposing several

indicators in the framework of the symmetrical components. It must be noted that, despite

considering imbalances, distortions, and the resistive Steinmetz inductor, the previous

works do not provide any analytical expressions for the Steinmetz circuit design (i.e.,

for the determination of the Steinmetz reactances). On the other hand, in [14], analytical

expressions for the design of the Steinmetz circuit reactances were obtained considering

unbalanced supply voltages.

This article expands the Steinmetz circuit design study in [14] considering the

resistance of the Steinmetz inductor and the unbalanced supply voltages to obtain novel,

more general analytical expressions for the symmetrizing reactances. Moreover, a detailed

comparative study between these new expressions, those in [14], and the traditional

balanced supply voltage expressions is presented. This contribution allows determi-

nation of the error introduced by the approximations. A numerical example of the

Steinmetz circuit design is studied with MATLAB software (The MathWorks, Natick,

Massachusetts, USA) and PSpice simulations (Microsim Corporation, Irvine, California,

USA), and two practical cases are analyzed to compare the results provided by the

reactance expressions.

2. Steinmetz Circuit Design

The line currents consumed by a single-phase load connected to a three-phase system

can be balanced with two reactances (usually an inductor and a capacitor) in delta

configuration with the load (Figure 1(b)). This delta-connected set is commonly known

as the Steinmetz circuit.

Figure 2 shows this circuit in detail, where the single-phase load (i.e., ZL DY �1

L D RL C jXL) is connected to an inductor with its associated resistance (i.e.,

Z1 D Y �11 D R1 CjX1) and to a capacitor (i.e., Z2 D Y �1

2 D �jX2). In this study,

the three-phase supply voltages can be considered unbalanced (i.e., V F D VF ∠�F with

F D A, B , C ). The procedure for designing the Steinmetz circuit is to determine the

values of the reactances X1 and X2 from the single-phase load impedance by forcing

the line current unbalance factor to be zero.

Therefore, Kirchoff’s laws are applied to obtain the line currents from the phase-to-

phase voltages:

2

6

6

4

I A

I B

I C

3

7

7

5

D

2

6

6

4

1 0 �1

�1 1 0

0 �1 1

3

7

7

5

2

6

6

4

Y 1 0 0

0 Y L 0

0 0 Y 2

3

7

7

5

2

6

6

4

V AB

V BC

V CA

3

7

7

5

; (1)

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Figure 1. (a) Railroad substation connection scheme and (b) Steinmetz circuit. (color figure avail-

able online)

and the symmetrical components of the line currents are obtained with the Fortescue

transformation:

2

6

6

4

I 0

IC

I�

3

7

7

5

D

2

6

6

4

1 1 1

1 a2 a

1 a a2

3

7

7

5

�1 2

6

6

4

I A

I B

I C

3

7

7

5

.a D ej 2�=3/: (2)

The unbalance factor of the line currents is then derived from the sequence currents:

mi D I�

IC

D I A C a2I B C aI C

I A C aI B C a2I C

D Y 1V AB.1 � a2/ C Y LV BC .a2 � a/ C Y 2V CA.a � 1/

Y 1V AB.1 � a2/ C Y LV BC .a � a2/ C Y 2V CA.a2 � 1/

D 1 � a2

1 � a� Y 1V AB C Y La2V BC C Y 2aV CA

Y 1V AB C Y LaV BC C Y 2a2V CA

: (3)

Figure 2. Elements, voltages, and currents of Steinmetz circuit.

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According to [14], Eq. (3) can be rewritten as

mi D 1 � a2

1 � a� Y 1.h � a2/ C Y La2.a2 � a/ C Y 2a.a � h/

Y 1.h � a2/ C Y La.a2 � a/ C Y 2a2.a � h/

; (4)

where

h D hr C j � hi D 1 C 2mu

1 � mu

.h � jhj/; (5)

and mu is the unbalance factor of the three-phase supply voltages, which is obtained as

follows:

2

6

6

4

V 0

VC

V�

3

7

7

5

D

2

6

6

4

1 1 1

1 a2 a

1 a a2

3

7

7

5

�1 2

6

6

4

V A

V B

V C

3

7

7

5

) mu D mu∠�u D V�

VC

: (6)

Considering supply voltage unbalance and the resistance of inductor X1 (i.e., mu and

R1), the values of the symmetrizing reactive elements X1 and X2 are obtained by forcing

the unbalance factor of the line currents consumed by the Steinmetz circuit (Eq. (4)) to

be zero (i.e., mi D jmi j D 0):

X1 DRL�2

1

n

2p

3�

hr.hr C 2/ C h2i

�

� �1.4.hr C 1/ � 2h2/o

2p

3�2L�2

1 fhr K3 C hi K2 C 2�Lg;

X2 DRL

n

2p

3�

hr .hr C 2/ C h2i

�

� �1.4.hr C 1/ � 2h2/o

2p

3�2LfhrK4 � hi K1 � 2�L � �1.hr K1 C hi K4 C 2/g

;

K1 D 1 Cp

3�L; K2 D 1 �p

3�L; K3 Dp

3 C �L; K4 Dp

3 � �L;

(7)

where �t D Rt=jZt j is the power factor of the single-phase load (t D L) and the inductor

(t D 1), and

�L D XL

RL

D

q

1 � �2L

�L

; �1 D R1

X1

D �1q

1 � �21

: (8)

The Steinmetz circuit is usually formed by static VAR compensators (SVCs), which

allow changing the reactance values according to Eq. (7) to compensate for the usual

fluctuations of single-phase load currents [10, 11].

The reactance values in Eq. (7) depend on five variables:

� the resistance RL and the power factor �L of the single-phase load,

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� the ratio between the resistance and reactance of inductor �1 (or also power factor

�1 of the Steinmetz circuit inductor, Eq. (8)), and

� the variable h, which characterizes the unbalance (or also magnitude mu and angle

�u of the unbalance factor, Eq. (5)).

Thus, these reactances can be expressed as Xb D gb.RL; �L; �1; mu; �u/ with b D 1,

2. In order to reduce the number of variables, the reactances can be normalized with

respect to the resistance of the single-phase load, i.e., Xb=RL D gb;N .�L; �1; mu; �u/

with b D 1, 2. The usual range of normalized reactance variables is

� power factor of the single-phase load: �L D .0:8; : : : ; 1/;

� ratio R=X of the inductor X1: �1 D .0; : : : ; 1/; and

� unbalance factor: mu D .0; : : : ; 0:05/ and �u D .0; : : : ; 360ı/.

The number of variables can also be reduced by using some approximations, but

then a compromise between the simplification of the problem and the error introduced

in the reactance calculation must be reached. The simplified expressions of the reactance

values can be derived from Eq. (7) considering the following three approximations:

� Approximation 1 (A1): balanced supply voltages (mu D 0, and therefore, h D1 C j 0, Eq. (5)):

X1;A1 D g1.RL; �1; 0; —/ D RL�21f

p3 � �1g

�2L�2

1 K1

;

X2;A1 D g2.RL; �1; 0; —/ D RLfp

3 � �1g�2

LfK2 � �1K3g;

(9)

where �u D “—” means that the value of the variable �u is irrelevant.

� Approximation 2 (A2): resistance of inductor X1 is neglected (�1 D 0, and

therefore, �1=�1 D 1):

X1;A2 D g1.RL; 0; mu; �u/ DRL

˚

hr.hr C 2/ C h2i

�2LfhrK3 C hi K2 C 2�Lg

;

X2;A2 D g2.RL; 0; mu; �u/ DRL

˚

hr.hr C 2/ C h2i

�2LfhrK4 � hi K1 � 2�Lg

:

(10)

These expressions are equivalent but simpler than those in [14].

� Approximation 3 (A3): balanced supply voltages (mu D 0, and therefore, h D1 C j � 0) and resistance of inductor X1 is neglected (�1 D 0, and therefore,

�1=�1 D 1):

X1;A3 D g1.RL; 0; 0; —/ Dp

3RL

�2LK1

Dp

3RL

�2Lf1 C

p3�Lg

;

X2;A3 D g2.RL; 0; 0; —/ Dp

3RL

�2LK2

Dp

3RL

�2Lf1 �

p3�Lg

:

(11)

These are the well-known analytical expressions proposed in Steinmetz circuit

design [1, 9, 10, 14]. They can also be derived from Eqs. (9) and (10) by imposing

�1 D 0 and h D 1 C j 0, respectively.

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The Steinmetz circuit under study (with inductor X1 and capacitor X2) turns out to

be possible only when X1 and X2 values are positive. This was numerically analyzed

from Eq. (7) considering the usual range of variables. Thus, X1 is always positive, while,

according to Figure 3, X2 is only positive when the power factor of the single-phase

load satisfies the condition 1 � �L � �LC D fLC .�1; mu; �u/. It must be noted that for

1 > �1 > 0:577, reactance X2 is always negative (see Appendix A).

Considering approximations A1, A2, and A3, the following analytical expression of

�LC can be derived from Eqs. (9), (10), and (11), respectively:

�LC;A1 D fLC .�1; 0; —/ D �1 Cp

3

2

q

1 C �21

;

�LC;A2 D fLC .0; mu; �u/ D hr Cp

3hi C 2

2

q

hr.hr C 1/ C hi .hi Cp

3/ C 1

;

�LC;A3 D fLC .0; 0; —/ Dp

3

2:

(12)

The expression of �LC;A1 corresponds to the curves of mu D 0 in Figure 3 (i.e.,

�LC;A1 D fLC .�1; 0; —/). The expression of �LC;A2 is equivalent but simpler than those

in [14]. The well-known value of �LC;A3 [14] can also be obtained by imposing �1 D 0 in

�LC;A1 or mu D 0.h D 1 C j � 0/ in �LC;A2. This value corresponds to the points �1 D 0

and mu D 0 in Figure 3 (i.e., �LC;A3 D fLC .0; 0; —/). It is also numerically verified that

the �LC D fLC .�1; mu; �u/ curves merge into in a single curve when �u D 30 C n � 180

(n D 1; 2; : : : ), and they overlap with the �LC;A1 curve, i.e.,

�LC D fLC .�1; mu; 30ı C n � 180ı/ D fLC .�1; 0; —/ D �LC;A1: (13)

3. Comparison Between the Steinmetz CircuitDesign Expressions

As mentioned in Section 2, Eq. (7) provides the values of Steinmetz circuit reactive

elements X1 and X2 considering the unbalanced supply voltages (i.e., mu ¤ 0) and

the resistance of inductor X1 (i.e., R1 D �1 � X1 ¤ 0). However, these values can also

be approximately calculated with the simplified expressions in Eqs. (9), (10), and (11),

which are derived from Eq. (7) with approximations A1, A2, and A3, respectively. These

expressions are simpler than Eq. (7), but the error that they introduce in the calculations

must be checked to ensure their applicability.

Considering the feasible zones of X2 in Figure 3, the locus of Xb=RL D gb;N .�L; �1;

mu; �u/ with b D 1, 2 was numerically calculated from Eq. (7) and is shown in Figure 4

for �L D 1, 0.95, and 0.9 and �1, mu, and �u values, which verify the restriction

1 � �L � �LC D fLC .�1; mu; �u/. As can be observed in Figure 4,

� in all plots, the central points of the Xb=RL locus correspond to Xb;A1=RL Dgb;N .�L; �1; 0; —/ (Eq. (9)) and

� the �1 D 0 plots correspond to the locus of Xb;A2=RL D gb;N .�L; 0; mu; �u/

(Eq. (10)), and the central point of this locus corresponds to Xb;A3=RL D gb;N .�L;

0; 0; —/ (Eq. (11)).

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Figure 3. Plots of �LC D fLC (�1, mu, and �u).

Thus, the different values obtained from the X1 and X2 expressions can be checked

to analyze how far the approximated values (i.e., Xb;A1, Xb;A2, and Xb;A3 values) are from

those obtained from Eq. (7). For example, if the value of the Steinmetz circuit variables is

RL D 20 �, �L D 1:0, mu D 0:03∠ � 30ı, and �1 D 0:2, the normalized reactances are

X1=RL D 1:57 p.u. and X2=RL D 2:26 p.u. (X1 D 31:46 � and X2 D 45:25 �, Eq. (7))

and are located as point P in Figure 4. Nevertheless, according to approximations A1 to

A3, they could be X1;A1=RL D 1:47 p.u. and X2;A1=RL D 2:34 p.u. (X1;A1 D 29:46 �

and X2;A1 D 46:88 �, Eq. (9)), X1;A2=RL D 1:82 p.u. and X2;A2=RL D 1:73 p.u.

(X1;A2 D 36:51 � and X2;A2 D 34:70 �, Eq. (10)) or X1;A3=RL D 1:73 p.u. and

X2;A3=RL D 1:73 p.u. (X1;A3 D 34:64 � and X2;A3 D 34:64 �, Eq. (11)). These values

are located as points PA1, PA2, and PA3 in Figure 4, respectively.

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Figure 4. Locus of reactive elements X1 and X2. (color figure available online)

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To validate the goodness of the approximated values, the errors between them and

Eq. (7) are numerically calculated as follows:

eb;a D 100Xb � Xb;a

Xb

.b D 1; 2I a D A1; A2; A3/; (14)

and are plotted in Figures 5, 6, and 7, respectively. The eb;A1 values in Figure 5 correspond

to the error made when using Eq. (9) by not considering the supply voltage unbalance

(mu D 0) in the reactance calculation. For a given power factor �L, this error represents

the difference between the central point of each plot and the rest of the chart points.

In the previous example, it is the difference between P and PA1 points in Figure 4, i.e.,

e1;A1 D 10031:46 � 29:46

31:46D 6:36%;

e2;A2 D 10045:25 � 46:88

45:25D �3:60%:

(15)

These values are located as point PA1 in Figure 5. The eb;A2 values in Figure 6 are

the error made when using Eq. (10) by not considering the resistance of the Steinmetz

inductor (�1 D 0) in the reactance calculation. For a given power factor �L, this error

represents the difference between the chart points of the �1 D 0 plots and the rest of the

plot points. In the previous example, it is the difference between P and PA2 points in

Figure 4, i.e.,

e1;A2 D 10031:46 � 36:51

31:46D �16:05%;

e2;A2 D 10045:25 � 34:70

45:25D 23:31%:

(16)

These values are located as point PA2 in Figure 6. The eb;A3 values in Figure 7 are

the error made when using Eq. (11) by not considering supply voltage unbalance and the

resistance of the Steinmetz inductor (mu D 0 and �1 D 0, respectively) in the reactance

calculation. For a given power factor �L, this error represents the difference between the

central point of the �1 D 0 plots and the rest of the plot points. In the previous example,

it is the difference between P and PA3 points in Figure 4, i.e.,

e1;A3 D 10031:46 � 34:64

31:46D �10:12%;

e2;A3 D 10045:25 � 34:64

45:25D 23:45%:

(17)

These values are located as point PA3 in Figure 7.

According to the above example and Figures 5, 6, and 7, the most critical approx-

imation is A2 (i.e., no consideration of the inductor resistance) and the most sensitive

reactance to the approximations is capacitor X2. Thus, considering that R1 D � � X1 D 0

can lead to the calculation of unacceptable reactance values, in particular, X2 values.

4. Tests

To illustrate the design of the Steinmetz circuit, a numerical test and two practical tests

are presented. They confirm the conclusions presented in Section 3.

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Figure 5. Locus of errors e1; A1 and e2; A1. (color figure available online)

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4.1. Numerical Tests

The balancing of the line currents consumed by a single-phase load of parameters RL D16 � and �L D 0:95 is analyzed. The symmetrizing reactive elements of the Steinmetz

circuit are calculated from the expressions in Section 2. The results and A1, A2, and A3

errors in Eq. (14) are shown in Table 1. The reactance and error values are located as

points Q, QA1, QA2, and QA3 in Figures 4 to 7.

The system (Figure 2) studied with the parameters of the numerical test is simu-

lated with PSpice software. The current waveforms before and after the connection of

reactances X1 and X2 or X1;a and X2;a (a D A1, A2, or A3) at instant t D 20 ms are

plotted in Figure 8; the voltage waveforms are also plotted as a reference. The unbalance

factors of the three-phase voltage and currents are also labeled in Figure 8, while the

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Figure 8. PSpice: (a) voltage and (b) current waveforms of the numerical test. (color figure avail-

able online)

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Table 1

Results of the numerical test

(RL D 16 �, �L D 0:95, �1 D 15%, mu D 2∠30ı%)

Equation

P1:

Eq. (7)

P2: A1,

Eq. (9)

P3: A2,

Eq. (10)

P4: A3,

Eq. (11)

X1=RL (p.u.) 1.13 1.09 1.25 1.22

X2=RL (p.u.) 15.1 14.4 4.62 4.46

e1;a (%) 3.09 �11.2 �8.47

e2;a (%) 4.56 69.4 70.5

contour plot of the current unbalance factor in the function of the reactance values is

shown in Figure 9. The current unbalance factors obtained with the different reactance

values (Table 1) are also labeled in this figure.

4.2. Practical Tests

Two practical tests from the literature are analyzed to illustrate the design of the Steinmetz

circuit design with the proposed expressions.

In [9], an unbalance study on the Channel Tunnel 25-kV railway system supplied

from the U.K. and French 400-/225-/132-kV grid systems was presented. On the U.K.

side, the point of common coupling (PCC) between the traction load and the tunnel

auxiliary load is at the Folkestone 132-kV busbar with a minimum short-circuit power

SSC equal to 800 MVA. The traction loads on the busbar of U0 D 25 kV range from

SL D 0 to 75 MVA with a displacement power factor �L D 0:93, and the Steinmetz

circuit with fast-acting thyristor-controlled reactors (TCRs) is connected in order to

enable the balancing equipment output to vary with the load pattern. In this section,

the Steinmetz circuit design is analyzed considering mu D 0:02∠45ı and �1 D 0:1 and

Figure 9. Current unbalance factor contour plot of the PSpice numerical test. (color figure available

online)

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Figure 10. Evron installation study: (a) time-varying consumptions, (b) Steinmetz circuit normal-

ized reactances, (c) errors e1;a (a D A1, A2, and A3), and (d) errors e2;a (a D A1, A2, and A3).

(color figure available online)

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that the normalized reactances are X1=RL D 1:14 p.u. and X2=RL D 23:42 p.u. (Eq. (7)).

According to approximations A1 to A3, the results are X1;A1=RL D 1:11 p.u. and

X2;A1=RL D 18:37 p.u. (i.e., e1;A1 D 2:43% and e2;A1 D 21:57%), X1;A2=RL D 1:21 p.u.

and X2;A2=RL D 6:93 p.u. (i.e., e1;A2 D �6:82% and e2;A2 D 70:42%), or X1;A3=RL D1:19 p.u. and X2;A3=RL D 6:35 p.u. (i.e., e1;A3 D �4:59% and e2;A3 D 72:89%). Results

are the same for the whole traction load range but not for the reactance values, which

vary with traction load power fluctuations.

In [11], the active Steinmetz circuit design on the Evron substation of the French

Railways is analyzed. In this substation, two transformers with 16 MVA of rated power

feed the 25-kV traction load, which consumes a time-varying current. The measurements

of this current, provided in [11], are shown in Figure 10(a). In this test, an unbalance

factor of mu D 0:015∠45ı and a ratio of �1 D 0:2 are considered, because there is no

other information thereon. The instantaneous SVC normalized reactance values X1=RL

and X2=RL (Eq. (7)) and the errors eb;a (b D 1, 2 and a D A1, A2, A3) determined

from the traction system data are shown in Figure 10. Data with displacement power

factors below �LC are not considered because they do not provide feasible results

of the SVC reactance values. From Figure 10, it is confirmed that the most critical

approximation is the lack of consideration of the inductor resistance and that the most

sensitive reactance to the approximations is capacitor X2. Moreover, the error in the

determination of the Steinmetz circuit inductor with approximation 2 (i.e., e1;A2) is

independent of the single-phase load. This can be verified by developing Eq. (14) from

Eqs. (7) and (10).

5. Conclusions

This article analyzes the balancing of three-phase line currents consumed by single-phase

loads using the Steinmetz circuit. The circuit is designed considering the supply voltage

unbalance and the resistance of the Steinmetz inductor. Novel analytical expressions

for the symmetrizing reactances are proposed. Approximated expressions are derived

from the previous ones, and a detailed comparison between the original and approximated

expressions is made. It is concluded that neglecting the inductor resistance can be critical

in the circuit design, with the Steinmetz capacitor being the most sensitive reactance. A

numerical example of the Steinmetz circuit design and two practical cases are studied

to compare the results provided by the reactance expressions. The numerical example

is completed with PSpice simulations to obtain the current waveforms before and after

connecting the balance elements.

References

1. Chindris, M., Cziker, A., Stefanescu, S., and Sainz, L., “Fuzzy logic controller for Steinmetz

circuitry with variable reactive elements,” Proceedings of the 8th International Conference

(OPTIM), pp. 233–238, Porto, 1–3 September 2001.

2. Arendse, C., and Atkinson-Hope, G., “Design of a Steinmetz symmetrizer and application in

unbalanced network,” Proceedings of the 45th International Universities Power Engineering

Conference (UPEC), pp. 1–6, Cape Town, 31 August–3 September 2010.

3. Mayer, D., and Kropik, P., “New approach to symmetrization of three-phase networks,” J.

Elect. Eng., Vol. 56, No. 5–6, pp. 156–161, 2005.

4. Chicco, G., Chindris, M., Cziker, A., Postolache, P., and Toader, C., “Analysis of the Stein-

metz compensation circuit with distorted waveforms through symmetrical component-based

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ry 2

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indicators,” Proceedings of the IEEE Bucharest Power Tech Conference, pp. 1–6, Bucharest,

28 June–2 July 2009.

5. Capasso, A., “The power quality concern in railway electrification studies,” Proceedings of the

8th IEEE International Conference on Harmonics and Quality of Power (ICHQP), pp. 647–

652, Athens, 14–18 October 1998.

6. Hill, R. J., “Electric railway traction. Part 3: Traction power supplies,” Power Eng. J., Vol. 8,

No. 6, pp. 275–286, 1994.

7. Marczewski, J. J. and the IEEE Working Group on System and Equipment Considerations for

Traction, “Utility interconnection issues,” IEEE Power Engineering Society Summer Meeting,

pp. 439–444, Edmonton, Alta, 18–22 July 1999.

8. Howroyd, D. C., “Public supply disturbances from AC traction,” Proceedings of the In-

ternational Conference on Main Line Railway Electrification, pp. 260–264, London, 25–

28 September 1989.

9. Barnes, R., and Wong, K. T., “Unbalance and harmonic studies for the Channel Tunnel railway

system,” IEE Proc. B Elect. Power Appl., Vol. 138, No. 2, pp. 41–50, 1991.

10. ABB Power Transmission, “Multiple SVC installations for traction load balancing in Central

Queensland,” Pamphlet A02-0134, available at: http://www.abb.com

11. Giuliano, R., “Active Steinmetz circuit in a single phase railway substation,” International

Exhibition and Conference for Power Electronics, Intelligent Motion, Power Quality (PCIM),

Nuremberg, Germany, 17–19 May 2001.

12. IEC, “Compatibility levels for low-frequency conducted disturbances and signalling in public

low-voltages power systems,” IEC Standard 1000-2-2, 1990.

13. IEC, “Compatibility levels in industrial plants for low-frequency conducted disturbances,” IEC

Standard 1000-2-2, 1994.

14. Jordi, O., Sainz, L., and Chindris, M., “Steinmetz system design under unbalanced conditions,”

Eur. Trans. Elect. Power, Vol. 12, No. 4, pp. 283–290, 2002.

Appendix A

In order to analyze the Steinmetz circuit balancing domain in Figure 3, the following

expression is derived from Eq. (1):

2

6

6

4

I A

I B

I C

3

7

7

5

D

2

6

6

4

I 1 � I 2

I L � I 1

I 2 � I L

3

7

7

5

D

2

6

6

4

0

I L

�I L

3

7

7

5

C

2

6

6

4

I 1

�I 1

0

3

7

7

5

C

2

6

6

4

�I 2

0

I 2

3

7

7

5

; (A1)

where

I L D V BC

ZL

D VBC

ZL

j�BC � �L;

I 1 D V AB

R1 C jX1

D VAB

X1

q

�21 C 1

j�AB � �1;

I 2 DV CA

�jX2

DVCA

X2

j�CA C �=2;

(A2)

and �t D cos�1.�t / with t D L and 1.

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The symmetrical components of the currents in Eq. (A1) are obtained by applying

the Fortescue transformation of Eq. (2):

2

6

6

4

I 0

IC

I�

3

7

7

5

D

2

6

6

4

1 1 1

1 a2 a

1 a a2

3

7

7

5

�1 2

6

6

4

I A

I B

I C

3

7

7

5

D

2

6

6

4

I L;0

I L;C

I L;�

3

7

7

5

C

2

6

6

4

I 1;0

I 1;C

I 1;�

3

7

7

5

C

2

6

6

4

I 2;0

I 2;C

I 2;�

3

7

7

5

; (A3)

where, considering balanced supply voltages (mu D 0) with the phasorial diagram in

Figure A1(a), the negative sequence currents are

I L D V

ZL

j��=2 � �L

I 1 D V

X1

q

�21 C 1

j�=6 � �1

I 2 D V

X2

j�2�=3

9

>

>

>

>

>

>

>

>

>

=

>

>

>

>

>

>

>

>

>

;

)

8

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

<

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

ˆ

:

I L;� D 1

3IL � .a2 � a/ D

p3

3

V

ZL

j� � �L

I 1;� D 1

3I 1 � .1 � a2/ D

p3

3

V

X1

q

�21 C 1

j�=3 � �1

I 2;� D 1

3I 2 � .1 C a/ D

p3

3

V

X2

j�=6

:

(A4)

Considering that I�

D I L;� C I 1;� C I 2;� (Eq. (A3)), the phasorial diagram of

these currents is provided (Figure A1(b)) to analyze the Steinmetz circuit balancing

(I�

D 0) domain. It can be observed that the negative sequence current angle of the

Steinmetz circuit inductor usually ranges between �=3 � �=4 D �=12.�1 D 1/ and

�=3 � �=2 D ��=6.�1 D 0/. Nevertheless, this angle must be below 0 (i.e., �1 > �=3,

and therefore, �1 < cos.�=3/ D 0:5 and �1 < 0:577) so that the Steinmetz circuit

(with an inductor and a capacitor) is able to balance the negative sequence current of the

single-phase load. For �1 D 0:577.�1 D �=3/, the negative sequence current angle of

the Steinmetz circuit inductor is equal to 0, and the Steinmetz circuit can only balance

Figure A1. Phasorial diagrams of the Steinmetz circuit: (a) supply voltages and (b) negative se-

quence currents. (color figure available online)

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negative sequence currents of the single-phase load with angles equal to � (i.e., �L D 0,

and therefore, �L D 1). For �1 D 0.�1 D �=2/, the negative sequence current angle of

the Steinmetz circuit inductor is equal to �� /6, and the Steinmetz circuit can balance

negative sequence currents of the single-phase loads with angles ranging between � (i.e.,

�L D 0, and therefore, �L D 1) and 5�=6 (i.e., �L D �=6, and therefore, �L Dp

3=2).

The �LC;A1 expression in Eq. (12) can be deduced from Figure A1(b) as follows:

�LC;A1 D cos.�LC;A1/ D cos��

3� �1

�

D cos��

3� cos�1.�1/

�

D cos

0

B

@

�

3� cos�1

0

B

@

�1q

�21 C 1

1

C

A

1

C

A

D cos��

3

� �1q

�21 C 1

C sin��

3

�

s

1 � �21

�21 C 1

D �1 Cp

3

2

q

�21 C 1

: (A5)

The unbalance supply voltage consideration in the 5% range (i.e., mu < 0:05) slightly

affects the angles �BC , �AB , and �CA in Eq. (A2), slightly modifying the final results of

the negative sequence currents I L;�, I 1;� and I 2;� and the final �LC curves (Figure 3).

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theoretical study of the steinmetz circuit design

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