Piero Belforte

April 11 2013

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TDR setup: CSA 803 and RG58 cable fixture

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Detail of SD24 head and cable connection fixtureCable connection to SD24 ports is achieved by means of two 60mm long SMA semirigid cables soldered to a reference ground plane (FR4 pcb). Cables under test inner conductors are connected together by means of short soldered splices.

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S11/S22 (measure)Heavy distributed impedance discontinuities (up to more than 50mrho pp) are pointed out by the measurement.

The cable is not symmetrical (S11 not equal to S22) due to these discontinuities

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S21

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OPTIMIZED SETUP MODEL(1) : Spicy SWAN schematicThis model utilizes an ERFC approximation of TDR waveform taking into account SMA fixture effects.

Connection spices are modeled by two equal TL (TSOLD1,TSOLD2).

RG58 CU cable is modeled as a cascade of 366 X 5cm RL-TL cell.

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SETUP DISCONTINUITIES (soldered splices between semirigid fixture ) can be used as TIME MARKERS.Comparing the measured S11 (red) to the simulated one (blue) the exact matching of marker position is achieved adjusting the value of TD of elementary RL_TL cell of the model. A slight reduction from nominal 25.3ps to 24.75ps was needed for perfect match

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FIRST SPLICE MODEL OPTIMIZATION Z0 and Td of TL model of the splice (TSOLD1) are optimized to match the first peak of actual measure . The same parameters are assigned to the second splice (TSOLD2)

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Actual SD24 TDR HEAD (CSA 803) waveformThe following is the actual waveform generated by Ch1 and observed on Ch2. The connection is made using a wideband 40cm SMA cable. In this way the step dispersion due to the fixture of RG58 cable is taken into account.The resulting risetime is 22.5ps between 20% and 80%, while the observed risetime at Ch1 (generator) is 17ps.

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Normalized TDR waveform (0-2rho)

This is 19-breakpoints PWL approximation of the previous SD24 waveform. The step amplitude has been normalized between 0 and 2rho for utilization in the simulative DWS model (model 2)

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OPTIMIZED SETUP MODEL(2)This is the Spicy SWAN schematic of the simulative model (2) using the pwl approximation of TDR step generator (VTDR).Splice models parameters are optimized , and the RG58 elementary RL-TL cell delay is optimized as well. The sim time step has been chosen to be 1/10of elementary cell delay (Tstep=2.475ps) to minimize overall delay errors.

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* Netlist and simulation file* Generated by: SPICY Schematics (ischematics.com)* File: CSA803_RG58_1.83m_3******************************************* Author: Piero Belforte* Date: March 28 2013* Desc: CSA803 actual setup model for 1.83m RG58* coax S-parameter measurement: actual SD24* CSA 803 waveform (pwl) and optimized* setup discontinuities.******************************************.CHAIN 366*RG58_RLT_5mm_OPT I:14; O:15TTDR 2 0 7 0 Z0=50 TD=500p TSOLD1 7 0 140001 0 Z0=100 TD=20p TSOLD2 150366 0 8 0 Z0=100 TD=20p R0 8 0 50 VTDR 2 0 PWL (0.00ps 0 11.50ps 0.03088 16.50ps 0.06504 21.50ps 0.12632+ 27.00ps .248 31.25ps .3888 39.25ps .7632 47.50ps 1.23552+ 54.25ps 1.59472 60.50ps 1.84672 66.00ps 1.9884 70.50ps 2.04816+ 75.75ps 2.047 91.75ps 1.9 97.25ps 1.878 110.25ps 1.928+ 119.00ps 1.957 139.25ps 1.928 162.00ps 2) 50 * {RS} N_5=1 N_S11=2 N_2=3 N_3=4 UN_2=140001 UN_3=150366 UN_5=7 N_S21=8 ******************************************* MODELS USED IN CIRCUIT ***************************************************************** Spicy SWAN - Model File* http://ischematics.com* Author: Piero Belforte* Date: Thu 04 Apr 2013 21:24:25 GMT**********************.CELL RG58_RLT_5mm_OPT 14 15R2 22 23 .10527 L2 0 24 1.734p R3 23 25 .035811 L3 0 26 3.151p R4 25 27 .016176 L4 0 28 6.6198p R5 27 29 7.3875m L5 0 6 13.469p

R6 29 7 3.3826m L6 0 4 25.327p R7 7 5 1.6371m L7 0 11 45.323p R8 5 12 .8425m L8 0 8 80.524p R9 12 9 .41854m L9 0 2 .11427n R10 9 3 .35315m L10 0 21 .40739n R11 3 20 .11879e-3m L11 0 19 18.906n R1 14 22 .2224m T0 20 0 15 0 Z0=49.942 TD=24.75p AS2 22 23 24 AS3 23 25 26 AS4 25 27 28 AS5 27 29 6 AS6 29 7 4 AS11 3 20 19 AS7 7 5 11 AS8 5 12 8 AS9 12 9 2 AS10 9 3 21 .ENDC RG58_RLT_5mm_OPT******************************************* Simulations* Note: This portion below is updated when you simulate******************************************.OPTIONS DELAYMETH=INTERPOLATION.TEMP 27.TRAN TSTEP=2.475e-12 TSTOP=50e-9 TSTART=0e-9 LIMPTS=5000 I(VTDR,2) A(VTDR,2) A(R0,8).END

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Spicy SWAN (DWS) results of model (2)The following are the plots of simulated S11 and S22 of previous setup.This sim requires about 30s with about 20K points and 28K model elements.

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The following slides show the differences between measured and simulated waveforms including setup effects.

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The RL-TL cell model is practically symmetrical, while the actual cable is not.Actual cable S11/S22 values are under-estimated with respect model values due to distributed impedance discontinuities.Overall behavior after first reflection shows good agreement between model and meaure

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measuremodel

Splice 1 discontinuity

Distributed impedance discontinuities

The waveforms are not matched in time for better comparison.Distributed impedance discontinuities on the actual cable are well visible.

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model

measure

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model

measure

S21 edge comparison (model1)In this slide the absolute delays are taken into account (Splice markers matched) Measured 20%-80% risetime : 80ps vs 70ps of model. The measured waveform has a slower foot but a faster edge in the upper part. This is due probably to dielectric losses (slower foot). The faster upper part can be due to stranded conductors of the actual cable,

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S21:measure

S21:model

S21 edge comparison (model2)

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In this slide the splice markers are NOT exactly matched to superimpose the waveforms.The measured risetime is identical to that of model:80ps, but the shape differences of model 1 are confirmed: slower measured waveform foot andfaster upper portion of measured edges

Measure

Model

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measureRL-TL model

5 Gbit/sec

10 Gbit/sec

WCED: Worst Case Eye Diagrams : YELLOW 5Gbit/sec, RED 10Gbit/sec

EYE CLOSURE and ISI JITTER are slightly higher in the measure due to dielectric losses not taken into account in the model

EYE shapes are more symmetrical in the measure: this can be also due to dielectric losses not taken into account in the model

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Removing Splices from the simulative model, the simulated eye diagram gets more open and less similar to the eye calculated from actual measure (including splice effects). The dielectric loss effect (not considered in the model) symmetrizes the eye diagram.

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S11

PWL-BTM model

RL-TLS21

BTM

RL-TL

As can be pointed out from the plots the BTM is far more realistic than the RL-TL model. It is also 10-50 times FASTER (sim time under 1sec).

Conclusions The used setup is effective for a 1.83m long cable characterization The TDR incident pulse risetime (22ps) is fast enough to achieve good waveform

resolution (80ps risetime at cable’s output) Actual cable shows sensible impedance discontinuities (S11) Actual cable is asymmetrical Theoretical cable delay is slightly overestimated RL-TL model gives good S11 estimate (without discontinuities) S21 edge risetime agreement is good (70-80ps) Dielectric losses have to be added to achieve better S21 waveform match (edge

foot too fast in the sim model) Skin effect losses are probably over-estimated (upper S21 edge too slow) EYE CLOSURE and ISI JITTER (5-10Gbit/sec) slightly higher in the measure due to

dielectric losses not taken into account in the model DWS is very effective in terms of accuracy and sim times (50X faster than MC10) BTM S-parameters modeling supported by DWS can take into account effects like

distributed discontinuities and asymmetricity of actual cable with a further speed-up factor of 10X to 50X (more than 3 orders of magnitude faster than MC10)

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[1] Piero Belforte, Spartaco Caniggia, “CST coaxial cable models for SI simulations: a comparative study”, March 24th 2013

[2] P. Belforte, S. Caniggia,, “Measurements and Simulations with1.83-m RG58 cable”, April 5th 2013