Pramana – J. Phys. (2021) 95:165 © Indian Academy of Scienceshttps://doi.org/10.1007/s12043-021-02210-0

TCAD simulation study on reliability issue of heterojunctionheterodielectric FinFET: Effect of interface trap charge, BOXheight and temperature

YASH HIRPARA1 and RAJESH SAHA2,∗

1School of Electronics Engineering, Vellore Institute of Technology, Andhra Pradesh University,Amravati 522 237, India2Department of Electronics and Communication Engineering, Malaviya National Institute of Technology,Jaipur 302 017, India∗Corresponding author. E-mail: rajeshsaha93@gmail.com

MS received 10 January 2021; revised 20 April 2021; accepted 21 June 2021

Abstract. In this paper, a heterojunction FinFET on heterodielectric BOX is proposed and this device is namedas heterojunction heterodielctric BOX (HJHDB) FinFET, to eliminate the effect of trap density. The interface trapcharge is considered at the interface of Si-HfO2 in technology computer aided design (TCAD) simulator. The effectof trap charges on transfer characteristics, surface potential, subthreshold swing (SS) and threshold voltage areinvestigated for both HJHDB FinFET and conventional FinFET (C-FinFET) taking box height as a parameter. Suchanalysis is also demonstrated by varying the temperature in wide ranges for both the devices. It is seen that there isno effect of fixed trap in HJHDB FinFET even at high temperature, whereas a noticeable amount of trap effect isobserved for C-FinFET. Furthermore, the effect of trap level on various electrical parameters is presented for bothdevices and an insignificant amount of trap level variation is observed for HJHDB FinFET. On the other hand, avisible impact of trap level is observed in C-FinFET.

Keywords. FinFET; heterodielectric BOX; heterojunction; interface trap charge; temperature.

PACS Nos 61.82.Fk; 71.30.+h; 73.40.Qv; 72.80.Cw

1. Introduction

MOSFET technology has played a very vital role inthe continuous growth of semiconductor industry. Byincreasing the number of transistors on a single chip,the continuous scaling of the MOSFET transistor hasdegraded the device performance, which leads to highleakage current and severe short-channel effects (SCEs)[1,2]. In this aspect, FinFET is a strong candidate, dueto its excellent immunity against SCEs and its com-patibility with the CMOS fabrication process [3,4].Various possibilities like modification of device archi-tecture, channel/source material other than silicon, gatework function engineering, etc. were introduced bythe researchers to improve the performance of Fin-FET. Many FinFET geometries such as double gate,triple gate, gate all around FinFET [5], pie gate Fin-FET [6], omega FinFET [7] and cylindrical FinFET[8] are reported in the literature. Moreover, to have

high ON current, a heterojunction FinFET with Gesource is reported and its electrical properties for vari-ous fin dimensions are analysed [9]. Various electricalparameters such as transfer characteristic, output char-acteristic, switching ratio and subthreshold swing (SS)of high-k spacer junctionless FinFET (HKS JL-FinFET)are compared with conventional FinFET (C-FinFET)[10]. It is seen that HKS JL-FinFET performs bet-ter than C-FinFET. The DC and RF performances ofJL-FinFET are studied for two different oxide thick-nesses (tox = 0.4 and 1 nm) and it is reported thatdevice with tox = 1 nm has improved cut-off fre-quency and unilateral gain compared to tox = 0.4nm [11]. For high power and mobility, a multichannelFinFET AlGaN/GaN high electron mobility transistor(HEMT) is optimised for various layer thicknesses, finwidths and channel doping concentrations [12]. Resultsreveal that FinFET with four channels has 3.2 timesmore transconductance than single channel device. The

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effect of γ -ray radiation on DC and RF parameters arereported with scaling of various device parameters suchas gate length, number of fins and number of fingersin 10 nm n-FinFET [13]. The result reveals the γ -rayradiation degrades the maximum oscillation frequency,whereas cut-off frequency remains unchanged. The per-formance improvement and reduction in variability canbe achieved through source/drain extension (SDE) inFinFET architecture and SDE doping is optimised tosuppress the variability and enhance the ION/IOFF ratio[14]. The RF parameters are suppressed and linearityfigure of merits (FOMs) are improved in Fe-FinFET astemperature is increased, as pointed out by Saha et al[15].

On the other hand, reliability and applicability of thedevice for a wide variation in temperatures is a majorconcern and therefore, the effect of temperature andinterface trap charges (ITC) have to be analysed. For thenanoscale device, the impact of interface trap chargespresent at the semiconductor and oxide interface is veryprominent from the perspective of reliability. The inter-face trap fluctuation (ITF) with high-k/metal gate devicedemonstrated that ITF affects the device performancewhen it works in the strong inversion region [16]. Thepresence of ITC at the semiconductor and oxide inter-face reduces the electron mobility, which leads to areduction in current [17].

Das and Baishya [18] have reported that the change inelectrical characteristics in the presence of trap chargesis negligible when heterodielectric BOX is consideredinstead of homodielectric BOX. Amoroso et al [19]reported that the impact of trap can be reduced by scalingdown the fin dimensions and the applied gate volt-age. Moreover, SRAM circuit implemented by FinFEThas reduced statistical variation in read noise margin(RNM) and write noise margin (WNM) with increase intrap density [20]. The variability in threshold voltage issuppressed for NC-FinFET compared to conventionalFinFET in the presence of interface trap density [21].Likewise, the electrical characteristics of NC-Ge Fin-FET is improved with increased positive trap charges,whereas it degrades with negative trap charges [22].Moreover, the effect of trap charge is very significant intunnel FET (TFET) due to changes in the electric fieldinduced by ITC. Madan and Chaujar [23] have demon-strated that the OFF-state of the device changes tremen-dously for the variation in trap charge densities. In [24],a comparative study of conventional SOI TFET, gate-on-source TFET and gate-on-source/channel TFET areinvestigated in the presence of trap charge. The analysishighlighted that gate-on-source/channel TFET has bet-ter immunity against the interface trap charge variation.It also exhibits higher ON current and ON to OFF currentratio than the other devices. The impact of interface trap

Figure 1. 3D view of the FinFETs. (a) Heterojunction het-erodielectric BOX (HJHDB) FinFET and (b) conventionalFinFET.

charge on electrical parameters in NC-FinFET revealsthat NC-FinFET is more resilient towards interface trapcharge than the conventional FinFET [25].

In this paper, a heterojunction heterodielectric BOX(HJHDB) FinFET is proposed to reduce the effect of trapcharge. The HJHDB FinFET can eliminate the effectof trap charge at various box thicknesses, temperaturesand wide range of trap levels. Such effect of trap isdemonstrated on various electrical parameters like trans-fer characteristics, surface potential, subthreshold swingand threshold voltage.

2. Device structure and TCAD deck

The 3D views of the heterojunction heterodielectricBOX (HJHDB) and conventional FinFETs (C-FinFETs)are shown in figures 1a and 1b, respectively. For HJHDBFinFET, the source region is made of germanium,whereas channel and drain regions are made of silicon;the high-k (HfO2) dielectric material (k = 22) is con-sidered as BOX under the drain region and the low-k(SiO2) dielectric material (k = 3.9) is used as BOXfor the remaining region. For C-FinFET, silicon andSiO2 are considered as the fin material and the BOX,respectively. However, HfO2 and metal with work func-tion (�M = 4.4 eV) are considered as gate dielectricand gate material, respectively, for both the structures. Astandard value of drain bias (VDS) = 0.5 V is considered.The n+ source/n+ drain regions are doped with concen-tration of 1019 cm−3 and the p-type channel region isdoped with concentration of 1015 cm−3. The variousdevice dimensions are: fin thickness (Tfin) = 10 nm, finheight (Hfin) = 20 nm, gate oxide thickness (tox) = 1.5nm, gate length (L) = 30 nm and the height of the BOX(tbox) is varied.

All the simulations have been carried out using theTCAD Sentaurus simulator [26] and we have con-sidered calibrated physics model during simulation asmentioned in our previous work [27]. The various

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Figure 2. Effect of trap charges for different box height on transfer characteristics for (a) HJHDB and (b) C-FinFETs.

physics models activated during simulations are: thecarrier transport model used is a drift-diffusion model,which solves the Poisson’s and carrier transport equa-tions; Fermi–Dirac statistics and Slootboom modelsare used to consider the highly doped source/drainregion; Shockley–Read–Hall (SRH) model is activatedfor recombination of the carriers; to consider the mobil-ity of the carriers the doping-dependent Masetti modelwith adjusted parameters is enabled in the simulator. Inthis work, interface trap charge (ITC) is considered atthe interface of Si–HfO2 in the channel region of 1012

cm−3 trap density according to the published data [28].However, to analyse the effect of trap variations, the trapdensity is varied from 1011 to 1013 cm−3. The distribu-tion of the trap charge density is considered uniform forthe entire simulations.

3. Results and discussion

3.1 Effect of BOX height

The effect of interface trap charge on transfer charac-teristics for both the HJHDB and C-FinFETs are shownin figures 2a and 2b, respectively. The increase in boxheight enhances the channel potential, which resultsin the high value of ON current for both devices. Asexpected, the ON current reduces in the presence oftrap charges (figure 2). It is seen from figure 2a thatthe effect of trap is insignificant in HJHDB compared tothe conventional device and this is due to the presenceof high-k BOX under the drain region. This high-k BOXeliminates the depletion region under the channel–draininterface and accordingly, the trap effect gets nullified[29]. It can be better explained from figure 3, whichshows the effect of trap charges on the channel potentialfor both the devices. It is seen that there is no effect oftrap charges for HJHDB FinFET, whereas the potentialof C-FinFET is significantly affected by trap charge.

Figure 3. Effect of trap charges on potential for both HJHDBand C-FinFETs when tbox = 40 nm.

The effects of trap charges on SS and threshold volt-age taking box thickness as a parameter are portrayed infigures 4a and 4b, respectively. As box height increases,the leakage current decreases, which leads to a decreasein SS values for both the devices as summarised in fig-ure 4a. As expected, the effect of trap on SS value isinsignificant for HJHDB FinFET, whereas trap effectis prominent for C-FinFET. The threshold voltage ofthe devices is measured at a constant current of 10−7

A, and ON current increases with box thickness, whichcorrespond to an increase in threshold voltage as shownin figure 4b. It is also observed that the effect of trapcharges is significant for C-FinFET and such effect isnot observed for HJHDB FinFET.

3.2 Effect of temperature

The effect of temperature in the presence of trap chargesfor both the devices is studied by plotting the trans-fer characteristics as shown in figure 5. It is seen thatthe effect of temperature is very prominent for both thedevices. However, even at high temperature, the impactof trap charge is negligible in HJHDB FinFET. At highgate voltage, the mobility of the carriers reduces, whichleads to a decrease in ON current. However, at low gatevoltage, energy band gap reduces with increased temper-ature which results in an increase in OFF current. Again,

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Figure 4. Effect of trap charges on (a) SS vs. box height and (b) threshold voltage vs. box height for both HJHDB andC-FinFETs.

Figure 5. Effect of trap charges for different temperature on transfer characteristics for (a) HJHDB and (b) C-FinFETs whentbox = 40 nm.

the effect of trap charge on the potential for HFHDB andC-FinFETs are shown in figures 6a and 6b, respectively.It is observed from the potential plot that the effect oftrap charge is absent in HJHDB at high temperature (fig-ure 6a), whereas this effect is prominent in C-FinFET(figure 6b).

The effects of temperature on SS and threshold volt-age in the presence of trap charges for both the devicesare shown in figures 7a and 7b, respectively. It is visu-alised from figure 7 that, both SS and threshold voltageare significantly affected by temperature. However, theimpact of trap charge is negligible for HJHDB FinFETat higher temperature as well. SS is directly related to thetemperature [30], which in turn degrades the SS valuewith increase in temperature. It is seen that thresholdvoltage reduces with the rise in temperature and this isdue to the degradation in OFF current with the rise intemperature as shown in figure 7b.

3.3 Effect of trap level

The impact of trap level on HJHDB and C-FinFETs areshown in figures 8a and 8b, respectively, for both linearand log scale. It is seen that the increase in trap leveldecreases the ON current for both the devices.

The increase in trap level increases the flat bandvoltage and consequently, the drain current is affectedsignificantly in the superthreshold regime. On the otherhand, the effect of trap level is very insignificant forHJHDB FinFET (figure 8a) compared to C-FinFET dueto the presence of high-k box under the drain region.

The effect of trap level on surface potential forHJHDB and C-FinFETs are shown in figures 9a and 9b,respectively. It can be seen that the changes in poten-tial is negligible as the trap level concentration changesin HJHDB FinFET, whereas in C-FinFET, the poten-tial changes by an observable amount. This behaviourin potential for HJHDB FinFET indicates insignificantchanges in drain current as shown in figure 8a.

The impact of trap charge on SS and threshold voltagefor both HJHDB and C-FinFETs are reported in figures10a and 10b, respectively. It is seen from figure 10a,that there is an insignificant change in SS for HJHDBFinFET with trap level. However, SS reduces for C-FinFET with increase in trap density Nf and this is dueto a decrease in drain current in the subthreshold region.It is also observed from figure 10b that, the thresholdvoltage increases with rise in Nf and this is becauseof reduction in drain current with Nf , as observed infigure 8.

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Figure 6. Effect of trap charges for different temperature on potential for (a) HJHDB and (b) C-FinFETs when tbox = 40nm.

Figure 7. Effect of trap charges on (a) SS vs. temperature and (b) threshold voltage vs. temperature for both HJHDB andC-FinFETs when tbox = 40 nm.

Figure 8. Effect of different trap levels on transfer characteristics for (a) HJHDB and (b) C-FinFETs.

Figure 9. Effect of trap level on potential for (a) HJHDB and (b) C-FinFETs.

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Figure 10. Effect of trap level on (a) SS and (b) threshold voltage for both HJHDB and C-FinFETs.

4. Conclusions

In this work, the reliability issues of HJHDB Fin-FET is presented by varying the BOX thickness andtemperature in the presence of fixed trap charge. Theperformance of this device is compared with C-FinFETusing TCAD simulator. By varying BOX thickness,there is no effect of the trap on drain current, SS andthreshold voltage for HJHDB, whereas such electricalparameters of C-FinFET is affected by tarp charge. Ithas been shown that the proposed device has a negligibleimpact of trap charge at high temperature compared toC-FinFET. Furthermore, the effects of trap level on draincurrent and short channel characteristic are observed forboth the devices. It is seen that the electrical parametersof HJHDB FinFET are more immune to trap level vari-ation than C-FinFET. Therefore, HJHDB FinFET is areliable device for wide variations of BOX thickness,temperature, trap level and it can be a promising candi-date for low power applications.

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