synchronous static random access memory (ssram)
DESCRIPTION
Synchronous Static Random Access Memory (SSRAM). Internal Structure of a SSRAM. AREG: Address Register CREG: Control Register INREG: Input Register OUTREG: Output Register ADS_L: Address Select (Low Voltage Assert) GW_L: Global Write (Low Voltage Assert) . - PowerPoint PPT PresentationTRANSCRIPT
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Synchronous Static Random Access Memory (SSRAM)
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Internal Structure of a SSRAMAREG: Address RegisterCREG: Control RegisterINREG: Input RegisterOUTREG: Output Register
ADS_L: Address Select (Low Voltage Assert)
GW_L: Global Write(Low Voltage Assert)
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Burst mode for consecutive access. (No ADDR needs to be sampled after Y)AREG serves as a counter INREG is sampled one clock tick
after the AREG is loaded. Thus, ADS_L has to be inhibited (H in the next rising edge)
Valid for 2 cycles
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Data Output available with 1 cycle delay … But the output is valid for a whole cycle. Thus it mayallow operation at higher clock freq.
Flow-through output
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SRAM Address Block
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Linear vs. Interleaved Burst Modes
Mode Pin is Low
Mode Pin is High
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Big Endian Little Endian000 12 78001 34 56010 56 34011 78 12
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• Conventional SSRAMs share the same pins for both input data and output data.
• Based on the patterns of data-bus and SRAM-array use, there is a turn-around penalty – a clock period must be idle when a read is followed by a write
• The penalty is eliminated in Zero-bus-turn-around (ZBT) SSRAMs
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• An operation (R/W) set up before the rising edge of the clock is performed during the subsequent clock period (since the use of registers as buffers)
• However, in higher frequency of clock rate, it takes less number of cycles to access memory.
Why SSRAM?
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When the clock rate reaches to 75 MHz or higher, pipeline burst mode needs only 1 cycle for second thru fourth access.
When the clock rate reaches to 50 MHz or higher, async mode needs 2 cycles each for second thru fourth access.
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DDR
• Data transferred on both the rising and falling edges of the clock signal.
• Also known as double pumped, dual-pumped, and double transition.
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DDR Write Cycle
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DDR Read Cycle
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How to fully utilize the data bus?
• 2-word-burst mode occupies a single cycle of data bus
• 4-word-burst mode occupies two cycles of data bus
• What, then, will be the frequency of providing Address in each mode?
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DDR2• Like all SDRAM implementations, DDR2 stores data in memory
cells that are activated with the use of a clock signal to synchronize their operation with an external data bus.
• DDR2 I/O buffer transfers data both on the rising and falling edges of the clock signal
• The key difference is that for DDR2 the memory cells are clocked at 1 quarter (rather than half) the rate of the bus.
• This requires a 4-bit-deep prefetch queue, but, without changing the memory cells themselves,
• DDR2 can effectively operate at twice the bus speed of DDR.
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• In 4-bit prefetch architecture, DDR2 SDRAM can read/write 4 times the amount of data as an external bus from/to the memory cell array for every clock, and can be operated 4 times faster than the internal bus operation frequency. • External clock frequency = 2 times of internal bus operation frequency • Double data rate output = 2 times of external clock frequency
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Comparison between DDR2 SDRAM, DDR SDRAM, and SDR SDRAM