institutionen f or systemteknik - diva...

Institutionen for systemteknikDepartment of Electrical Engineering

Examensarbete

Evaluation of FPGA based Test Systems

Examensarbete utfort i datorteknikvid Tekniska hogskolan i Linkoping

av

Marcus Stavstrom

LiTH-ISY-EX--15/4866--SE

Linkoping 2015

Department of Electrical Engineering Linkopings tekniska hogskolaLinkoping University Institutionen for systemteknikS-581 83 Linkoping, Sweden 581 83 Linkoping

Evaluation of FPGA based Test Systems

Examensarbete utfort i datorteknikvid Tekniska hogskolan i Linkoping

av

Marcus Stavstrom

LiTH-ISY-EX--15/4866--SE

Handledare: Ronnie WicklanderOFG, Saab Support and Services

Examinator: Kent PalmkvistISY, Linkopings universitet

Linkoping, June 8, 2015

Presentationsdatum 2015-06-08

Publiceringsdatum (elektronisk version) 2015-06-09

Institution och avdelning Division of Computer Engineering Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden

URL för elektronisk version http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-119094

Publikationens titel Evaluation of FPGA based Test Systems

Författare Marcus Stavström

Sammanfattning This master thesis report covers an investigation of how FPGA-based systems can be used to create customizable measurement instruments for test of electrical equipment. This investigation at Saab Support and Services in Arboga. Testing aircraft electronics regularly is essential in order to maintain flying safety of the JAS 39 Gripen, the aircraft manufactured by Saab. These tests are somewhat exhaustive and require several types of measure instruments in order to verify proper operation of the aircraft electronics. There exist systems that performs this kind of test today. However, Saab wants to see how FPGAs can be used to simplify these tests and make them more configurable. An oscilloscope and a signal generator have been implemented as test example in order to practice this concept. The FPGA design and a PC application has been implemented using hardware from National Instruments and National Instruments design suite LabVIEW.

Nyckelord fpga, test system, oscilloscope, function generator, labview

Språk Svenska x Annat (ange nedan) Engelska

Antal sidor 77

Typ av publikation Licentiatavhandling x Examensarbete C-uppsats D-uppsats Rapport Annat (ange nedan)

ISRN: LiTH-ISY-EX--15/4866--SE

Master Thesis Report

Marcus Stavstrom

June 8, 2015

Abstract

This master thesis report covers an investigation of how FPGA based hardwarecan be used to create customizable measurement instruments, for test of electricalequipment in JAS 39 Gripen. The investigation is done at Saab Support and Servicesin Arboga.

Electrical equipment are gradually replacing functions, which previously have beenobtained by other systems, in safety critical environments. Since the functionsare safety critical, they require regular testing in order to verify proper operation.The aircraft JAS 39 Gripen, which is manufactured and developed by Saab, is anexample of such system. Proper operation of the avionics in it are essential in orderto maintain flying safety.

There already exist systems today that can verify the functionality of electronics inJAS 39 Gripen. However, there are a number of scenarios where those test systemsare somewhat inflexible. More flexible test systems are often desired. This flexibilitycan be obtained by using configurable hardware, suggestively with FPGAs. Thisapproach is investigated in this master thesis.

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Master Thesis Report June 8, 2015

Contents

1 Introduction 11.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Disposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Selecting hardware 32.1 Initial words about FPGA hardware . . . . . . . . . . . . . . . . . . 32.2 Properties to consider . . . . . . . . . . . . . . . . . . . . . . . . . . 32.3 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3.1 Requirements of the oscilloscope . . . . . . . . . . . . . . . 42.3.2 Requirements of the function generator . . . . . . . . . . . . 52.3.3 Summarizing requirements . . . . . . . . . . . . . . . . . . . 6

2.4 Hardware candidates . . . . . . . . . . . . . . . . . . . . . . . . . . 62.4.1 Programming tools . . . . . . . . . . . . . . . . . . . . . . . 6

2.5 Altera DE2-70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.5.1 Base board . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.5.2 A/D and D/A expansion modules . . . . . . . . . . . . . . . 92.5.3 Pricing information . . . . . . . . . . . . . . . . . . . . . . . 102.5.4 Loan during evaluation period . . . . . . . . . . . . . . . . . 102.5.5 Summarize . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 Virtex-6 FPGA ML605 Evaluation Kit . . . . . . . . . . . . . . . . 112.6.1 Base board . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.6.2 A/D and D/A expansion modules . . . . . . . . . . . . . . . 12

2.6.2.1 ADAC250 . . . . . . . . . . . . . . . . . . . . . . 122.6.2.2 FMC110 . . . . . . . . . . . . . . . . . . . . . . . 12

2.6.3 Pricing information . . . . . . . . . . . . . . . . . . . . . . . 132.6.4 Loan during evaluation period . . . . . . . . . . . . . . . . . 132.6.5 Summarize . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7 National Instruments PXIe-7965R . . . . . . . . . . . . . . . . . . . 142.7.1 Base board . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.7.2 A/D and D/A expansion modules . . . . . . . . . . . . . . . 162.7.3 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . 172.7.4 Pricing information . . . . . . . . . . . . . . . . . . . . . . . 172.7.5 Loan during evaluation period . . . . . . . . . . . . . . . . . 182.7.6 Summarize . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.8 Making the choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Description of software 193.1 LabVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.1 Virtual Instruments (VIs) . . . . . . . . . . . . . . . . . . . 193.1.1.1 Comparing Computer VIs and FPGA VIs . . . . 203.1.1.2 How LabVIEW FPGA block diagram code is mapped

into hardware . . . . . . . . . . . . . . . . . . . . 223.1.1.2.1 Single cycle timed loops . . . . . . . . . 223.1.1.2.2 Case structures . . . . . . . . . . . . . . 24

3.1.1.3 Synchronization between computer VIs and FPGAVIs . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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3.1.1.3.1 DMA Channels . . . . . . . . . . . . . . 253.1.1.3.2 Read/Write Controls . . . . . . . . . . . 26

3.1.2 Synthesis using a compile server . . . . . . . . . . . . . . . . 273.1.3 Importing custom VHDL files using CLIP . . . . . . . . . . 27

3.1.3.1 Workaround for hierarchical architectures . . . . 293.2 GHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2.2 Adding support for the Unisim Library . . . . . . . . . . . . 30

3.3 GTKWave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 Theory 334.1 Bilinear transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334.2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334.3 DSP48E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5 Results 415.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1.1 Analog to digital converters . . . . . . . . . . . . . . . . . . 435.1.2 Filter selector . . . . . . . . . . . . . . . . . . . . . . . . . . 435.1.3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.1.3.1 Run-time filter synthesis . . . . . . . . . . . . . . 445.1.4 Trigger selector . . . . . . . . . . . . . . . . . . . . . . . . . 455.1.5 Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2 Implementing biquad filter with DSP48E components . . . . . . . . 455.3 Mapping filter poles to biquad section . . . . . . . . . . . . . . . . . 47

5.3.0.1 Biquad stage . . . . . . . . . . . . . . . . . . . . . 495.4 Preventing incorrect slope detection . . . . . . . . . . . . . . . . . . 505.5 Multiple trigger conditions . . . . . . . . . . . . . . . . . . . . . . . 515.6 Variable waveform window span . . . . . . . . . . . . . . . . . . . . 53

5.6.1 On-board DRAM . . . . . . . . . . . . . . . . . . . . . . . . 555.6.1.1 Addressing . . . . . . . . . . . . . . . . . . . . . . 55

5.6.2 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565.6.3 VRMS unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 575.6.4 VPP unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575.6.5 Oscilloscope states . . . . . . . . . . . . . . . . . . . . . . . 57

5.6.5.1 Init state . . . . . . . . . . . . . . . . . . . . . . . 585.6.5.2 Idle state . . . . . . . . . . . . . . . . . . . . . . . 585.6.5.3 Write block state . . . . . . . . . . . . . . . . . . 59

5.6.5.3.1 Continuously write state . . . . . . . . . 595.6.5.3.2 Finishing write state . . . . . . . . . . . 59

5.6.5.4 Read block state . . . . . . . . . . . . . . . . . . 605.7 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6 Conclusions 636.1 Possible improvements . . . . . . . . . . . . . . . . . . . . . . . . . 64

References 65

A CLIP XML file example 67

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B Trigger unit 71

C Hysteresis unit 73

D VRMS unit 75

E VPP unit 77

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List of Figures

1 The main principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 LabVIEW program example. . . . . . . . . . . . . . . . . . . . . . . 73 Illustration of the code generation process. . . . . . . . . . . . . . . 84 Picture of the DE2-70 board. . . . . . . . . . . . . . . . . . . . . . . 95 Picture of the Highspeed AD/DA Card . . . . . . . . . . . . . . . . 106 Picture of ML605 evaluation board . . . . . . . . . . . . . . . . . . 117 Picture of the ADAC250 expansion card . . . . . . . . . . . . . . . 128 Picture of the FMC110 expansion card . . . . . . . . . . . . . . . . 139 Picture of the PXIe-7965R card. . . . . . . . . . . . . . . . . . . . . 1510 Picture of the NI PXIe-1062Q PXI Express chassis. . . . . . . . . . 1511 Picture of a PXI to PCI converter inserted into a PXI Express chassis. 1612 Picture of the Baseband Transceiver module. . . . . . . . . . . . . . 1713 Illustration of communication between host computer VI and FPGA

VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2114 Creating a register using a shift register. . . . . . . . . . . . . . . . 2315 Creating a register using a feedback node. . . . . . . . . . . . . . . 2316 Result of feedback node or shift register. . . . . . . . . . . . . . . . 2417 Creating a case structure. . . . . . . . . . . . . . . . . . . . . . . . . 2418 Case structure translated to hardware. . . . . . . . . . . . . . . . . 2519 Creating a FPGA FIFO Write Invoke Method. . . . . . . . . . . . . 2620 Creating a DMA FIFO Read procedure. . . . . . . . . . . . . . . . 2621 Communication using Read/Write Controls. . . . . . . . . . . . . . 2622 Compilation server setup. . . . . . . . . . . . . . . . . . . . . . . . . 2723 Screenshot of GTKWave . . . . . . . . . . . . . . . . . . . . . . . . 3224 FIR filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3425 IIR filter of order two. . . . . . . . . . . . . . . . . . . . . . . . . . . 3526 Simplified block diagram of a DSP48E block. . . . . . . . . . . . . . 4027 Screenshot of the user interface for the oscilloscope and the function

generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4128 Overview of the oscilloscope architecture. . . . . . . . . . . . . . . . 4229 Interface of the filter selector. . . . . . . . . . . . . . . . . . . . . . 4330 Block diagram of the filter architecture. . . . . . . . . . . . . . . . . 4431 Direct form II structure. . . . . . . . . . . . . . . . . . . . . . . . . 4632 A transformed direct form II biquad filter. . . . . . . . . . . . . . . 4633 A transformed direct form II biquad filter, identifying DSP48Es. . . 4734 Mapping of filter poles between the time-continuous butterworth fil-

ter of order 2 and the time discrete filter. . . . . . . . . . . . . . . . 4835 Mapping of filter poles between the time-continuous butterworth fil-



ter of order 8 and the time discrete filter. . . . . . . . . . . . . . . . 4938 Final implementation of biquad filter, using DSP48Es. . . . . . . . . 5039 Figure illustrating the a detection error when monitoring noisy signals. 5140 Figure illustrating the hysteresis approach. . . . . . . . . . . . . . . 5141 A situation with two trigger conditions, which will not trig. . . . . . 52

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42 A situation with two trigger conditions, which will trig. . . . . . . . 5343 Offset and waveform window zoom factor. . . . . . . . . . . . . . . 5444 Waveform window placement when the offset is zero. . . . . . . . . 5445 DRAM addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5646 The different FPGA states. . . . . . . . . . . . . . . . . . . . . . . . 5847 The states used within the Write block state. . . . . . . . . . . . . . 5948 The states used within the Read block state. . . . . . . . . . . . . . 60

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Abbreviations

A/D Analog to DigitalALU Arithmetic Logic UnitAPI Application Programming InterfaceCLB Configurable Logic BlockCLIP Component Level Intellectual PropertyCPU Central Processing UnitD/A Digital to AnalogDDR Double Data RateDMA Direct Memory AccessDRAM Dynamic Random Access MemoryDSP Digital Signal ProcessingFFT Fast Fourier TransformFIR Finite Impulse ResponseFMC FPGA Mezzanine CardFPGA Field-Programmable Gate ArrayGHDL G Hardware Design LanguageGIMP GNU Image Manipulation ProgramGPIO General Purpose Input and OutputGTK GIMP ToolKitGTKWave GTK WaveHDL Hardware Description LanguageIEEE Institute of Electrical and Electronics EngineersIIR Infinite Impulse ResponseIO Input and OutputJAS Jakt Attack SpaningLabVIEW Laboratory Virtual Instrumentation Engineering WorkbenchLaTeX Lamport TeXLCD Liquid Crystal DisplayLUT LookUp TableMRO Maintenance Repair and OverhaulOEM Original Equipment ManufacturerPC Personal ComputerPCI Peripheral Component InterconnectPXI PCI eXtensions for INstrumentationRAM Random Access MemoryRS232 Recommended Standard 232SD-RAM Synchronous Dynamic Random Access MemoryVDC Voltage Direct CurrentVHDL VHSIC Hardware Description LanguageVHSIC Very High Speed Integrated CircuitVI Virtual InstrumentVPP Voltage Peak to PeakVRMS Voltage Root Mean SquareXML eXtensible Markup Language

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1 Introduction

This master thesis has been performed at Saab Support and Services, a businessunit within Saab AB.

1.1 Background

Electrical equipment are gradually replacing functions, which previously have beenobtained by other systems, in safety critical environments. Since the functionsare safety critical, they require regular testing in order to verify proper operation.The aircraft JAS 39 Gripen, which is manufactured and developed by Saab, is anexample of such system. Proper operation of the avionics in it are essential in orderto maintain the flying safety.

There already exist systems today that can verify the functionality of electronics inJAS 39 Gripen. However, there are a number of scenarios where those test systemsare somewhat inflexible. More flexible test systems are often desired.

1.2 Objective

The objective of this master thesis is to investigate how FPGAs can be used to createmore configurable test equipment for testing aircraft avionics for the multirole fighterJAS 39 Gripen.

Test systems usually consist of several types of measurement instruments. One typethat typically require more flexible measurements are oscilloscopes, where one prop-erty that is particulary inflexible is trigger conditions. Usually it is only possible toset one voltage level with a desired slope as a trigger condition. However, sometimesmore complex trigger patterns are needed in order to be able to perform a measure-ment. Another property that is inflexible is input filters to oscilloscopes. Inputsignals often contain frequency components that make it hard to perform certainmeasurements. Traditional oscilloscopes usually contain some kind of static filtercomponent such as HF-reject (High Frequency reject), which removes high frequencysignal components at a static cut-off frequency. However, sometimes it is needed tobe able to specify custom filter properties.

Therefore, an oscilloscope should be designed and implemented in FPGA hardwarein this master thesis. The oscilloscope should be able to specify more complex triggerpatterns than a traditional off-the-shelf oscilloscopes. It should also be possible toconnect a filter to the input channels in order to removed undesireble frequencycomponents. It should also be able to perform a number of simple measurements,such as voltage peak-to-peak and voltage RMS.

A simple function generator should also be designed in order to show how test systemoutput can be obtained using FPGAs.

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There are several aspects that makes this master thesis interesting and meaningful:

• See how FPGAs can be used for testing purposes.

• Reduce size of the test equipment.

• Be able to run various instruments on the same hardware, an approach thatsaves money.

• Make Saab less dependent of various instrument manufacturers.

1.3 Disposition

Speaking generally, the report is divided into five parts:

• Selecting hardware

Describes a short investigation that was performed in the beginning of thismaster thesis. The inital requirements are specified and a short comparisonof different FPGA hardware is performed. Hardware from Altera, Xilinx andNational Instruments are compared.

• Description of software

Intended as a manual. Describes the software that have been used in thisproject and how to use it. LabVIEW, GHDL and GTKWave are mentionedhere.

• Theory

Theory that are used to obtain the results. This section mostly consist oftime-continous and time-discrete filter theory. A short description of a FPGADSP component is also given here.

• Results

A technical specification of the work that has been done. This section alsocovers some parts of the way of obtaining the technical solutions.

• Conclusions

A chapter containing my personal reflections.

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2 Selecting hardware

2.1 Initial words about FPGA hardware

An FPGA is an integrated circuit designed to be configured by the customer or de-signer after manufacturing, hence ”field-programmable” in its name. Configurationof the FPGA is generally specified by using a hardware description language. FP-GAs contain a large amount of programmable logic, called ”logic blocks”, which canimplement any logic function (such as AND, NOR and XOR). These logic blocks areattached to a large interconnect network, in which paths between the logic blockscan be created to obtain more complex logic functions. Modern FPGAs consist over100’000 of these logic blocks [2].

FPGAs are good for digital signal processing. However, aircraft electronics consist ofmany analog signals which requires analog signal measurements. Thus, it is requiredthat the FPGA is combined with hardware that transforms the measured signalsfrom an analog domain to a digital domain and vice versa. That task is suggestivelyperformed with some type of A/D Converter and D/A Converter. The principle isillustrated in figure 1.

FPGA

(digitalsignal processing)

A/D

D/A

Analog signals

10101011...

...10101011

Figure 1: The main principle.

2.2 Properties to consider

This section covers the requirements of the test system which should be implementedin this master thesis.

There is a large number of FPGAs that is available on the market. There are severalproperties to consider when choosing FPGA-hardware:

• Clock frequency

• Size of FPGA (in terms of number of logic blocks)

• DSP (Digital Signal Processing) operation capabilities

• A/D Converter and D/A Converter sampling frequency

• A/D Converter and D/A Converter voltage swing

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• Built-in memory

• Expansion possibilities

There are also properties to consider that aren’t related with the hardware perfor-mance:

• Documentation

• Software tools

• Cost

• Possibility to loan hardware during evaluation

2.3 Requirements

Section 2.3.1, 2.3.2 and 2.3.3 are describing initial requirements that have been foundnecessary for this thesis work.

2.3.1 Requirements of the oscilloscope

The oscilloscope shall:

• Have at least two analog input channels where data is sampled.

• Have a sample frequency of at least 1 MS/s with a resolution of 8 bits.

• Have a memory that is sufficiently large in order to save samples for at leastone millisecond.

• Have a front panel where the waveform window and the functionality of theoscilloscope is controlled.

• Have an input filter with a maximal order of eight. It shall be possible to selectthe filter order dynamically from the oscilloscope front panel. The input filtershould be of the type low pass. The cut-off frequency shall be specifiable inreal time by the user.

• Have at least three trigger conditions that can be specified separately. Thetime between the events that the trigger conditions specify shall also be speci-fiable.

• Be able to measure VPPof at least one channel.

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• Be able to measure VRMS of at least one channel.

• Have at least two cursors which the user can control. The amplitude and timedifference between the cursors shall be displayed in the front panel.

Optionally, if time is available in the end of the project, the oscilloscope shall:

• Have a programmable interface (API) where the functionality of the oscillo-scope is controlled.

• Be able to measure VRMS and VPP from both channels.

• Be able to specify other type of filters than low-pass.

Translating the functional requirements above gives the following hardware require-ments, which means that the oscilloscope shall:

• Be implemented on a FPGA connected to at least two A/D converters.

• Have an on-board DRAM that has sufficient space to store waveform samplesfor at least one millisecond.

• Be connected to some equipment that can present the front panel, suggestivelya personal computer.

• Have a FPGA with at least 50 embedded multipliers:

– 20 embedded multipliers for the input filter, assuming that a cascadedbiquad structure is used (five embedded multipliers for each biquad).

– 3 embedded multipliers for the VRMS unit.

– 27 embedded multipliers for additional functionality.

2.3.2 Requirements of the function generator

The function generator shall:

• Have a front panel where the the functionality of the function generator iscontrolled.

• Have a programmable interface (API) where the functionality of the functiongenerator is controlled.

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• Have at least one analog output channel.

• Be able to output sine wave, square wave and triangle wave.

Translating the functional requirements above gives the following hardware require-ments, which means that the function generator shall:

• Be implemented on a FPGA connected to an A/D converter.

• Be connected to some equipment that can present the front panel, suggestivelya personal computer.

2.3.3 Summarizing requirements

As an initial approach, the focus is to get one data channel working. If there is timeavailable in the end of this master thesis, another data channel can be implemented.Two data channels gives some interesting additional capability, such as possibilityto measure phase shift and output two identical signals with a given phase shift.

It is not important to achieve good performance of the application that should bebuilt. The focus of this master thesis is to investigate how appropriate FPGA basedinstruments are for test of aircraft electronics, rather than how appropriate they areto achieve high performance.

All requirements specified in section 2.3.1 and 2.3.2 are used during the process thatis performed when choosing hardware. This process is described in section 2.4.

2.4 Hardware candidates

After a short period of exhaustive research on the web, three proper candidateshave been found that satisfies the requirements given in section 2.3. Each candidatediffers from each other in terms of price and performance and are described in thefollowing sections. There are three candidates from three diffrent manufacturers:Altera, Xilinx and National Instruments.

2.4.1 Programming tools

The software that often is bundled with the Altera bases FPGA boards is QuartusII. This tool is produced by Altera and is used for analysis and synthesis of HDLdesigns. The programming language that is used is VHDL.

The software tool that often is bundled with Xilinx based FPGA boards is the ISE.This is a software tool produced by Xilinx and is used for analysis and synthesis ofHDL designs. The programming language that is used is VHDL.

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LabVIEW is a platform from National Instruments that provides a developmentenvironment for graphical programming. LabVIEW is commonly used for dataacquisition, instrument control and industrial automation and is available for severaloperating systems.

The programming paradigm of LabVIEW is dataflow programming. The behaviorof the program is determined by the structure of the graphical block diagram onwhich the programmer connects different function nodes by drawing wires. Eachblock can only execute if there is available data on all its inputs. For example, if ablock has two inputs (A and B) and data arrives at input A at a certain time, theblock doesn’t executes until valid data arrives on port B.

There exists a large amount of hardware, mainly used for data acquisition, that arecompatible with LabVIEW. This is one big benefit with LabVIEW since it has ex-tensive support for instrumentation hardware. Many different types of instrumentsand buses are available for inclusion in the LabVIEW programs. Instruments, busesor other hardware are represented as graphical nodes in these block diagrams. Asample of a graphical program is shown in figure 2 .

Figure 2: LabVIEW program example [14].

LabVIEW code is mainly targeted for personal computers. However, LabVIEWblock diagrams can be used for other targets as well. One module of LabVIEW,which can be used in this project, is a module that makes it possible to synthesizeLabVIEW block diagrams and implement them as FPGA hardware. That moduleis called the LabVIEW FPGA module. Under the hood, the module uses codegeneration techniques to generate VHDL code, which in its turn is synthesized bytools that are provided by the FPGA manufacturer. The code generation processfor LabVIEW FPGA is illustrated in figure 3.

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Figure 3: Illustration of the code generation process used by the LabVIEWFPGA module.

2.5 Altera DE2-70

2.5.1 Base board

The Altera DE2-70 development board is based on a Cyclone II EP2C70 FPGA.This FPGA is marketed as a low cost FPGA, but offers some interesting capabilities[4]:

• 68,416 logic cells

• 68,416 programmable Flip-Flops

• 1152 kBit of embedded RAM (MK4 RAM)

• 150 embedded 18x18 bit multipliers, for DSP applications

• External memory interfaces, with data rates up to 668 Mbps.

Besides the FPGA, the board itself has a number of components [3]:

• Two 32 Megabyte SD-RAM - for storing of A/D Converter samples.

• 10/100 Ethernet connector - for computer connection.

• RS232 interface - for computer connection.

• 16x2 LCD display - for debugging purposes.

• Two GPIO expansion connectors.

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Figure 4: Picture of the DE2-70 board. Notice the general purpose expansionconnectors on the right hand side of the board [3].

A picture of the DE2-70 board is shown in figure 4. This board offers a rich setof features making it suitable for a variety of projects. However, this card doesn’tinclude any A/D or D/A converters, so the expansion possibilities of this card hasto be used in order to make it satisfy the requirements.

2.5.2 A/D and D/A expansion modules

These is one module, offered by Terasic, that fits into the GPIO sites of the DE2-70development board. That module is called the Highspeed AD/DA Card, and is anexpansion card that contains two A/D converters and two D/A converters with thefollowing specifications [5]:

A/D converters:

• Resolution: 14 bits

• Sample rate: 65 MS/s

D/A converters:


• Update rate: Up to 125 MS/s

A picture of the Highspeed AD/DA Card is shown in figure 5.

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Figure 5: Picture of the Highspeed AD/DA Card [5].

2.5.3 Pricing information

Using the DE2-70 board and a High-speed AD/DA daughter board provides a lowcost solution with the actual pricing information of today:

• DE2-70 board: $599

• High-speed AD/DA daughter board: $219

This gives a total price of $818.

2.5.4 Loan during evaluation period

A discussion with Altera has been done and they were not interested in any loanduring this thesis work.

2.5.5 Summarize

This kit is one of the cheapest on the market and well worth its money. The cardprecisely satisfies all requirements given in section 2.3, but does not provide anysignificant additional capacity for future expansion. Someday it may be interestingto implement a spectrum analyzer, which requires a FFT to operate. FFTs aredemanding and requires hardware, which is a constraint which this card probablywon’t fulfill. It has capacity for the problems that should be solved in this masterthesis but probably not more.

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2.6 Virtex-6 FPGA ML605 Evaluation Kit

2.6.1 Base board

The Virtex-6 FPGA ML605 Evaluation Kit is based on a XC6VLX240T FPGA,which is a full feature high end FPGA with the following interesting capabilities [7]:


• 301,440 CLB Flip-Flops

• 14,976 KBit of embedded RAM (block ram)

• 768 embedded 25x18 bit multipliers (in DSP blocks)

• 2 blocks for PCI Express communication

The board itself also has some interesting components [6]:

• 512MB DDR 3 RAM - for storing of A/D Converter samples.

• 10/100/1000 Ethernet connection - for computer connection

• PCI Express x8 Edge connector - for computer connection.

• 16x2 LCD display - for debugging purposes.

• Two FMC expansion connectors.

Figure 6: Picture of ML605 evaluation board [6].

A picture of the ML605 development board is shown in figure 6. The board offersa rich set of features and significantly better performance than the DE2-70 board,making it suitable for more sophisticated projects. This board does not provide anyD/A or A/D converters, so an expansion module with A/D and D/A converters hasto be installed at the FMC sites on the board.

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There exist two manufacturers that develops expansion modules for FMC sites. Twosuch cards has been found; the ADAC250 and the FMC110.

2.6.2.1 ADAC250

The ADAC250 expansion board is developed and manufactured by Lyrtech Inc, acompany with main site in Canada. The card has two A/D and two D/A converters,with the following specifications [8]:

A/D converters:



• Voltage swing: ± 1 V

D/A converters:


• Update rate: 1 GS/s


Figure 7: Picture of the ADAC250 expansion card [8].

A picture of the ADAC250 is shown in figure 7.

2.6.2.2 FMC110

This card is manufactured by 4DSP Incorporated, a company with main site inReno, Nevada, United States. Like the ADAC250, it also has two A/D and twoD/A converters with the following specifications [9]:

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A/D converters:


• Sample rate: 1 GS/s


D/A converters:


• Update rate: 1 GS/s


Figure 8: Picture of the FMC110 expansion card [9].

A picture of the card is shown in figure 8.


The following pricing information has been found for this card:

• ML605 Evaluation Kit: $1995

• ADAC250 expansion card: $2995

This gives a total price of $4990 for a complete solution with base board andADAC250 expansion card. Unfortunately no pricing information was found for theFMC110.


The Xilinx office in Sweden has been contacted and they were not interested in anyloan during this thesis work.

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2.6.5 Summarize

The Virtex-6 FPGA ML605 Evaluation Kit is considerably more expensive thanthe DE2-70 board, but offers a FPGA device with significantly better performance.This card offers a market leading FPGA architecture that provides a lot of capacityfor additional improvements that are done after this thesis work.

Regarding the price it may appear somewhat expensive, but in return offers marketleading performance.

2.7 National Instruments PXIe-7965R

2.7.1 Base board

The National Instruments PXIe-7965R is based on a Virtex-5 SX95T FPGA. TheFPGA has the following specifications [10]:


• 58,880 CLB Flip-Flops

• 4752 kBit of embedded RAM (block ram)

• 640 embedded 25x18 bit multipliers (in DSP blocks)

• 1 PCI Express Interface

The board itself has the following interesting capabilities [1]:

• 512 MB DDR2 DRAM - for storing of A/D converter samples

• 16 DMA channels - for computer interface

• PXI Express connector - for computer interface

• FlexRIO expansion connector - for connection of adapter modules

A picture of the PXIe-7965R is shown in figure 9.

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Figure 9: Picture of the PXIe-7965R card [1].

The PXIe-7965R cannot be utilized unless it is inserted into a PXI Express chassis. APXI Express chassis is an empty box with a common backplane based on a modulardesign principle, into which a number of PXI Express cards can be inserted. Thereexist several PXI Express chassis of this type, where a chassis named NI PXIe-1062Qwhich is interesting for this thesis work. This PXI Express chassis has eight PXIExpress slots, making it possible to connect up to eight PXI Express cards [11].

The modular design offers capability to connect other hardware into the same PXIExpress chassis, making it possible to combine the cards inserted in the chassis withthe software bundled by National Instruments. A picture of the chassis is shown infigure 10.

Figure 10: Picture of the NI PXIe-1062Q PXI Express chassis [15].

In order for a personal computer to communicate with the FPGA board assembledin the PXI Express chassis, a PXI Express to PCI Express converter system mustbe installed. Such a converter consist of a PXI Express card (inserted into the PXIexpress chassis), a PCI express card (inserted into the PC) and either a copper orfiber optic cable. A copper cable solution, namely the PXIe-PCIe8370, is suitablefor this thesis work. A picture of that solution is shown in figure 11.

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Figure 11: Picture of a PXI to PCI converter inserted into a PXI Express chassis[16]

The PXIe-7965R (the FPGA card) is a so called FlexRIO card. That means ithas an expansion interface on its front panel, making it possible to connect oneof the FlexRIO adapter modules that are provided by National Instruments. Thisexpansion possibility has to be used in this thesis work, since the PXIe-7965R doesn’tinclude any A/D- or D/A-converters.


There exists a FlexRIO module named the NI 5781 Baseband Transceiver module,which is interesting for this thesis work. The module has two A/D converters andtwo D/A converters with the following specifications [12]:

A/D converters:




D/A converters:


• Update rate: 100 MS/s


A picture of the Baseband Transceiver module is shown in figure 12.

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Figure 12: Picture of the Baseband Transceiver module.

2.7.3 Software tools

The software tool that is provided with the solution offered by National Instrumentsis LabVIEW. LabVIEW has an entirely different approach than Xilinx and Altera,particularly regarding the graphical programming that can be used to program theFPGA. Moreover, it has some other interesting capabilities:

• Easy creation of user interface panels with the library provided by LabVIEW.

• Several CLIP nodes available.

• Setup of high speed DMA channels without any particular effort.

• If needed, ability to import VHDL code into LabVIEW block diagrams.

• A more intuitive approach of modeling hardware for users that don’t have anyknowledge in HDL.


The pricing information for the entire package is the following:

• FPGA board (PXIe-7965R): $8499

• PXI Express chassis (PXIe-1062Q): $2699

• PXI Express to PCI Express converter (PXIe-PCIe8370): $2099

• Baseband Transceiver module (NI 5781): $2999

This gives a total price of $16296.

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Discussions with National Instruments has been done and they could afford a freeloan of the hardware mentioned in section 2.7.4, for an evaluation period of 10 weeks.

2.7.6 Summarize

The solution provided by National Instruments requires finances, but in return ithas some interesting benefits.

Particularly the user interface panels which can be created with LabVIEW saves alot of time. It also targets a wider span of people, so they can read, understandand make modifications without any knowledge in traditional hardware descriptionlanguages.

2.8 Making the choice

The solution that is provided by National Instruments has been selected to be usedduring this Master Thesis. That decision is based on the following facts:

• Good hardware performance, with capacity for future extensions.

• Libraries for creation of user interface panels. This provides faster develop-ment of user interface panels, bringing much focus of the project from the”front-end” (interface) to the ”back-end” (FPGA development).

• Easy setup of communication between FPGA and host computer.

• Intuitive programming language which can involve more people to extend theproject after this master thesis.

• Free loan during evaluation period. This is a clever way of enticing customersand establish relations to a company is to provide free (or at least affordable)samples of a product during a short evaluation period. Neither Altera or Xil-inx were interested in that.

• Extended personal experience.

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3 Description of software

This section discusses the software tools that have been used in this master thesis.A brief description of them are given and some words about how they are used.

3.1 LabVIEW

The software that mainly has been used during this project is LabVIEW. The fol-lowing sections describes some functions and features of LabVIEW more in detail.

3.1.1 Virtual Instruments (VIs)

LabVIEW programs and subroutines are called Virtual Instruments (VIs). EveryVI consist of three major components:

• Block diagram

Contains the ”program code”, which controls the behavior of the LabVIEWprogram. This is the ”back-end” of the LabVIEW program.

• Front panel

Contains the interface that is presented to the user. There exists a largelibrary of user interaction components such as buttons, slides and waveformwindows which can be added to the front panel. This is the ”front-end” of theLabVIEW program.

Communication with the block diagram is done by using so called controlsand indicators. Controls send data from the front panel to the block diagram,and indicators sends data from the block diagram to the front panel.

• Connector panel

A panel that is used to specify the output and inputs of the block diagram.Usage of the connector panel is only applicable for VIs that are used as sub-routines.

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3.1.1.1 Comparing Computer VIs and FPGA VIs

There are two different types of VIs that can be created inside an environment thathas the LabVIEW FPGA module installed:

• VIs for execution on host computer

• VIs that are implemented in FPGA hardware

VIs that are executed on the host computer has a larger library of components thatcan be used than the VIs that are aimed for the FPGA hardware. For example, acomponent that is available for the host computer VIs are floating point numbers(such as double precision float). This component is not available for FPGA VIs.

As mentioned in section 3.1.1, all VIs consist of three components. That applies toboth host computer VIs and FPGA target VIs. That means that there are a frontpanel for the FPGA target VI as well, which can present all signals in the FPGAhardware. Considering that, it might sound sufficient to only use FPGA VIs.

However, there are several advantages of having one VI implemented in FPGAhardware and one VI running on the host computer. Some data processing is moreefficient on the FPGA and some other data processing is more efficient to implementon a host computer. For example, tasks that are CPU-intensive are advantageouslyimplemented in FPGA hardware (via FPGA target VIs) and tasks that are not per-formed so often are advantageously in software (via host computer VIs). Moreover,as mentioned above, the computer VIs have a larger library of components that canbe used to solve various tasks that don’t require the performance of a FPGA. Theapproach of combining FPGA VIs and host computer VIs is illustrated in figure 13.

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Front panel

(not used)

Block diagram

(digital signalprocessing)

FPGA VI(implemented as FPGA hardware)

Front panel

(contains buttons, indicators and

waveform windows)

Block diagram

(handles user interfaceand communication to

and from FPGA VI)

Host computer VI (running on PC)

Communications betweenhost computer VI and FPGA VI

Figure 13: Illustration of communication between host computer VI and FPGAVI.

Synchronization between the FPGA target VI and the host computer VI is neededin order to use the approach that is the paragraph above. Particularly, the followingdata streams are common when FPGA VIs and host computer VIs are communi-cating:

• Data streams from FPGA hardware to host computer:

– Measurement data (requires high throughput)

– Status data (requires only low throughput)

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• Data streams from host computer to FPGA hardware:

– Command data (requires only low throughput)

Techniques for synchronization between host computer VIs and FPGA VIs are de-scribed in section 3.1.1.3.

3.1.1.2 How LabVIEW FPGA block diagram code is mapped into hardware

Block diagrams that are used for FPGA targets have slightly different semanticsof diagram structure than traditional block diagrams. A few common LabVIEWconstructs are described here.

3.1.1.2.1 Single cycle timed loops

Creating loops in the LabVIEW block diagrams are required in order to achievelogic that are continuously executed. If logic components are placed directly to thebackground of the block diagram, they will only execute once. There are severaltypes of loops available in the LabVIEW FPGA module. The most appropriate onefor modeling hardware is the single cycle timed loop.

A single cycle timed loop is represented as a rectangle which can be adjusted in sizein order to hold more or less components in it. Single cycle timed loops does whatthe name implies, it performs all actions defined by the blocks inside it within thetime limit of a single clock cycle. That means that basically every component thatis placed inside a single cycle timed loop are synthesized to combinatorial logic. Thefrequency f that is specified to the loop specifies the maximum allowed time Tcriticalfor the critical path of the combinatorial logic, according to this simple relation:

Tcritical =1

f(1)

Registers are essential in order to create register transfer logic. Registers can becreated in two ways using the LabVIEW FPGA module:

• Using so called shift registers (not to be confused with traditional shift regis-ters)

• Using feedback nodes

A shift register is placed as two parts in the block diagram, one at the left sideborder and one the right side border of the single cycle timed loop. The part onthe left side represents the register output and the right side represents the registerinput. This approach is illustrated in a screenshot given in figure 14. An initial

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value of zero has been set to the register in this screenshot. The combinatorial partconsist of an incrementing component, which will increment the value of the registerby one at every clock cycle.

Register input

Register output

Initial value

Combinatorial logic

Figure 14: Creating a register using a shift register.

The same functional behavior can be achieved by using feedback nodes. Feedbacknodes only consist of one part and are placed inside the border of the single cycletimed loop, in opposite to the shift registers that are placed on the left side borderand the right side border of the block diagram. The same functional behavior as infigure 14 is illustrated with feedback nodes in figure 15. In this example, the registeris initialized with a value of zero as well.

Register inputRegister output

Initial value

Combinatorial logic

Figure 15: Creating a register using a feedback node.

Shift registers are suggestively used for data that are used in larger parts of theblock diagram. The input of the register often is dependent of the output of theregister, which requires a long wire routed between the input and the output.

It is more appropriate to use feedback nodes if the value of the register only shouldbe used in local areas of the single cycle timed loop. In fact they are even required

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in VIs that are used as sub-routines, which are included inside single cycle timedloops. Shift registers are not suitable here since it would require a single cycle timedloop in the sub-routine. That would mean that a single cycle timed loop will beincluded inside another single cycle timed loop and a compilation error will occur.

The diagrams in figure 14 and figure 15 will both result in the principal hardwaregiven in figure 16:

Increment D Q

100 MHz

Figure 16: Result of feedback node or shift register.

3.1.1.2.2 Case structures

The case structure is a conditional structure component which perform differentactions depending on whether a programmer-specified variable evaluates to a certainvalue associated with a certain case. The case structure is represented as a rectanglewhich can be adjusted in size in order to hold more or less components in it. Thecase structure can evaluate on an arbitrary number of cases. The most common isto have two cases, which depends on a variable that evaluates to either true or false.

An screenshot of a case structure is given in figure 17. In this example a variablenamed ”Control” is incremented if the boolean variable ”Increment” evaluates trueor decremented if it evaluate false.

Figure 17: Creating a case structure.

The diagram given in figure 17 has the same functionality as the hardware describedin figure 18.

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Increment?

Inc

Dec

Control Indicator

1

0

Figure 18: Case structure translated to hardware.

3.1.1.3 Synchronization between computer VIs and FPGA VIs

There are two ways of sending data between the host computer and the FPGAhardware:

• DMA channels

• Read/Write Controls

3.1.1.3.1 DMA Channels

LabVIEW provides an interface that makes it fairly uncomplicated to setup DMAchannels for data streaming between the FPGA hardware and the software runningon the host computer. DMA channels can be created to operate in both directions,FPGA to host computer or host computer to FPGA. This is a property that onlycan be set before compile-time. The direction of the DMA channel can’t be changedduring run-time (after synthesis).

The advantage of using DMA channels is the high data throughput rate that itcan obtain. According to National Instruments, the DMA channels of the hardwarewhich have been used during this project (NI PXIe-7965R) can obtain a data stream-ing speed of 800 MB/s [1]. That makes them suitable for streaming of measurementdata.

However, there are only a limited number of DMA channels that can be setup fordata communication, which makes them unsuitable for status data from the FPGAand command data to the FPGA. These applications are better implemented usingRead/Write Controls, which are described in section 3.1.1.3.2.

Creating DMA channels is performed by first defining av DMA channel in the projectexplorer of a LabVIEW project. This DMA channel can then be invoked by placinginvoke methods in the FPGA VIs and the host computer VIs. Figure 19 shows aDMA invoke method that is implemented on a FPGA VI, which is used in order to

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write to a DMA channel (DMA TEST FIFO in the figure). Figure 20 shows DMAinvoke methods implemented on a host computer VI that are needed to read froma DMA channel.

Figure 19: Creating a FPGA FIFO Write Invoke Method.

Figure 20: Creating a DMA FIFO Read procedure.

3.1.1.3.2 Read/Write Controls

For data communication that don’t require the transfer rates of DMA channels, likestatus conditions and such, Read/Write Controls are more suitable.

Read/Write controls don’t require any particular setup on the FPGA side of theLabVIEW project. In order to write to or read from a variable on the FPGA, aRead/Write control is placed in the block diagram of the host computer VI, as shownin figure 21. In this example, a variable named ”state” is continuously monitored.

Figure 21: Communication using Read/Write Controls.

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3.1.2 Synthesis using a compile server

The synthesis of LabVIEW FPGA projects is a CPU intensive and time consumingprocess. Synthesis times up to 90 minutes have been experienced during this project,when synthesizing the LabVIEW FPGA design on the client computer. However,the synthesis times can be minimized by setting up a separate compile server onanother computer. LabVIEW has a separate application that has support for suchan approach, namely the LabVIEW FPGA Compile Server.

In order to use the approach mentioned in the paragraph above, LabVIEW andLabVIEW FPGA have to be installed on both the client computer and the compileserver. The compile server doesn’t require any particular setup, more than startingthe LabVIEW FPGA Compile Server application on it. Eventual firewalls have tobe disabled as well.

The client computer requires an IP-adress to the compile server, which is specifiedunder the ”FPGA Module Options” in LabVIEW.

The second Ethernet interface of the client computer used in this master thesis hasbeen used to create a direct connection to the compilation server. The setup shownin figure 22. This setup almost halved the synthesis times for the projects, comparedto the synthesis times on the client computer.

Figure 22: Compilation server setup.

3.1.3 Importing custom VHDL files using CLIP

LabVIEW has a component named CLIP (Component-Level Intellectual Property),which makes it possible to import VHDL files into LabVIEW and use these as blocksin the LabVIEW block diagrams. This is a fairly complicated progress and requiressome additional work than just ”importing” a VHDL file into the project. Theprocess is divided in five major stages:

1. First of all, the entity port of the imported VHDL file has to be adapted tothe data types that are compatible with LabVIEW. There are a lot of datatypes that are compatible, where the interesting ones for FPGA projects ismentioned here:

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• Boolean (corresponds to std logic in VHDL)

• U8 (corresponds to std logic vector(7 downto 0) in VHDL)




• I8 (corresponds to std logic vector(7 downto 0) in VHDL)




This means that entity signals with other word length than the ones men-tioned above have to be extended to a longer word length in the entity andthen shortened in the VHDL code. For example, if an entity signal initiallyhas a word length of 14 bits, it has to be converted to 16 bits in the entity.The rest of the VHDL code probably expects the word length to be 14 bits, soa word length wrapper has to be implemented in order to avoid compilationerrors. That is done by converting the 16 bit entity signal to a 14 bit signalbefore it is passed to the rest of the VHDL code.

2. Secondly, a XML file has to be written. This is actually the file that is usedby CLIP when transforming the VHDL entity into a LabVIEW block.

There are several keywords that needs to be taken care of when writing thisXML file. It is recommended for the reader of this document to study theVHDL entity and the XML file examples in appendix A.

There are some important aspects to be taken care of:

• Two signal lists are always declared in the file using the <SignalList>tag. The first signal list is for all signals except the reset signal. The resetsignal has a separate signal list since it is a ”Fabric type”.

• The keyword ”out” in a VHDL entity corresponds to ”FromCLIP” in theXML file.

• The keyword ”in” in a VHDL entity corresponds to ”ToCLIP” in theXML file.

• The clock frequency ranges of the clock signal in VHDL has to be specifiedin the signal list.

An automation program (fairly tested) has been written in this thesis work,which uses a given VHDL file to automatically generate a XML file. The nameof the program is VHDL Entity Parser and is written in C++.

When the XML file is written, it can be imported into LabVIEW and instan-siated in a LabVIEW block diagram.

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3.1.3.1 Workaround for hierarchical architectures

Sometimes VHDL projects have a hierarchical structure. That means that the topVHDL file includes components that are declared in other VHDL files, and thesefiles in its turn includes components that are declared in other VHDL files. CLIPdoesn’t detect this dependency, so every file that belongs to a VHDL project must beimported into LabVIEW. However, there is a relief here. The first step in the guideabove can be skipped when importing files with entities that shouldn’t accessed inthe LabVIEW block diagram (every file except the top VHDL file).

That means that a XML file must be created for every file in the VHDL project,but there is no need to modify their entity to make it agree with the datatypes ofLabVIEW. For every std logic vector type in the VHDL file, just pick any of theword data types (U8, U16, U32, U64, I8, I16, I32, I64) and specify it in the XMLfile.

3.2 GHDL

Some parts of the design in this master thesis are VHDL blocks which have beenimported in LabVIEW. VHDL has a better expression power and generates moreefficient hardware than LabVIEW code. Therefore it is more suitable for calculationintensive operations, such as digital filters.

One benefit with VHDL code is that it exists tools that makes it possible to analyze,simulate and verify its behavior. A tool that is named GHDL has been used in thisproject.

GHDL is a shorthand for G Hardware Design Language. It is an open source VHDLcompiler that can execute (nearly) any VHDL program. It is not a synthesis tool,which means netlists can’t be created with GHDL. GHDL has a great library ofpackages that can be used for compilation of VHDL files, such as std logic 1164,std logic arith and std logic signed [13].

The current version of GHDL doesn’t contain any waveform viewer. The waveformviewer that has been used in this master thesis is GTKWave, which also is opensource software. More information about GTKWave can be found in section 3.3.

3.2.1 Usage

The mostly used commands of GHDL are those to analyze, elaborate and simulatinga design. They must be executed in the mentioned order in order to be able toperform a VHDL testbench simulation. That means that elaboration has to beperformed before simulation, and analysis has to be performed before elaboration.

In order to analyze a VHDL file and let it have support for the synopsys implemen-tation of the IEEE packages, the following command in a terminal can be used:

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ghdl -a --ieee=synopsys -fexplicit <Path to your VHDL file>

Elaboration is performed by entering the following command:

ghdl -e --ieee=synopsys -fexplicit <Entity name of your VHDL file>

Finally, simulation of the design can be performed by entering the following com-mand:

ghdl -r --ieee=synopsys -fexplicit <Entity name> --stop-time="<Simulation Time>"

--vcd=<name of simulation output>.vcd

The simulation output file (the .vcd file) can be viewed using a waveform viewer,such as Modelsim or GTKWave. GTKWave has been used during this project. Ashort description of GTKWave is given in section 3.3.

3.2.2 Adding support for the Unisim Library

Often it is desirable to be able to simulate integrated FPGA components, such asblock rams, DSP blocks or distributed RAM in a waveform viewer. GHDL doesn’tinclude any support for these components at all, not for any FPGA manufacturer.These libraries has to be compiled manually with GHDL.

The library that are used for Xilinx devices are the Unisim library. Adding supportfor this library is a bit tricky but works following these guidelines:

1. First get a copy of the Unisim library. A copy from the installation folder of Na-tional Instruments FPGA has been used in this thesis work. Place the libraryin the directory below the directory of the VHDL files that should be simulated.For example, if the VHDL files are located under ”c:\my-vhdl-files\”, then thefiles for the unisim library should be located under ”c:\my-vhdl-files\unisim\”.The library should consist of the following files:

• unisim SECUREIP.vhd

• unisim SMODEL.vhd

• unisim VCOMP.vhd

• unisim virtex5 SMODEL.vhd (unique for Virtex-5 devices)

• unisim VITAL.vhd

• unisim VPKG.vhd

2. Open a terminal and use the ”cd” command to change directory the unisimdirectory.

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3. Analyze the files one by one with the following commands, in the followingorder:

ghdl -a --work=unisim --ieee=synopsys -fexplicit unisim_VCOMP.vhd

ghdl -a --work=unisim --ieee=synopsys -fexplicit unisim_VPKG.vhd

ghdl -a --work=unisim --ieee=synopsys -fexplicit unisim_VITAL.vhd

ghdl -a --work=unisim --ieee=synopsys -fexplicit unisim_SMODEL.vhd

ghdl -a --work=unisim --ieee=synopsys -fexplicit unisim_virtex5-SMODEL.vhd

ghdl -a --work=secureip --ieee=synopsys -fexplicit unisim_SECUREIP.vhd

Some errors may occur when analyzing unisim VITAL.vhd. Comment the er-roneus lines out and reanalyze the file and the files after it. The lines are notneeded for a proper compilation.

4. When Unisim is analyzed, it is ready to be used for simulation with the VHDLfiles. In order to use the Unisim library with a VHDL file, perform the follow-ing:

(a) The VHDL files that uses an Unisim component have to include the fol-lowing line next to its signal declaration list (between ”architecture” andbegin):

for all : COMPONENT_TO_USE use entity unisim.COMPONENT_TO_USE;

Where COMPONENT_TO_USE is the Unisim component that should be sim-ulated.

(b) Then analyze and elaborate the VHDL files one by one with the followingcommands:

ghdl -a -Punisim --ieee="synopsys" -fexplicit THE_VHDL_FILE

ghdl -e -Punisim --ieee="synopsys" -fexplicit THE_VHDL_FILE

3.3 GTKWave

GTKWave is a fully featured GTK+ based waveform viewer which reads and numberof files, as well as standard Verilog VCD/EVCD files and allows their viewing.GTKWave is developed for Linux, with ports for various other operating systemsincluding Microsoft Windows (either natively as a Win32 application or via Cygwin)and Mac OS X.

GTKWave isn’t as sophisticated as its competitors, such as Modelsim, but has beenmore than good enough for the work in this master thesis. It provides a componentwaveform viewer that is entirely free.

GTKWave is best used from a terminal command line, by giving a path to a .vcdfile (suggestively generated by GHDL):

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gtkwave <path to .vcd file>

In order to load a save file that keeps all settings you have done in GTKWave,specify the path to the save file as the second argument:

gtkwave <path to vcd file> <path to .sav file>

A screenshot of GTKWave is shown in figure 23.

Figure 23: Screenshot of GTKWave.

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4 Theory

4.1 Bilinear transform

Often there exist well proven continuous-time systems which functionality needsto be transferred to a discrete-time domain. Such systems are butterworth filters,chebyshev filters, bessel filters and comb filters.

Stability is a desirable property for both continuous-time systems and discrete-timesystems. If a continuous-time system is stable, it is required that the translateddiscrete-time system also is stable. A continuous-time system is stable if all polesare in the left part of the s-plane, and a discrete-time system is stable if all poles arewithin the unit circle of the z-plane. Therefore it’s desirable if the entire left part ofthe s-plane can be transformed to the inner part of the unit-circle of the z-plane.

Sune Soderkvist [18] describes at page 273 a method called bilinear transform, whichsatisfies the requirements stated above. Bilinear transform is performed by doingthe following variable substitution:

s = γ

(z − 1

z + 1

)(2)

where γ is an arbitrary constant. The imaginary axis of the s plane is transformedto the unit circle of the z plane according to the following relation:

Ω = 2 arctanω

γ(3)

The γ constant is suggestively adapted in a way so that a certain point in thecontinuous-time domain is transformed to a certain point in the discrete-time do-main. When performing filter transformations, that point is suggestively the cut-offfrequency of the filter. This approach is applicable for low pass filters and highpass filters, which only have one point of action which is interesting (the cut-offfrequency).

4.2 Filter

One or more filters should be implemented on the FPGA chip in order to satisfy therequirements given in section 2.3. Sune Soderkvist [18] classifies two types of filtersat page 237:

• FIR filters

• IIR filters

Marcus Stavstrom 33


FIR filters are characterized by not having any feedback loops. The impulse responseis finite, because it settles to zero in a finite number of sample intervals. The transferfunction of it can be generalized to:

H[z] =

N∑i=0

aiz−i (4)

FIR filters do not have any feedback loops in their design, which make them stablefor all amplification coefficients that are less than infinity. FIR filters suffers froma major disadvantage, which is the poor filter characteristics for low filter orders.In order to obtain a FIR filter with good characteristics, a high order has to beimplemented. A high order in its turn requires a large amount of hardware, whichis the main disadvantage of these filters. A conceptual FIR filter is illustrated infigure 24.

z-1

z-1

x[n]

y[n]

. . .

z-1

a0 a1 aN

Figure 24: FIR filter.

IIR filters, in opposite to FIR filters, have feedback loops in their design. Theimpulse response in infinite. The transfer function can be generalized to:

H[z] =

P∑i=0

aiz−i

1 +

Q∑j=1

bjz−j

(5)

A low order IIR filter can be used to achieve good filter characteristics. However,the presence of feedback loops may cause the filter to continue to respond infinitelyon certain input patterns. An IIR filter of order two is illustrated in figure 25.

Marcus Stavstrom 34


z-1

z-1

x[n] y[n]

a1

a2

b1

b2

a0

Figure 25: IIR filter of order two (biquad filter).

The higher the order of the filter, the more sensitive it will be to truncation errorsand quantization errors. A good approach here is to cascade a number of IIR-filtersof a low filter order. A suitable special case of an IIR-filter of a low filter order isthe biquad filter.

A biquad (shorthand for bi-quadratic) filter is an IIR filter of order two, which meansit has two poles in its transfer function.

S.M. Kuo, B.H. Lee and W. Tian [19] describes at page 266 the cascade form real-ization of an IIR filter. The form assumes that the transfer function is the productof a second order IIR sections (biquad). That approach will make it possible tocreate a high order IIR filter using several low order IIR filters that are cascaded.Let H1[z] and H2[z] be the transfer functions for two separate biquad filters. Thenthe entire filter has the following transfer function H[z]:

H[z] = H1[z]H2[z] (6)

Sune Soderkvist [17] describes at page 299 the characteristics of a butterworth filter.The butterworth filter is designed to have a flat frequency response in the passband.That is a desirable property in measurement instruments like oscilloscopes sincenothing in the measurement instrument should affect the measured value in thepassband.

A continuous-time butterworth filter has the following transfer function H(s), whereω0 is the 3 dB cut-off frequency:

Marcus Stavstrom 35


H(s) =1

1 + b1sω0

+ b2

(sω0

)2

+ ...+(sω0

)n (7)

The poles to the filter H(s) are given by the following expression:

pk = ω0e(j 2k+n−1

2n π), k = 1, 2..., n (8)

With the location of the poles, it’s easy to determine the factorized transfer functionfor a butterworth filter:

H(s) =1(

s− ω0e(j 1+n

2n π))(

s− ω0e(j 3+n

2n π))...(s− ω0e

(j 2k+n−12n π)

) ,k = 1, 2..., n

(9)

The entire filter should be able to use one, two, three or four biquad sections, whichwill result in four transfer functions H1(s), H2(s), H3(s) and H4(s):

H1(s) =1(

s− ω0ej34π)(

s− ω0ej54π)

H2(s) =1(

s− ω0ej58π)(

s− ω0ej78π)(

s− ω0ej98π)(

s− ω0ej118 π)

H3(s) =1(

s− ω0ej712π)(

s− ω0ej912π)(

s− ω0ej1112π)(

s− ω0ej1312π)

1(s− ω0ej

1512π)(

s− ω0ej1712π)

H4(s) =1(

s− ω0ej916π)(

s− ω0ej1116π)(

s− ω0ej1316π)(

s− ω0ej1516π)

1(s− ω0ej

1716π)(

s− ω0ej1916π)(

s− ω0ej2116π)(

s− ω0ej2316π)

(10)

Pairing of complex conjugated pairs gives the following transfer functions:

Marcus Stavstrom 36


H1(s) =1(

s2 + 2ω0 cos(π4 )s+ ω20

)H2(s) =

1(s2 + 2ω0 cos( 3π

8 )s+ ω20

) (s2 + 2ω0 cos(π8 )s+ ω2

0

)H3(s) =

1(s2 + 2ω0 cos( 5π

12 )s+ ω20

) (s2 + 2ω0 cos( 3π

12 )s+ ω20

)1(

s2 + 2ω0 cos( π12 )s+ ω20

)H4(s) =

1(s2 + 2ω0 cos( 7π

16 )s+ ω20

) (s2 + 2ω0 cos( 5π

16 )s+ ω20

)1(

s2 + 2ω0 cos( 3π16 )s+ ω2

0

) (s2 + 2ω0 cos( π16 )s+ ω2

0

)

(11)

The filter implemented in the FPGA is discrete, so a transformation between continuous-time and discrete-time domain has to be performed. Bilinear transform is a goodway of doing this, since the entire left plane of the s-plane is transformed to theinner part of the unit circle of the z-plane. Bilinear transform is performed by doingthe following variable substitution:

s = γ

(z − 1

z + 1

)(12)

where γ is an arbitrary constant. The imaginary axis of the s plane is transformedto the unit circle of the z plane according to the following relation:

Ω = 2 arctanω

γ(13)

It is proper if the cut-off frequency is transformed to its corresponding point on theunit circle in the z plane. That is done by choosing γ so the cut-off frequency ω0

of the continuous-time filter is transformed on the normed angular frequency Ω0 ofthe discrete-time filter, so that:

ω0 = γ tanΩ0

2⇒ γ =

ω0

tan Ω0

2

(14)

Since each biquad section has an order of two, it is proper if each complex conjugatedpair of poles in the transfer functions H1(s), H2(s), H2(s) and H4(s) are mappedinto a separate biquad section. As seen in equation (11), the transfer function foreach biquad section can be generalized with the following expression:

Hbiquad(s) =1

s2 + 2ω0 cos(

(2k−1)π2n

)s+ ω2

0

k = 1, 2...,n

2(15)

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Let Ck,n = 2 cos(

(2k−1)π2n

)in order to simplify the equations, then Hbiquad(s) will

be given by the following expression:

Hbiquad(s) =1

s2 + Ck,nω0s+ ω20

(16)

Where n is the filter order and k = 1, 2, ..., 2n − 1. Rename the coefficients inequation (16):

bs0 = ω20 , bs1 = Ck,nω0, bs2 = 1

⇒ Hbiquad(s) =1

bs0 + bs1s+ bs2s2

(17)

Applying bilinear transformation to the continuous-time transfer function of eachbiquad section gives the following equations:

Hbiquad[z] =1

bs2

(γ z−1z+1

)2

+ bs1

(γ z−1z+1

)+ bs0

=(z + 1)2

bs2γ2(z − 1)2 + bs1γ(z − 1)(z + 1) + bs0(z + 1)2

=z2 + 2z + 1

z2(bs0 + γbs1 + γ2bs2) + z(2bs0 − γ22bs2) + (bs0 − γbs1 + γ2bs2)

=z−2 + 2z−1 + 1

z−2(bs0 − γbs1 + γ2bs2) + z−1(2bs0 − γ22bs2) + (bs0 + γbs1 + γ2bs2)(18)

Let K = bs0 + γbs1 + γ2bs2:

Hbiquad[z] =z−2

K + 2z−1

K + 1K

z−2 (bs0−γbs1+γ2bs2)K + z−1 (2bs0−γ22bs2)

K + 1(19)

A time-discrete filter with two poles and two zeros is obtained using this transforma-tion, which will fit perfectly inside a biquad section. Six coefficients can be identifiedfor the biquad filter:

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b0 = 1

b1 =2bs0 − γ22bs2

K

b2 =bs0 − γbs1 + γ2bs2

K

a0 =1

K

a1 =2

K

a2 =1

K

(20)

where K = bs0 + γbs1 + γ2bs2.

4.3 DSP48E

The Virtex 5 FPGAs provides an interesting component that is called DSP48E,which is a component can be used for a variety of DSP intensive calculations. Prin-cipally it consist of one multiplier and one ALU. The ALU can be used to accumulatedata from the multiplier with data from an input of the DSP block or with datafrom other DSP blocks. These properties makes this component ideal for filterapplications, since it includes a lot of multiplication and accumulation.

DSP48Es are stacked in so called DSP48E columns. There are a various numberof those columns, and a various number of DSP48Es in each column, dependingon what FPGA that is used. For example, the FPGA that is used in this project(XC5VSX95T) contains 10 DSP48E columns with 64 DSP48Es in each column [10].Organizing DSP48Es into columns makes it possible for all DSP48Es to use thecomputation results from its adjacent DSP48Es.

An simplified block diagram of the DSP48E component is illustrated in figure 26.

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25 x 18

DD

D

DD

D

ALU D

A

B

C

P

PCOUT(To next DSP48e block)

PCIN(From previousDSP48e block)

ALU mode(add, sub etc.)

A1 A0

B1 B0

M

C

P

Figure 26: Simplified block diagram of a DSP48E block.

As shown in figure 26, the DSP48E block consist of a number of synchronizationregisters. All these registers, except the M register, can be enabled or disabled inthe generic declaration part of the DSP48E component.

The ALU in the DSP48E component can be configured to perform a number ofarithmetic operations, such as addition, subtraction, bitwise AND or bitwise OR.

The multiplexers can only be configured before compile time.

Marcus Stavstrom 40


5 Results

This section describes the results of the investigation which have been done in thismaster thesis. An oscilloscope and a function generator have been implemented ona FPGA device and combined it with A/D- and D/A-converters in order to be ableto monitor and output analog signals.

Figure 27: Screenshot of the user interface for the oscilloscope and the functiongenerator.

The user interface of the oscilloscope and function generator is shown in figure 27.With this user interface, it is possible to perform the following tasks:

• Use two vertical markers to measure the difference between two points in thewaveform.

• Measure peak-to-peak voltage and voltage RMS.

• Apply a customizable low pass filter for one of the input channels.

• Apply up to three trigger conditions. For each trigger condition, it is possibleto specify a voltage span in which the measured waveform should satisfy. It isalso possible to specify the allowed time between the trigger conditions.

• Generate a waveform with a desired frequency and DC-offset. Available wave-forms are sinus and square wave. The duty cycle of the square wave can bechanged.

Marcus Stavstrom 41


The architecture of the oscilloscope and the function generator is described in section5.1. The performance achieved by implementing this architecture is given in section5.7.

5.1 Architecture

This section describes the architecture of the oscilloscope and the function generatorwhich have been implemented.

The oscilloscope and the function generator is mainly programmed using componentsin LabVIEW block diagrams. There are a few blocks that have been programmedin VHDL and imported to the LabVIEW block diagram via CLIP, such as the inputfilter, the trigger unit, the VPP unit and the RMS unit. These components amongwith several others are illustrated in the block diagram given in figure 28.

The clock frequency of the logic has been set to the same as the clocking frequencyof the A/D- and D/A-converters.

Analog signals

ADC

ADC

Filter selector

Trigger selector

Filter

Trigger

DMA Channel 1 input

DRAM Bank 1 input

DMA Channel 0 input

DRAM Bank 0 input

DMA Channel 0 selector

DMA Channel 1 selector

DRAM Bank 0

DRAM Bank 1

Trig request?

VPP Unit

RMS Unit

Figure 28: Overview of the oscilloscope architecture.

Note that the block diagram illustrated in figure 28 only is a course overview.

More information about each block illustrated in figure 28 is given in the sections5.1.1, 5.1.2, 5.1.3, 5.1.4, 5.1.5, 5.6.1 and 5.6.2.

Marcus Stavstrom 42


5.1.1 Analog to digital converters

The analog to digital converters are located in the IO module that is attached tothe FPGA card.

The analog to digital converters samples data with 14-bit precision, but this isimmediately extended to 16 bits in order to simplify read and write operation of theDRAM controller. For more information about this issue, refer to section 5.6.1.

5.1.2 Filter selector

Only one filter have been implemented in order to reduce the synthesizing timesof the FPGA project. The filter selector makes it possible to either connect inputsignal A or input signal B to the input filter.

Filter selector

To filter input

Output signal A

Output signal B

From filter output

Input signal A (from ADC A)

Input signal B (from ADC B)

Figure 29: Interface of the filter selector.

5.1.3 Filter

An input filter is implemented on the oscilloscope in order to make it possible toremove undesired signal components from the analyzed input signal. The input filterconsist of four separate biquad filters and one multiplexer. A block diagram showingits architecture is given in figure 30.

Marcus Stavstrom 43


Biquad section

Filter output

mux

Filter coefficients

Filter coefficients

Filter coefficients

Filter coefficients

Input signal

Output signal

Nr of filter stages to use

Biquad section

Biquad section

Biquad section

Figure 30: Block diagram of the filter architecture.

The filter order, or the number of biquad stages enabled, can be controlled from theuser interface panel. For example, if only one biquad stage is enabled, the multiplexerwill take the signal between the first biquad stage and the second biquad stage andforward this to the output of the multiplexer.

Each biquad stage adds an order of two to the filter, which means that the entirefilter can be of order two, four, six or eight. The higher order enabled, the moresteep the cut-off frequency slope will be. However, higher order of the filter results ina larger filter with more computations. That results in a larger number calculationerrors which may affect the filter stability.

5.1.3.1 Run-time filter synthesis

The filter is synthesized by using an application that is executed on the host com-puter. When the user either changes cut-off frequency or filter order, the applicationcalculates new filter coefficients and sends them to the FPGA hardware.

The application that calculates the filter coefficients is called filter create. It isdivided into two major stages:

• Butterworth filter synthesis

Given sample frequency, cut-off frequency and filter order, the program calcu-lates the filter coefficients for a continuous-time butterworth filter. The allowedorders are two, four, six or eight since the discrete-time filter on the FPGAcan be customized to use one, two, three our four biquad sections (each biquadsection adds an order of two to the filter).

• Bilinear transform

When the coefficients for time-continuous butterworth filter has been calcu-lated, the program transforms the continuous-time filter to a discrete-time

Marcus Stavstrom 44


filter. That is performed by using bilinear transformation. As mentionedabove, the filter implemented on the FPGA consist of several cascaded biquadsections. Each biquad section has a filter order of two, giving it two complexconjugated poles in a pole-zero diagram of its transfer function. Thus, eachcomplex conjugated pair of poles in the continuous-time filter is transformedseparately into the discrete-time domain. Two poles in the continuous-time fil-ter are mapped to two poles in the discrete-time filter, which makes it possibleto fit it into a biquad section.

5.1.4 Trigger selector

Only one trigger is implemented on the FPGA hardware, so a selector (multiplexer)is implemented to make it possible to either trig on input signal A or input signalB.

5.1.5 Trigger

A trigger unit has been implemented on the FPGA hardware in order to make itpossible for the user to specify certain signal properties which will cause the dataacquisition to stop. Trigger units that monitors the signal in real-time on the FPGAhardware are essential in order to catch up with the data acquisition speeds of theanalog to digital converters.

The trigger unit is implemented in VHDL code, and the block diagram for it isattached with appendix B. It has a variety of input signals, but the most dis-tinctive part are the trigger signals that control the three separate trigger condi-tions. The properties given by each trigger condition is monitored by shared hard-ware. If no trigger condition has been satisfied, the values given by trig_level_1,trig_level_tol_1, trig_slopel_1 etc. will be forwarded by the multiplexersto the following hardware. When the input signal satisfies the properties givenby this trigger condition, the values given by trig_level_2, trig_level_tol_2,trig_slopel_2 etc. will be forwarded instead.

The trigger_done signal indicates if all trigger conditions has been satisfied bygoing high. It will remain high unless it is reset by the trigger_reset signal. Thissignal controls the data acquisition. If it goes high, data acquisition stops and if itgoes low acquisition starts.

As shown in the block diagram, the trigger level detection is performed inside ahysteresis unit.

5.2 Implementing biquad filter with DSP48E components

S.M. Kuo, B.H. Lee and W. Tian [19] describes at page 265 direct form II structureof a biquad filter, as shown in figure 31.

Marcus Stavstrom 45


D

D

b1

b2

a0

a1

a2

Input Output

Figure 31: Direct form II structure.

The direct form II structure gives the following transfer function H[z]:

H[z] =a0 + a1z

−1 + a2z−2

1 + b1z−1 + b2z−2(21)

In order to utilize the DSP48E component for the direct form II structure, a num-ber of modifications have to be performed. This is because the M register of theDSP48E can’t be disabled, so a natural delay element has to be inserted after themultiplications. A standard pipelining has been performed in order to acheive thisproperty, and the result is illustrated in figure 32.

D

D

b1

b2

a0

a1

a2

Input Output

DD D

D

D

D

D

Figure 32: A transformed direct form II biquad filter.

Figure 32 shows a transformed biquad filter, where the synchronization registers

Marcus Stavstrom 46


have been moved without affecting the transfer function of the biquad filter. Usingthis transformation, six DSP48Es in each biquad section can be identified, as shownin figure 33.

D

D

b1

b2

a0

a1

a2

Input Output

DD D

D

D

D

D

DSP48E

DSP48E

DSP48E

DSP48E

DSP48E

DSP48E

Figure 33: A transformed direct form II biquad filter, identifying DSP48Es.

The DSP48E on the top left in figure 33, which adds the input signal to the feedbackloop, doesn’t contain any multiplication. That behavior is achieved by inputtingzeros to the inputs of the multiplication unit.

5.3 Mapping filter poles to biquad section

The mapping between poles in the continuous-time filter and poles in the biquadsections are illustrated in figure 34, 35, 36 and 37.

Marcus Stavstrom 47


Biquad 1

Biquad 1

Figure 34: Mapping of filter poles between the time-continuous butterworthfilter of order 2 and the time discrete filter.

Biquad 1

Biquad 1

Biquad 2

Biquad 2


Marcus Stavstrom 48


Biquad 1

Biquad 1

Biquad 2

Biquad 2

Biquad 3

Biquad 3


Biquad 1

Biquad 1

Biquad 2

Biquad 2

Biquad 3

Biquad 3

Biquad 4

Biquad 4


5.3.0.1 Biquad stage

The final biquad design is illustrated in figure 38.

Marcus Stavstrom 49


DSP48E

A

B

C PCIN

PCOUT P

DSP48E P

PCIN

PCOUT A

B

C

DSP48E P

PCIN

PCOUT A

B

C

Coeff b1

Coeff b2

0x0

0x0

DSP48E

A

B

C PCIN

PCOUT

P

DSP48E

A

B

C PCIN

PCOUT

P

DSP48E

A

B

C PCIN

PCOUT

P

Output signal

Input signal

0x0

0x0

Coeff a0

Coeff a1

Coeff a2

0x0

0x0

0x0

Figure 38: Final implementation of biquad filter, using DSP48Es.

5.4 Preventing incorrect slope detection

When the user of the oscilloscope is specifying trig voltage level and slope, it is desir-able to have functionality that makes it possible to reject high frequency componentsof the signal that can disturb the slope detection. An example is illustrated in figure39, where a negative slope is desired at a certain trigger level. This example showsthat high frequency components, such as noise, can disturb the slope detection sothe trigger triggers at a wrong location.

Marcus Stavstrom 50


Trig level

Negative slope desired

Trigger point!

Figure 39: Figure illustrating a slope detection error when monitoring noisysignals.

Regarding this problem, it is possible for the user of the oscilloscope to specifytrigger tolerance levels that works as a kind of hysteresis. Figure 40 illustratesexactly the same scenario as in figure 39, but trigger tolerance levels has been setto avoid incorrect slope detection. Here the signal has to pass through the entire”trigger tolerance window” before it is detected as a slope. In this example, theslope around the illustrated trig level will be detected as a positive slope.

Trig level

Trig level tolerance

Figure 40: Figure illustrating the hysteresis approach.

The hysteresis unit is implemented in VHDL code. The block diagram for it isshown in Appendix C.

5.5 Multiple trigger conditions

This function is useful if the trigger condition specified by trigger condition 1 happensmore frequently than trigger condition 2. An example is illustrated in figure 41. Thefirst trigger condition will be satisfied, but the second trigger condition will not besatisfied since the maximum time limit between the first and the second triggercondition is exceeded.

Marcus Stavstrom 51


Trigger condition 1

Trigger condition 2

Trigger condition 1 satisfied!

Time 0

Minimum time betweentrigger condition 1 andtrigger condition 2

Maximum time betweentrigger condition 1 andtrigger condition 2

Figure 41: A situation with two trigger conditions, which will not trig.

The scenario which is shown in figure 41 is also illustrated in figure 42. The firstand the second trigger condition are both satisfied and fulfills all constraints, whichwill cause the trigger unit to trig.

Marcus Stavstrom 52


Trigger condition 1

Trigger condition 2


Time 0

Minimum time betweentrigger condition 1 andtrigger condition 2

Maximum time betweentrigger condition 1 andtrigger condition 2


Figure 42: A situation with two trigger conditions, which will trig.

5.6 Variable waveform window span

It is desirable to have a waveform window in which the waveform can be zoomedin or zoomed out. The ability of zooming in and zooming out introduces a variablewaveform window span. The variable waveform window span is dependent of twofactors:

• The zoom factor

• The size of memory, where all samples are stored.

The waveform window span is a measure of how wide memory address area that isspanned by the waveform window. For example, a waveform window that is zoomedout has a longer time between first sample (at the left) and the last sample (at theright), than a waveform window that isn’t zoomed out. A longer time between thefirst sample and the last sample represents in larger distance in the memory.

A large zoom factor causes the waveform window span get big, and a lower zoomfactor will cause the waveform window span to get small. A larger waveform windowspan will also cause the offset boundaries to shrink, as illustrated in figure 43.

Marcus Stavstrom 53


Memory

Adress 0 Adress N

Small waveform window

(a) Small waveform windowspan, caused by a small zoomfactor

Memory

Adress 0 Adress N

Large waveform window

(b) Large waveform windowspan, caused by a large zoom fac-tor

Figure 43: Offset and waveform window zoom factor.

The width of the waveform window, W , when using a zoom factor Z is given by thefollowing relation:

W = NZ (22)

The constant N is the number of samples that are sent to the host computer. Azoom factor Z with a value 1, which is the lowest specifiable, will cause W to achievea value of N . That means that the waveform window will be N addresses wide.

The maximum and the minimum boundaries for the offset scale will be given by thefollowing relation:

|O| ≤ M −W2

(23)

where M is the number of samples that can be stored in the memory. An offset whereO = 0 represents a waveform window that aligns in the middle of the memory, asillustrated in figure 44.

Memory

Adress 0 Adress NOffset = 0

Waveform window

Figure 44: Waveform window placement when the offset is zero.

The number of samples S that fits into the memory with size M (in bytes) is givenby the relation

Marcus Stavstrom 54


S =M

2(24)

since each sample takes two bytes. Then time range T of the memory is given byfollowing relation

T = S1

fs(25)

where fs is the sample frequency. For example, a memory with a size of 8 kB (8192bytes) sampling at a frequency of 100 MHz can store a time range of

S =8192

2= 4096⇒ T = 4096

1

100000000= 40.96µs (26)

5.6.1 On-board DRAM

The FPGA board which have been used during this project includes an on-boardDRAM. The DRAM is divided into two banks, DRAM bank 0 and DRAM bank 1,which each can store 256 Megabytes of data. DRAM bank 0 is used to store samplesfrom input signal A and DRAM bank 1 is used to store samples from input signalB.

5.6.1.1 Addressing

The DRAM is accessed using a memory controller that is provided by NationalInstruments. Data words on the DRAM are addressed on a 32-bit level, but datais retrieved and written in 128-bit words. This causes some extra restrictions thatneeds to be considered. Figure 45 illustrates the problem with an example, wherethe data stored at each address contain the address itself.

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0x0100 0x0101 0x0102 0x0103Address 0x0100

0x01000x0101 0x0102 0x0103Address 0x0101

0x0100 0x01010x0102 0x0103Address 0x0102

0x0100 0x0101 0x01020x0103Address 0x0103

Output from DRAM data controller

0x0105 0x0106 0x01070x0104Address 0x0104

(Each block consist of 32 bits)

Figure 45: DRAM adressing.

This memory controller approach generates the following requirements during readand write operations:

• Data can be retrieved at every single address as long as only the first 32-bitsis considered.

• Data can only be written at every fourth address, since four 32-bit words arewritten at every write operation.

In order to solve this problem, the oscilloscope uses a temporary data storage mech-anism which waits for eight samples before they are written to the DRAM. Eachsample is 16 bits wide, which results in eight data samples per write operation (16bits times 8 is 128 bits).

5.6.2 DMA

Waveform data is sent to the host computer by using two separate DMA channels,one for channel A and one for channel B. Waveform data is continuously sent ata speed of 100 MHz to the host computer when data acquisition is in progress. If

Marcus Stavstrom 56


data acquisition is stopped, samples will only be sent on demand. That happensif the waveform window needs to be updated, for example when the offset slider isadjusted.

The DMA channel is implemented by using a standard component in LabVIEW.

5.6.3 VRMS unit

The VRMS unit is used to calculate VRMS of the signal at input channel A. TheVoltage Root Mean Square Vrms is calculated accordning to the formula

Vrms =

√√√√ 1

N

N−1∑i=0

s2i (27)

where N is the number of samples and si is the voltage level of a certain sample.The square operation is done by inputting the input signal to both multiplicationinputs of a DSP48E. The result from this operation is forwarded to another DSP48E,which performs the summation of 220 samples. The division is done by performinga shift operation, since a radix-2 number of samples is used in the calculation ofthe VRMS. The square root operation is done by using a standard component inLabVIEW.

The block diagram of the VRMS unit is attached with appendix D.

5.6.4 VPP unit

The VPP unit stores the lowest and the highest input sample during a specifiedamount of time. The amount of time is determined by the surrounding LabVIEWcode.

The block diagram of the VPP unit is attached with appendix E.

5.6.5 Oscilloscope states

The oscilloscope uses four operational states, which all are described in the followingsections. A state diagram is given in figure 46.

Marcus Stavstrom 57


Init Idle

Start

Write block

Trigger disabled?

Trigger enabledand trigger conditionssatisfied?

Read block

DRAMinitialized?

Trigger enabled, trigger conditions satisfied and

update frame command received?

Waveform frame transmission done?

Figure 46: The different FPGA states.

5.6.5.1 Init state

The Init state is entered at startup of the FPGA hardware. It waits for the DRAMcontroller to initialize. After that, it enters the Idle state.

5.6.5.2 Idle state

The Idle state is a kind of ”wait for user interface” state. It is used when all triggerconditions have been satisfied. Basically it doesn’t perform anything, more thanwaiting for commands from the user interface which will make it enter either theWrite block state or the Read block state. The commands that will make it entereither Write block state or Read block state are the following:

• Trigger unit disable command. When the trigger is disabled, the oscilloscopeis ready to start the data acquisition and write data to the DRAM. That isperformed by entering the Write block state.

• A frame update command. No data are written to the DRAM and no waveformdata are sent to the user interface when the trigger is active and all triggerconditions have been satisfied. If the user of the oscilloscope for instance

Marcus Stavstrom 58


changes the zooming factor of the waveform window, an ”updated” waveformwindow frame has to be sent from the FPGA to the user interface. That isdone by sending a frame update command to the FPGA hardware, which willcause it to leave the Idle state and enter the Read block state.

5.6.5.3 Write block state

The Write block state is used when the trigger is disabled, or when the trigger isenabled and the trigger conditions haven’t been satisfied.

During the Write block state, sampled data from the analog to digital convertersare written to the DRAM and continuously sent to the user interface panel.

In order for the oscilloscope to leave the Write block state, the trigger has to beenabled and all trigger conditions has to be satisfied. When all trigger conditionshas been satisfied, data acquisition will continue until half the DRAM is filled fromthe trigger point that should be centered in the DRAM. After that it enters the Idlestate.

The write state itself uses two operational states, which are called Continuouslywrite and Finishing write. The state chart diagram is illustrated in figure 47.

Continuouslywrite

Finishingwrite

Start

Trigger done? S samples writtento DRAM? Will leave the write

block state and enter the idle state

Figure 47: The states used within the Write block state.

5.6.5.3.1 Continuously write state

The Continuously write state is used during normal operation when the input signalhas not satisfied trigger conditions given to the trigger unit. If all trigger conditionsare satisfied, the oscilloscope will change state to the Finishing write state.

5.6.5.3.2 Finishing write state

The finishing write state does what the name indicates; it finishes the write state.When all trigger conditions have been satisfied, the data acquisition must continuefor a while in order to make it possible ”to see the future” beyond the trigger point.The number of samples S that is written to the DRAM during the Finishing writestate is given by the relation

Marcus Stavstrom 59


S =M

2− δ (28)

where M is the number of samples that fits in the memory. The symbol δ representsthe number of clock cycles that has elapsed between the last trigger condition andthe trigger condition that should be centered in the waveform window.

5.6.5.4 Read block state

The Read block is used to read one waveform window frame from the DRAM andsend it to the user interface. It is a short state and only lasts for a few hundreds ofclock cycles. When it has read a waveform window and transmitted it to the userinterface panel, it enters the Idle state again.

The read block state uses two state machines, one for each input channel. The statemachines manages the read operations from the DRAM. The states for both thesestate machines are:

• Start read

• Wait for read strobe

• Idle

A state diagram is shown in figure 48.

Wait for read strobe

Start read Idle

Channel A

Read strobe received?

400 samples read?

Wait for read strobe

Start read Idle

Channel B

Read strobe received?

400 samples read?

(Will leave read block stateif both channels are in

idle state)

Figure 48: The states used within the Read block state.

The Start read state is the initial state. It sends a read command to the memorycontroller. After that, it enters the Wait for read strobe state.

The Wait for read strobe state does what the name intends, it waits for a readstrobe signal from the memory controller. When a read strobe is detected, data

Marcus Stavstrom 60


from the memory is available on the outputs of the memory controller. That datais forwarded to the DMA controller, which will send it to the host computer. Afterthat, the state machine inside the Read block state will enter:

• Start read state again, if less that 400 samples has been read from the DRAM.

• Enter the idle state, if 400 samples has been read from the DRAM.

The idle state performs nothing, more than waiting for the second input channel tocomplete its read procedure. After that the Read block state will be leaved.

5.7 Performance

The oscilloscope has the following performance and capabilities:

• Two input channels, A and B

– Sample rate: 100 MS/s.

– Voltage swing: ±1V.

– 14 bit precision (lsb = 122 µV).

• One trigger unit, being able to:

– Trig on either input channel A or input channel B.

– Trig on up to three subsequent events, with the following requirements:

∗ Positive, negative or both slopes.

∗ A certain trig level.

∗ Specify levels to a hysteresis, which can reject high frequency compo-nents.

∗ Specify an allowed time span between two trigger events.

• One low-pass filter:

– Specify cut-off frequency from 1 MHz to 50 MHz.

– Specify filter order (two, four, six or eight)

• Adjustable data acquisition times, by changing size of memory.

• Measure VRMS and VPP.

• Two individual waveform cursors, which can:

– Measure voltage DC level.

– Measure difference in time between the cursors.

– Measure difference in amplitude between the cursors.

Marcus Stavstrom 61


• Zoom adjustment.

• Offset adjustment, which can be used browse the waveform that is stored inmemory.

The function generator has the following performance and capabilities:

• Two output channels, A and B:

– Update rate: 100 MS/s.

– Voltage swing: ±1V.

– 16 bit precision (lsb = 31 µV).

• Able to output sinus wave and square wave.

• Frequencies from 1Hz to 50 MHz.

• Duty cycle adjustment for square wave generator.

Marcus Stavstrom 62


6 Conclusions

The purpose of this master thesis was to investigate how FPGAs could be usedto create more flexible test equipment for testing avionics in JAS 39 Gripen. Anoscilloscope and a function generator have been developed in order to practice thisconcept. The oscilloscope has been equipped with two input channels and the func-tion generator has been equipped with one output channel. In order to practice theflexible measurement concept further, the oscilloscope has been equipped with a cus-tomizeable trigger unit which makes it possible to select multiple trigger conditions.It is also possible to connect a low pass filter to one of the input channels.

Building FPGA based test equipment is time consuming, but in return it offers fullytailored test systems for the users and their applications. It is a large initial cost butis a time saving approach in the long run. Another advantage is cost efficiency, sinceit is possible to reprogram the FPGA and implement various measurement appli-cations on the same hardware. The user also have full control of the programminginterface which eliminates the need of wrapper APIs.

LabVIEW has been the main tool used in this project. It has a lot of benefits asdescribed in section 2.7.3, but unfortunately it also suffers from a few disadvantages:

• Overproduction of VHDL code

LabVIEW produces a large amount of VHDL code when the VI block dia-grams are translated to VHDL code. Over 700 VHDL files were generated byLabVIEW at the last compilation of this project, which is a proportionatelygood measure that there is an overproduction of VHDL code. When thoseVHDL files had been synthesized, the project utilized about 30% of the FPGALUTs. That is a lot for such a small project like this, especially when theproject is implemented on such a large device as a SX95T FPGA.

• No waveform simulation ability

There is no way of performing any waveform simulation in LabVIEW. Thereexists a simulation mode though, where the functionality of the block diagramscan be simulated without any presence of FPGA hardware. At this kind ofsimulation, inputs and outputs of the LabVIEW block diagram are simulatedwith random numbers. However, inputs and outputs aren’t just physical inputto the hardware (such as those to the A/D- and D/A-converters). For exam-ple, memory interfaces and CLIP declarations are also treated as inputs andoutputs. That means there is no possibility of simulating your VHDL codeor any memory operations with the simulation mode. These components willonly output random numbers, no matter the input to them. The only wayof verifying this functionality is to synthesize the entire project, which is atime consuming process. Debugging, which often is a trial and error process,becomes very slow.

Marcus Stavstrom 63


• Demanding computer application

LabVIEW is a demanding computer application. Memory peaks up to 1.5GB have been experienced during this project, which significantly burdens thecomputer making it slower and less responsive.

It’s hard to say if it’s more time efficient to use LabVIEW or more efficient to useonly VHDL. LabVIEW suffers from the disadvantages that are described above, butit also offers some notable advantages. It’s hard to say if more work could have doneusing hardware from other manufacturers. Other manufacturers would have offeredthe ability to perform waveform simulation and synthesize a more optimized design,which would have saved a significant amount of time. However, the prepared userinterface panels and FPGA to PC communication, which LabVIEW offers, wouldtake a lot of time to develop using VHDL. The intuitive way of modeling hardwarein LabVIEW also makes it possible for a wider span of people to be involved in aFPGA project, which may be desirable for a working site where it’s common thatnew employers are participating.

6.1 Possible improvements

There are several improvements that can be done to this project:

• User interface

The user interface has some smaller bugs that can be corrected, such as miss-ing limits for certain input controls.

• More measurement operations

More measurement operations can be added to make the oscilloscope moreconvenient. Such operations are frequency measurement, phase shift and FFT.

• More efficient hardware

Some solutions that are implemented as LabVIEW code can be optimizedby implementing them in VHDL code instead.

Marcus Stavstrom 64

References

[1] National Instruments Corporation: NI PXIe-7965R NI FlexRIO FPGA Modulefor PXI Express,<http://sine.ni.com/nips/cds/view/p/lang/en/nid/208167> (2010-09-06)

[2] Xilinx Incorporated: Silicon Devices,<http://www.xilinx.com/products/devices.htm> (2010-10-06)

[3] Terasic Technologies Incorporated: Altera DE2-70 Board,<http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&

CategoryNo=53&No=226&PartNo=2> (2010-10-06)

[4] Altera Corporation: Cyclone II Device Handbook, Volume 1,Available at <http://www.altera.com/literature/hb/cyc2/cyc2_cii5v1.pdf>(2010-10-06)

[5] Terasic Technologies Incorporated: Highspeed AD/DA Card,<http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&

CategoryNo=73&No=278&PartNo=2> (2010-10-06)

[6] Xilinx Incorporated: Virtex-6 FPGA ML605 Evaluation Kit,<http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm> (2010-10-06)

[7] Xilinx Incorporated: XILINX VIRTEX R©-6 FAMILY FPGAS,Available at: <http://www.xilinx.com/publications/prod_mktg/

Virtex6_Product_Table.pdf> (2010-10-06)

[8] Lyrtech Incorporated: ADAC250,<http://www.lyrtech.com/Products/ADAC250.php> (2010-10-06)

[9] 4DSP, LLC: FMC110,<http://www.4dsp.com/FMC110.php> (2010-10-06)

[10] Xilinx Incorporated: XILINX VIRTEX R©-5 FAMILY FPGAS,Available at: <http://www.xilinx.com/publications/prod_mktg/

V5_LX__TXT_psm_table.pdf (2010-10-06)

[11] National Instruments Corporation: NI PXIe-1062Q 8-Slot 3U PXI ExpressChassis with AC - Up to 3 GB/s,<http://sine.ni.com/nips/cds/view/p/lang/en/nid/202664> (2010-09-06)

[12] National Instruments Corporation: NI 5781 Baseband Transceiver for NIFlexRIO,

Marcus Stavstrom 65

<http://sine.ni.com/nips/cds/view/p/lang/en/nid/208378> (2010-09-06)

[13] Tristan Gingold: GHDL User Guide,<http://ghdl.free.fr/site/pmwiki.php?n=Main.UserGuide> (2010-10-06)

[14] National Instruments Corporation: LabVIEW block diagram,<http://www.ni.com> (2010-10-06)

[15] National Instruments Corporation: NI-1062Q,<http://sine.ni.com/nips/cds/view/p/lang/sv/nid/202664> (2015-05-09)

[16] National Instruments Corporation: NI-PXIe-PCIe8371,<http://sine.ni.com/nips/cds/view/p/lang/sv/nid/203007> (2015-05-09)

[17] Sune Soderkvist: Tidskontinuerliga Signaler & System. Tryckeriet Erik Lars-son, 2000

[18] Sune Soderkvist: Tidsdiskreta Signaler & System. Tryckeriet Erik Larsson, 1994

[19] S.M. Kuo, B.H. Lee and W. Tian: Real-Time Digital Signal Processing. JohnWiley & Sons, 2006

Marcus Stavstrom 66

A CLIP XML file example

The following example shows a VHDL file and its corresponding CLIP declarationfile. I have created a dummy VHDL entity named ”my entity name”. The filenameof the dummy VHDL file is assumed to be the same as the entity (with extension),namely ”my entity name.vhd”. It is also assumed that the VHDL file and the XMLfile are located in the same directory.

Listing 1: VHDL entity example

Entity my entity name i sport (

c l k : in s t d l o g i c ;r s t : in s t d l o g i c ;input : in s t d l o g i c v e c t o r (15 downto 0 ) ;output0 : out s t d u l o g i c v e c t o r (63 downto 0 ) ;output1 : out s t d u l o g i c v e c t o r (63 downto 0 ) ;f u l l : out s t d l o g i c

) ;end ;

Listing 2: Corresponding XML file

<?xml version=” 1 .0 ”?><CLIPDeclaration Name=” my entity name ”><FormatVersion>1 .0</FormatVersion><HDLName>my entity name</HDLName><Implementat ionList><Path>my entity name . vhd</Path>

</ Implementat ionList><Inter faceType>LabVIEW</ Inter faceType><S i g n a l L i s t>

<S igna l Name=”Clock”><HDLName>c l k</HDLName><DataType><Boolean />

</DataType><Dir e c t i on>ToCLIP</ Di r e c t i on><SignalType>c l o ck</ SignalType><FreqInHertz><Max>500M</Max><Min>50M</Min>

</ FreqInHertz></ S igna l>

<S igna l Name=” input ”>

Marcus Stavstrom 67

<HDLName>input</HDLName><Datatype><I16 />

</Datatype><Dir e c t i on>ToCLIP</ Di r e c t i on><SignalType>data</ SignalType>

</ S igna l>

<S igna l Name=” output0 ”><HDLName>output0</HDLName><Datatype><U64/>

</Datatype><Dir e c t i on>FromCLIP</ Di r e c t i on><SignalType>data</ SignalType>

</ S igna l>

<S igna l Name=” output1 ”><HDLName>output1</HDLName><Datatype><U64/>


</ S igna l>

<S igna l Name=” f u l l ”><HDLName> f u l l</HDLName><Datatype><Boolean />


</ S igna l>

</ S i g n a l L i s t>

<Inter faceType>Fabric</ Inter faceType>

<S i g n a l L i s t><S igna l Name=” Reset ”><HDLName>r s t</HDLName><DataType><Boolean />

</DataType><Dir e c t i on>ToCLIP</ Di r e c t i on><SignalType>r e s e t</ SignalType>

Marcus Stavstrom 68

</ S igna l></ S i g n a l L i s t>



</ CLIPDeclaration>

Marcus Stavstrom 69


Marcus Stavstrom 70

B Trigger unit

Hysteresis

input_signal

trig_level

trig_level_tolerance

trig_level_change

slope

transition

trig_level_1

trig_level_2

trig_level_3

trig_level_tol_1

trig_level_tol_2

trig_level_tol_3

trig_slope_1

trig_slope_2

trig_slope_3

trig_slope_1_doesnt_matter



trig_distance_1_min

trig_distance_2_min

trig_distance_1_max

trig_distance_2_max

trig_slope

trig_slope_doesnt_matter

trig_distance_min

trig_distance_max

xnorslope

trig_slope

trig_slope_doesnt_matter

or

andtransition

is_level_and_slope_satisfied

>=distance_counter

trig_distance_min

is_above_trig_distance_min

<=distance_counter

trig_distance_max

is_below_trig_distance_max

andis_above_trig_distance_min

is_above_trig_distance_max

is_trig_distance_satisfied

and is_one_trigger_condition_satisfiedis_level_and_slope_satisfied

is_trig_distance_satisfied

D

nr_of_trigger_conditions_satisfied

not

ortrigger_reset

is_below_trig_distance_max

is_one_trigger_consition_satisfied

trigger_done

and

Prio 2

"00" inc

2

D/=

D

Prio 0 => "00"

Prio 1 => "01"

trigger_reset

>=

nr_of_trigger_conditions_enabled

Prio

Prio 0 => "00"

Prio 1 => "01"

force_trig

or

2

’0’

’1’

D

nottrigger_done_reg

Prio

Prio 0 => "00"

Prio 1 => "01"

2

inc0x00000000

32 distance_counter

trigger_reset

is_one_trigger_condition_satisfied

’1’

trig_level_change

trig_level_change

input_signal

slope

transition

trigger_done


00

00

00

00

01

01

01

01

01

01

10

10

10

10

10

10

00

01

10

0

1

00

01

10

00

01

10

else => "10"

else => "10"

else => "10"

Inputs

input_signal

trigger_reset

force_trig

center_trig_at_slope

nr_of_trigger_conditions_enabled

trig_level_1

trig_level_2

trig_level_3

trig_level_tol_1

trig_level_tol_2

trig_level_tol_3

trig_slope_1

trig_slope_2

trig_slope_3




trig_distance_1_min

trig_distance_1_max

trig_distance_2_min

trig_distance_2_max

Outputs

trigger_done

clock_cycles_since_centered_slope

="00"


trigger_done

and

and

>=center_trig_at_slope


Prio

Prio 0 => "00"

Prio 1 => "01"

else => "10"

D

0x00000000

clock_cycles_since_centered_slope

00

01

10

2

inc

32

16

2

2

16

16

16

16

16

16

32

32

32

32

32

not

not

Marcus Stavstrom 71


Marcus Stavstrom 72

C Hysteresis unit

Prio

00

01

10

>=

<

input_signal

Prio 0 => "00"

Prio 1 => "01"

else => "10"

2

D

’1’

’0’

Prio

Prio 0 => "00"

Prio 1 => "01"

else => "10"

and

and

00

01

10

D

2

’1’

’0’ slope

xnor

and

trig_level_change not

not

not

D transition

add

sub

trig_level


input_signal

trig_level


trig_level_change

slope

transition

Inputs Outputs

16

16

16

Marcus Stavstrom 73


Marcus Stavstrom 74


D VRMS unit

DSP48E

A

B

CPCIN

PCOUTP

0x0

DSP48E

A

B

CPCIN

PCOUTP

0

1

0x0

0x0

0x0

andnotD

=0D

0

1inc

evaluate_sample

0

1

0x0

input_signal

evaluate_sample

D

0

1

output_signal

input_signal

evaluate_sample

Inputs

16

Outputs

output_signal 16

0

1

0x0

input_signal

evaluate_sample

SXT

SXT

30

18

20

48

47:32

Marcus Stavstrom 75


Marcus Stavstrom 76

E VPP unit

D

input_signal

evaluate_sample

Inputs

16

Outputs

16

0

1

max_and_min_done

max_and_min_done

16

16 vpp

Prio

Prio 0 => "00"

Prio 1 => "01"

else => "10"

D

00

01

10

0x8000

input_signal

max_and_min_done

max_tmp

>input_signal

max_tmp and

evaluate_sample

D

0

1

max_and_min_done

Prio

Prio 0 => "00"

Prio 1 => "01"

else => "10"

D

00

01

10

0x7FFF

input_signal

max_and_min_done

min_tmp

<input_signal

min_tmp and

evaluate_sample

sub

max

vpp

min

min

max

Marcus Stavstrom 77

Upphovsratt

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For ytterligare information om Linkoping University Electronic Press se forlagets hem-sida http://www.ep.liu.se/

Copyright

The publishers will keep this document online on the Internet – or its possible replace-ment – from the date of publication barring exceptional circumstances.

The online availability of the document implies permanent permission for anyone to read,to download, or to print out single copies for his/hers own use and to use it unchangedfor non-commercial research and educational purpose. Subsequent transfers of copyrightcannot revoke this permission. All other uses of the document are conditional upon theconsent of the copyright owner. The publisher has taken technical and administrativemeasures to assure authenticity, security and accessibility.

According to intellectual property law the author has the right to be mentioned whenhis/her work is accessed as described above and to be protected against infringement.

For additional information about the Linkoping University Electronic Press and its pro-cedures for publication and for assurance of document integrity, please refer to its wwwhome page: http://www.ep.liu.se/.

c© Marcus Stavstrom.

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