institutionen för systemteknik - diva...

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Design and implementation of a low-noise high-linearity

variable gain amplifier for high speed transceivers

Master Thesis in Division of Electronics Systems

at Linköping Institute of Technology by

Rehan Azmat

LiTH-ISY-EX--11/4543--SE 21st December, 2011

TEKNISKA HÖGSKOLAN LINKÖPINGS UNIVERSITET

Department of Electrical Engineering Linköping University S-581 83 Linköping, Sweden

Linköpings tekniska högskola Institutionen för systemteknik 581 83 Linköping

Master thesis performed in Fraunhofer Institute for Integrated Circuits (IIS)

Erlangen, Germany

Design and implementation of a low-noise high-linearity

variable gain amplifier for high speed transceivers

Master Thesis in Division of Electronics Systems at Linköping Institute of Technology

by

Rehan Azmat

LiTH-ISY-EX--11/4543--SE

Supervisor: Supervisor: Conrad Zerna Dr J. Jacob Wikner Optical Sensors and Communications Department of Electrical Engineering Fraunhofer Institute for Integrated Circuits (IIS) Linköping University Erlangen, Germany Linköping, Sweden [email protected] jacob.wikner @ liu.se

Examiner:

Dr. Mark Vesterbacka Department of Electrical Engineering (ISY) Linköping University Linköping, Sweden mark.vesterbacka @ liu.se

Date: 21st December, 2011.

Presentation Date

2011 – 12 - 21

Publishing Date (Electronic version) 2012 – 02 - 02

Department and Division Department of Electrical Engineering

Division of Electronics Systems Linköping University

SE-581 83, Linkoping, Sweden

URL, Electronic Version http://www.ep.liu.se

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73449

Publication Title

Design and implementation of a low-noise high-linearity variable gain amplifier for high speed

transceivers.

Author(s) Rehan Azmat

Abstract

The variable gain amplifier (VGA) is utilized in various applications of remote sensing and

communication equipments. Applications of the variable gain amplifier (VGA) include radar,

ultrasound, wireless communication and even speech analysis. These applications use the variable gain

amplifier (VGA) to enhance dynamic performance.

The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in

150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier

architectures are designed and compared. First architecture is an amplifier with diode connected load

and second architecture is a source degenerative amplifier. The performance of the amplifier with diode

connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise

and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage

variable gain differential amplifier is implemented with selected architecture.

The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to

22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth

achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35

mW at 1.8 V supply source.

Keywords

Transceiver, Analog, Amplifier, Linearity, Noise, Gain, Bandwidth, VGA, CMOS, HD3.

Language

English Other (specify below)

Number of Pages 95

Type of Publication Licentiate thesis Degree thesis

Thesis C-level Thesis D-level

Report

Other (specify below)

ISBN (Licentiate thesis)

ISRN: LiTH-ISY-EX--11/4543--SE

Title of series (Licentiate thesis)

Series number/ISSN (Licentiate thesis)

Linköping University Electronic Press

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© Rehan Azmat.



Abstract

The variable gain amplifier (VGA) is utilized in various applications of remote sensing andcommunication equipments. Applications of the variable gain amplifier (VGA) include radar,ultrasound, wireless communication and even speech analysis. These applications use thevariable gain amplifier (VGA) to enhance dynamic performance.The purpose of the thesis work is to implement a high linearity and low noise variable gainamplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two dif-ferent amplifier architectures are designed and compared. First architecture is an amplifierwith diode connected load and second architecture is a source degenerative amplifier. Theperformance of the amplifier with diode connected load is lower than the source degenerativeamplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerativeamplifier is selected for implementation. The three stage variable gain differential amplifieris implemented with selected architecture.The implemented three stage variable gain differential amplifier have gain range of−541.5 mdBto 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The −3 dBbandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is −45 dBc at250 mV and the power is 35 mW at 1.8 V supply source.

1

Acknowledgement

I owe my deepest gratitude to almighty Allah, who blessed me with strength, determinationand devotion to accomplish this thesis.It is an honour for me to work in Fraunhofer Institute for Integrated Circuits (IIS). I amheartily thankful to my supervisor, Conrad Zerna for giving me this opportunity. He receivedme at my arrival in Germany and arranged a nice accommodation for me. He also guidedme to solve the problems emerged during the thesis. This task would not have been possiblewithout his support, encouragement and guidance.I would like to thank my supervisor Dr J. Jacob Wikner, whose help, advice and supervisionwas invaluable throughout the thesis work.I also wish to thank my friend and colleague Choudhary Jabbar Younis for his encouragementto do a thesis outside Sweden. He also helped me during thesis application process. Weworked on same chip but different blocks. We had many cooperative discussions throughoutour thesis work.Finally, words alone cannot express the gratitude I owe to my family, especially my lovingparents for their support and prayers.

2

Contents

List of Abbreviations 3

List of Figures 5

List of Tables 7

1 Introduction 81.1 Overview of system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Analog Front End 112.1 Variable gain amplifier (VGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.1 Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.1.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.1.2 Non Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . 162.1.1.3 Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.1.1.4 Transistor type . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1.2 Simulation Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.1.2.1 Normal Operation Simulation . . . . . . . . . . . . . . . . . 19

2.2 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Variable Gain Amplifier Architectures 223.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.2 Selected Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.3 Differential amplifier with diode connected load . . . . . . . . . . . . . . . . . 233.4 Differential amplifier with source degeneration . . . . . . . . . . . . . . . . . . 283.5 Comparison of differential amplifier with diode connected load and differential

amplifier with source degeneration . . . . . . . . . . . . . . . . . . . . . . . . 333.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4 Three stage differential VGA with resistive network and source degener-ation 354.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354.2 Coarse stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.3 Fine stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.3.1 Fine stage version 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.3.1.1 Constant (gm) biasing circuit . . . . . . . . . . . . . . . . . . 424.3.1.2 Simulation results of the fine stage version 1 . . . . . . . . . 47

1

2

4.3.2 Fine stage version 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.3.3 Fine stage version 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.4 Output buffer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.5 Gain setting decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.6 Offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.6.1 First stage offset compensation amplifier . . . . . . . . . . . . . . . . . 624.6.2 Second stage offset compensation amplifier . . . . . . . . . . . . . . . 65

4.7 Three stage differential VGA with output buffer, gain setting decoder andoffset compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5 Layout design of the three stage variable gain differential amplifier withoutput buffer 715.1 Coarse stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725.2 Fine stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.3 Output buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.4 Three stage variable gain differential amplifier with output buffer, gain setting

decoder and offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . 79

6 Future work 846.1 VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.2 Fine stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.3 Coarse stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.4 Offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.5 Constant transconductance biasing circuit . . . . . . . . . . . . . . . . . . . . 856.6 Three stage variable gain differential amplifier with output buffer . . . . . . . 85

A Simulation Plan 86A.1 Normal Operation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

B Gain setting decoder verilogA code 89

The bibliography 93

3

List of Abbreviations

VGA: Variable gain amplifier.

AFE: Analog front end.

ADC: Analog to digital converter.

SNR: Signal to noise ratio.

DSP: Digital signal processor.

PAM: Pulse amplitude modulation.

EMI: Electromagnetic interference.

AVGA: Analog variable gain amplifier.

DVGA: Digital variable gain amplifier.

MOSFET: Metal oxide semiconductor field effect transistor.

DFT: Discrete Fourier transform.

AC: Alternating current.

DC: Direct current.

HD3: Third harmonic distortion.

CMFB: Common mode feedback.

dB: Decibel.

dBc: Carrier normalize decibel.

PMOS: P type metal oxide semiconductor transistor.

NMOS: N type metal oxide semiconductor transistor.

Vgs: Gate to source voltage.

R: Resistance.

gm: Transconductance.

RC: Resistance and capacitance.

List of Figures

1.1 Block diagram of the transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . 81.2 Pulse amplitude modulated signal. . . . . . . . . . . . . . . . . . . . . . . . . 91.3 Testing of the common mode rejection using cable clamp. . . . . . . . . . . . 10

2.1 Analog front end (AFE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2 Gain control curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3 Thermal Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.4 Long channel MOSFET, thermal noise model. . . . . . . . . . . . . . . . . . . 142.5 Reduction of the gate resistance to minimize the noise. . . . . . . . . . . . . . 152.6 Flicker noise spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.7 Non linearity phenomenon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.8 Common source amplifier with source regeneration. . . . . . . . . . . . . . . . 172.9 Analog-to-digital converter (ADC) block diagram. . . . . . . . . . . . . . . . 21

3.1 Transistor level schematic of the differential amplifier with diode connectedload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Small signal model of the differential amplifier with diode connected load. . . 233.3 Half circuit, small signal model of the differential amplifier with diode con-

nected load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.4 Transistor level schematic of the differential amplifier with diode connected

load and CMFB circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.5 Gain curves of the differential amplifier with diode connected load and CMFB

circuit in the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.6 Schematic of the differential amplifier with source degeneration. . . . . . . . . 283.7 Small signal model of the differential amplifier with source degeneration. . . . 293.8 Half circuit, small signal model of the differential amplifier with source de-

generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.9 Gain curves of the differential amplifier with source degeneration in the corner

analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1 Block diagram of the three stage differential amplifier with output buffer. . . 354.2 Schematic of the coarse stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.3 Gain curves of the coarse stage in the corner analysis. . . . . . . . . . . . . . 384.4 Schematic of the fine stage with constant gm biasing. . . . . . . . . . . . . . . 414.5 Schematic of the constant transconductance biasing circuit. . . . . . . . . . . 424.6 Schematic of the amplifier used in the constant transconductance biasing circuit. 434.7 Schematic of the complete constant transconductance biasing circuit. . . . . . 444.8 Gain curves of the fine stage with constant gm biasing in the corner analysis. 474.9 Gain setting curves of the fine stage with constant gm biasing in the corner

analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4

5

4.10 Bandwidth curve of the fine stage with constant gm biasing in all gain settings. 494.11 Schematic of the fine stage with high speed biasing transistors. . . . . . . . . 504.12 Gain curves of the fine stage with high speed biasing transistors in the corner

analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.13 Gain setting curves of the fine stage with high speed biasing transistors in

the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.14 Schematic of the fine stage with resized switching transistors. . . . . . . . . . 544.15 Gain curve without resized switching transistors. . . . . . . . . . . . . . . . . 554.16 Gain curve of the fine stage with resized switching transistors. . . . . . . . . . 554.17 Gain setting curves of the fine stage with resized switching transistors in the

corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.18 Schematic of the output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . 574.19 Gain curves of the output buffer in the corner analysis. . . . . . . . . . . . . . 584.20 Gain setting curves of the three stage variable gain differential amplifier with-

out gain setting decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.21 Gain setting curves of the three stage variable gain differential amplifier with

gain setting decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.22 Schematic of the offset compensation circuit. . . . . . . . . . . . . . . . . . . 614.23 Schematic of the first stage offset compensation amplifier. . . . . . . . . . . . 624.24 Gain curves of the first stage offset compensation amplifier in the corner

analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.25 Schematic of the second stage offset compensation amplifier. . . . . . . . . . . 654.26 Gain curves of the second stage offset compensation amplifier in the corner

analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.27 Gain curves of the three stage variable gain differential amplifier with im-

provements in the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . 684.28 Gain setting curves of the three stage variable gain differential amplifier with

improvements in the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . 694.29 Bandwidth curve of the three stage variable gain differential amplifier with

improvements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.1 Layout of the coarse stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725.2 Gain curves of the coarse stage layout in the corner analysis. . . . . . . . . . 735.3 Layout of the fine stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.4 Gain curves of the fine stage layout in the corner analysis. . . . . . . . . . . . 755.5 Layout of the output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.6 Gain curves of the output buffer layout in the corner analysis. . . . . . . . . . 785.7 Layout of the three stage variable gain differential amplifier. . . . . . . . . . . 795.8 Gain curves of the three stage variable gain differential amplifier layout in the

corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805.9 Gain setting curves of the three stage variable gain differential amplifier layout

in the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815.10 Bandwidth curve of the three stage variable gain differential amplifier layout

in the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

List of Tables

3.1 Simulation results of the differential amplifier with diode connected load andCMFB circuit in the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . 26

3.2 Simulation results of the differential amplifier with diode connected load andCMFB circuit in the montecarlo analysis. . . . . . . . . . . . . . . . . . . . . 27

3.3 Simulation results of the differential amplifier with source degeneration in thecorner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4 Simulation results of the differential amplifier with source degeneration in themontecarlo analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.5 Comparison of the simulation results of two differential amplifiers. . . . . . . 33

4.1 Gain settings with corresponding bandwidth of the coarse stage. . . . . . . . 374.2 Simulation results of the coarse stage in the corner analysis. . . . . . . . . . . 384.3 Simulation results of the coarse stage in the montecarlo analysis. . . . . . . . 394.4 Simulation results of the constant gm biasing circuit in the corner analysis. . 454.5 Comparison of simulation results of the fine stage with and without the con-

stant transconductance biasing circuit in the corner analysis. . . . . . . . . . 454.6 Comparison of simulation results of the fine stage with and without the con-

stant transconductance biasing circuit in the montecarlo analysis. . . . . . . . 464.7 Simulation results of the fine stage with constant gm biasing in the corner

analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.8 Simulation results of the fine stage with constant gm biasing in the montecarlo

analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.9 Simulation results of the fine stage with high speed biasing transistors in the

corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.10 Simulation results of the fine stage with high speed biasing transistors in the

montecarlo analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.11 Simulation results of the fine stage with high speed biasing transistors in the

montecarlo analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.12 Simulation results of the output buffer in the corner analysis. . . . . . . . . . 584.13 Simulation results of the output buffer in the montecarlo analysis. . . . . . . 594.14 Simulation results of the first stage offset compensation amplifier in the corner

analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.15 Simulation results of the first stage offset compensation amplifier in the mon-

tecarlo analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.16 Simulation results of the second stage offset compensation amplifier in the

corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.17 Simulation results of the second stage offset compensation amplifier in the

montecarlo analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.18 Simulation results of the three stage variable gain differential amplifier with

improvements in the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . 68

6

7

4.19 Simulation results of the three stage variable gain differential amplifier withimprovements in the montecarlo analysis. . . . . . . . . . . . . . . . . . . . . 69

5.1 Comparison of simulation results of the coarse stage schematic and layout inthe corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.2 Comparison of simulation results of the coarse stage schematic and layout inthe montecarlo analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.3 Comparison of simulation results of the fine stage schematic and layout in thecorner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.4 Comparison of simulation results of the fine stage schematic and layout in themontecarlo analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.5 Comparison of simulation results of the output buffer schematic and layoutin the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.6 Comparison of simulation results of the output buffer schematic and layoutin the montecarlo analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.7 Comparison of simulation results of the three stage variable gain differentialamplifier schematic and layout in the corner analysis. . . . . . . . . . . . . . . 80

5.8 Comparison of simulation results of the three stage variable gain differentialamplifier schematic and layout in the montecarlo analysis. . . . . . . . . . . . 83

Chapter 1

Introduction

This master thesis presents the design of a variable gain amplifier (VGA) for an analog frontend (AFE) of a high speed transceiver. The variable gain amplifier (VGA) is designed tokeep the input amplitude of the analog-to-digital converter (ADC) in range. The designerkeeps the linearity of the variable gain amplifier (VGA) high. The Variable gain amplifier(VGA) should also have low noise figure, so that the performance of the analog-to-digitalconverter (ADC) should not be degraded. Two amplifier architectures are designed ontransistor level. The architecture with higher performance in terms of linearity, noise andbandwidth is chosen for implementation.

1.1 Overview of system

The block diagram of the system is shown in figure 1.1. The system consists of the followingmain building blocks.

• Transmitter.

• Channel.

• Receiver.

PAM8Transmitter

AFE DSP

Receiver

Channel PAM86

Figure 1.1: Block diagram of the transceiver.

A digital signal is transmitted over the twisted copper pair channel and the noisy signalis received at the receiver by the analog front end (AFE). This noise is inserted by thechannel. The analog front end (AFE) processes the received noisy signal to convert it intopure digital signal again and send it to the digital signal processor (DSP) for processing ofthe information. These blocks are discussed further in the following sections.

8

CHAPTER 1. INTRODUCTION 9

1.2 Transmitter

The pulse amplitude modulated signal is transmitted over the channel by the transmitter.The pulse amplitude modulation is a technique of encoding information signal into amplitudeof pulses. The differential pulse amplitude modulated signal (PAM-8) transmitted over thechannel is shown in figure 1.2. This signal is called PAM-8, as it consists of eight differentamplitude levels of a pulse. PAM-8 encodes three bits in a single pulse.

Figure 1.2: Pulse amplitude modulated signal.

Bandwidth required for PAM-8 signal is given by the following equation 1.1.

BWPAM =1

2Tsym, (1.1)

where Tsym is the time period for one symbol. It is chosen for this system as it givesefficient design with the 6-bit analog-to-digital converter (ADC). With increase in the levelsof PAM signal, the SNR decreases and data rate increases. This increases the specificationrequirement on the variable gain amplifier (VGA) and the analog-to-digital converter (ADC).

1.2. TRANSMITTER

CHAPTER 1. INTRODUCTION 10

1.3 Channel

The channel is a twisted-pair copper wire. The twisted-pair cable have the ability to sig-nificantly cancel out the electromagnetic interference (EMI) induced in the channel fromthe external sources. This is called differential-mode transmission because the twisted-pairconsist of equal and opposite signals, which are differential. The receiver detects that signal.The noise and EMI sources induces noise in the channel by coupling the electric or magneticfield, which induce same noise signal in both wires of the twisted-pair. Thus, the noiseinduced is common signal in the channel, which is suppressed by the differential receiver.This suppression of the common signal depends on the common mode rejection ratio of theinput amplifier.The common mode rejection ability of the receiver is tested by the cable clamp, as shownin figure 1.3. The cable clamp is a 300 mm long clamp used to induce wide band commonmode voltage of amplitude 1 V and frequency 1 MHz to 1.6 GHz in the channel [1]. Thiscommon mode voltage is generated by the sweeping frequency of the signal generator, from1 MHz to 1.6 GHz, connected to the cable clamp shown in figure 1.3.

Cable ClampTwisted Pair

TRANSMITTER

Twisted Pair

Signal Generator

1 to 200 MHz @ 1V RECEIVER

Figure 1.3: Testing of the common mode rejection using cable clamp.

1.4 Receiver

The receiver consists of the following main building blocks shown in figure 1.1.

• Analog Front End (AFE).

• Digital Signal Processor (DSP).

Analog front end (AFE) is an electronic circuit between the channel and the digital sig-nal processor (DSP). The AFE conditions the analog signal received from the channeland performs the analog-to-digital (A/D) conversion. It is used in this project, to pro-duce every bit of the analog-to-digital converter (ADC) in the middle of the symbolicperiod. It consists of two main building blocks: A variable gain amplifier (VGA) andan analog-to-digital converter (ADC).

Digital signal processor (DSP) is a digital processor which is used to process the infor-mation received from the conditioned digital signal of the analog front end (AFE). Itis used for equalization, non-linearity compensation, decoding, descrambling and for-ward error correction of the digital signal received from the analog-to-digital converter(ADC).

1.3. CHANNEL

Chapter 2

Analog Front End

The receiver consists of the analog front end (AFE) and the digital signal processor (DSP).The analog front end (AFE) conditions the analog signal received from the channel andconverts it into a digital signal, for the digital signal processing (DSP).

VGA

ADC

Analog Front End

Receiver

5

6DifferentialInput

DigitalOutput

Gain Control

DSP

Figure 2.1: Analog front end (AFE).

Following are the main building blocks of the analog front end (AFE) shown in figure 2.1.

• Variable gain amplifier (VGA)

• Analog-to-digital converter (ADC)

Variable gain amplifier (VGA) conditions the signal received from the channel to utilizefull dynamic range of the analog-to-digital converter (ADC).

Analog-to-digital converter (ADC) converts this conditioned signal received from thevariable gain amplifier (VGA) into the digital signal for the digital signal processing.

11

CHAPTER 2. ANALOG FRONT END 12

2.1 Variable gain amplifier (VGA)

The variable gain amplifier (VGA) is utilized in many applications for decades, which in-cludes radar, ultrasound and wireless communication. The purpose of the variable gainamplifier (VGA) is to improve the dynamic performance. Broadly speaking, the variablegain amplifier (VGA) is used in two different situations. The first is to match the inputsignal level to full scale input level of a device like an analog-to-digital converter (ADC) ora FM-discriminator. The second in which the fixed input voltage is scaled to compensatevariable losses, like transmission line voltage level adjustment.The variable gain amplifier (VGA) is a signal conditioning circuit with adjustable gain. De-pending upon the nature of the gain control signal, the variable gain amplifier (VGA) isdivided into two categories.

• Analog variable gain amplifier (AVGA)

• Digital variable gain amplifier (DVGA)

The gain control in the analog variable gain amplifier (AVGA) is controlled by the analogvoltage and the gain is linear function of the analog control voltage signal. The gain levelsare continuous, as shown in figure 2.2(a).The gain control in the digital variable gain amplifier (DVGA) is controlled by the digitalcontrol word and the gain levels are stepped as shown in figure 2.2(b).

0 0.2 0.4 0.6 0.8 1 1.2

15

10

5

0

5

10

15

20

Gain Linear in dB

VGain (V)

Gain

(dB)

0 1 2 3 4 5 6

15

10

5

0

5

10

15

Gain in discrete steps

Gain Code

Gai

n (d

B)

00001 00010 00011 00100 00101 0011000000

(a) Gain versus Gain control voltage

0 0.2 0.4 0.6 0.8 1 1.2

15

10

5

0

5

10

15

20

Gain Linear in dB

VGain (V)

Gain

(dB)

0 1 2 3 4 5 6

15

10

5

0

5

10

15

Gain in discrete steps

Gain Code

Gai

n (d

B)

00001 00010 00011 00100 00101 0011000000

(b) Gain versus Gain control code

Figure 2.2: Gain control curves.

The analog variable gain amplifier (AVGA) is compact in size as compared to the digitalvariable gain amplifier (DVGA). Whereas, in the digital variable gain amplifier (DVGA)different parameters of the gain control could be observed.This project implements the digital variable gain amplifier (DVGA), which is used to adjustthe level of the signal received from the channel.

2.1. VARIABLE GAIN AMPLIFIER (VGA)


2.1.1 Design Challenges

In this project, there are few challenges, which the designer has to take care of duringdesigning and implementation of the variable gain amplifier (VGA). These parameters arediscussed following.

2.1.1.1 Noise

The noise is an unwanted signal, which degrades the performance of the system. It limitsthe signal level which could be processed by the system with acceptable quality. The noise isimportant for the analog design because it provides the trade-off between power dissipation,speed and linearity. Noise also degrades the dynamic range of the receiver [2]. The totalnoise figure, in a multi stage amplifier, is given by the Friis formula given below.

NFT = NF1 +NFr + 1

Av1, (2.1)

where NFT is the total noise figure, NF1 is the noise figure of the first amplifier, NFr is thenoise figure of rest of the amplifiers and Av1 is the gain of the first amplifier. This equationshows that the gain of the first amplifier should be low for lower noise figure.The analog signal in the variable gain amplifier (VGA) is corrupted by two types of noise.

• Electronic device noise

• Environmental Noise

The electronic device noise is generated by resistors, transistors and other electronic devices.

The environmental noise is random disturbance, which is experienced by the electroniccircuit through the supply lines or the substrate.

1. Thermal Noise

• Resistor thermal noise is generated due to the random motion of the electrons,which produces the fluctuation in the voltage across the resistor even in zero av-erage current [2]. The spectrum of the thermal noise is shown in figure 2.3(b).The thermal noise generated by the resistor can be modelled, by a voltage sourcein series as shown in figure 2.3(a).

- +R

Vn2

Noiseless Resistor

(a) Equivalent resistive thermalnoise source.

4KTR

f (Hz)

S v (f)

(b) Spectrum of the resistancethermal noise.

Figure 2.3: Thermal Noise.



The thermal noise voltage of the resistor is given by the following formula [2].

V̄n = 4kTR (V 2/Hz), (2.2)

where k is the Boltzmann constant of value 1.38∗10−23J/K, T is the temperaturein Kelvin and R is the resistance in ohms.

• MOSFET thermal noise is generated mostly by the channel. The noise modelfor a long channel device is shown in figure 2.4.

In2

logf (Hz)

20logVn2

Figure 2.4: Long channel MOSFET, thermal noise model.

The formula of the noise current source is [2]:

In = 4kRTγgm, (2.3)

where k is the Boltzmann constant of value 1.38x10−23 J/K, T is the tempera-ture in Kelvin, R is the channel resistance in ohms, γ is 2/3 for the long channeldevices and approximately 2.3 for the sub-micron devices and gm is the transcon-ductance of the MOSFET in 1/ohm. The channel noise can only be controlled bythe transconductance of the MOSFET. As given by the formula that In is directlyproportional to gm. The gate, drain and source terminals have finite resistivitywhich also introduce the noise in the electronic circuits. In the wide transistors,the source and the drain resistances are negligible while the gate resistance mayremain significant.



The noise generated by the gate resistance is improved by the proper layout. Anexample is shown in figure 2.5. In figure 2.5(a) the gate resistance is reduced byconnecting the gate terminal on both sides and in figure 2.5(b) the gate resis-tance is reduced by using the folded transistor. Each technique reduces the gateresistance by two times [2].

(a) Reduction of the gate resistanceby connecting the gate terminals onboth sides.

(b) Reduction of the gateresistance by the foldedtransistor.

Figure 2.5: Reduction of the gate resistance to minimize the noise.

2. Flicker Noise

The interface between the gate oxide and the substrate consists of many danglingbonds at extra energy state [2]. The charges moving at this interface, is trapped ran-domly and released, causing the flicker noise. This is believed that the trapping is notthe only phenomenon for the flicker noise. The flicker noise is modelled by a seriesvoltage source at the gate terminal of the MOSFET. The approximate formula for theflicker noise is [2]:

V 2n =

K

CoxWL

1

f, (2.4)

where K is the process dependent constant 10−25 V 2F , Cox is the oxide capacitancein farad, W is the width of the transistor in meters, L is the length of the transistorin meters and f is the frequency in hertz. By the above inverse relationship of thefrequency, this noise is also called 1/f noise. This relationship is also shown, in thefrequency spectrum of the flicker noise, in figure 2.6. The inverse relation of the WLsuggest that to reduce the 1/f noise, the device size should be increased. Therefore,in the low noise circuits, the transistors having large area are used.

In2

logf (Hz)

20logVn2

Figure 2.6: Flicker noise spectrum.



2.1.1.2 Non Linearity

The phenomenon of the non linearity in the differential amplifier is shown in figure 2.7.As the signal amplitude increases, the non linearity comes into play [2]. At the smallsignal amplitudes, the output is approximately exact replica of the input but as the signalamplitude increases from certain limit, the amplifier exhibit saturation, which results in thenon linearity as shown in figure 2.7.

(a) Small signal response of the dif-ferential amplifier.

(b) Large signal response of the differ-ential amplifier.

Figure 2.7: Non linearity phenomenon.

The analog circuit requires relatively small non linearity. The input/output characteristicsof the amplifier could be approximated by the Taylor expansion as:

y(t) = α1x(t) + α2x2(t) + α3x

3 + ..... (2.5)

At small x,y(t) = α1x(t), (2.6)

where α1 is the small signal gain, in the vicinity of x ≈ 0. The non linearity of the amplifieris also determined by measuring the harmonics of the output signal at the sinusoidal input.

y(t) = α1Acosωt+ α2A2cos2ωt+ α3A

3cos3ωt+ ..... (2.7)

By the above equation it is observed that the higher order terms results in the higherharmonics. These terms are cause of the harmonic distortion, which is quantified by thetotal harmonic distortion (THD). The total harmonic distortion is determined by summingall the harmonics and normalize the result with the power of the fundamental.The input/output characteristics of the differential amplifier shows the odd symmetric andthe Taylor expansion results in only the odd order terms, all the even order terms are zeroas shown in the following equation.

y(t) = α1Acosωt+ α3A2cos2ωt+ α5A

3cos3ωt+ ..... (2.8)

This is very important property of the differential amplifier, which shows that, it produceslower distortion then the common source amplifier.For higher linearity of the multi stage amplifiers, the gain of the first stage should be low.This will secure the following amplifiers to be saturated and degrades the linearity of thecircuit. But as discussed earlier, in the previous section 2.1.1.1, that higher the gain of thefirst stage, the lower the noise figure. So, there is a trade off in setting the gain of the multistage amplifiers.



• Linearisation Technique

The principle of the linearisation is to reduce the gain dependency of the amplifier onthe input amplitude, by making the gain independent of the bias current. For high speedapplications, the simplest method for the linearisation is the source degeneration. The sourcedegeneration utilizes a linear resistor at the source terminal as shown in figure 2.8. Thisresistor reduces the swing at the gate to source, making the input/output characteristicsmore linear.

RD

RS

Vout

Vin

VDD

Figure 2.8: Common source amplifier with source regeneration.

The overall transconductance of the amplifier shown in figure 2.8 is :

Gm =gm

1 + gmRs, (2.9)

where the body effect is neglected.Note that the linearisation depends upon gmRs not on Rs alone.



2.1.1.3 Mismatch

The two identical MOSFETs during the fabrication suffers from the mismatch, due to un-certainty in the manufacturing process. This mismatch results in the random variations inthe implant density and the oxide thickness [4]. These parameters result in variations inthe lengths, widths, charge mobility, threshold voltage and oxide capacitance. The draincurrent of the MOSFET in the saturation is given by the following equation [2].

ID =1

2µCox

W

L(VGS − VTH)2 (2.10)

The mismatch causes change in the drain current or the gate to source voltage of the identicaltransistors. It results in the following three phenomenons in the differential amplifiers.

1. DC offset.

2. Finite even order harmonic distortion.

3. Lower common mode rejection.

The mismatch can be reduced by increasing the length and the width. This decrease is dueto the reduction in the relative mismatch with the increment in the length and the width.The decrease of the relative mismatch is due to the fact that with the increase of the area,the averaging of the random variation is higher. The mismatch could also be reduced bybiasing the transistors in the weak inversion. In the weak inversion, the change of the outputcurrent, due to the input voltage, is small. So, the effect of the mismatch will be small.

2.1.1.4 Transistor type

The NMOS transistors are used as the input transistors. These transistors are high speedas compared to the PMOS. The 1/f noise produces by the NMOS does not effect this highspeed design, because it has low amplitude at high frequencies. This is shown in figure 2.6.The bulk variations also does not degrade the performance in this design, as the bulks areconnected to the supply voltage.



2.1.2 Simulation Plan

The testing of the variable gain amplifier (VGA) is planned in the initial phase of this project,in which, the types of the test signal, the simulations to test the different parameters andthe formula for these parameters are finalized.After completing the circuit, ten simulations are performed in the nominal, corner andmontecarlo with the different gain settings. The corner analysis is performed in the tendifferent corners. These corners use the supply voltage of 1.6, 1.7, 1.8 and 1.9 Volts. Thetemperature values used in the corners are: -40, 25 and 125. Different transistors, resistorsand capacitors models are used in the different corners.Following are the simulations used to test the variable gain amplifier (VGA).

2.1.2.1 Normal Operation Simulation

The following simulations use the sinusoidal test signal for the normal operation of thevariable gain amplifier (VGA).

1. DC SimulationThe following parameters will be checked by the DC simulation.

• Power consumption is measured by multiplying, the value of the DC supplyvoltage source with the current drawn from that source by the amplifier.

• Output common mode voltage is measured by taking the average of thedifferential output voltage.

• Output offset voltage is measured by taking the difference of the output DCvoltage.

• Operating regions of transistors is measured by the saved OP parameters,to check the correct overdrive and reserve voltages.

2. Transient simulationThe following parameters will be checked by the transient simulation.

• Third harmonic distortion is measured by using the DFT on the output signalat the input sine with frequency of 500 MHz and amplitude of 10 mV. Determinesthe magnitude of the third harmonic and subtracts it from the fundamental.

• Output differential voltage is measured by taking the maximum difference ofthe output voltage.

3. Transient and DC simulationThe following parameter requires the transient and the DC simulation during thetesting.

• Input referred offset voltage is measured by dividing the output offset voltageby the gain of the amplifier.

4. AC simulationThe following parameters will be checked by the AC simulation.

• Bandwidth is measured by the −3 dB crossing of the output signal at highfrequency.

• Lower cut-off frequency is measured by the −3 dB crossing of the outputsignal at low frequency.

• Transfer function is measured by the AC sweep from 0 to 10 GHz.



• AC gain is measured by the sine input of amplitude 500 mV and frequency10 MHz.

5. Noise simulationThe following parameter will be checked by the noise simulation.

• Input referred noise power is measured by integrate the noise spectrum overthe normalized transfer function of the amplifier.

6. Parametric TransientThe following parameter will be checked by the parametric transient simulation.

• Transient gain is measured by applying the input sine wave at frequencies: 100,400 and 800 MHz with amplitudes: of 50, 350 and 600 mV.

7. Parametric Transient and DCThe following parameters will be checked by the parametric, the transient and the DCsimulations.

• Output differential voltage is measured to check the waveform of the outputvoltage for the spikes.

• Gain is measured by changing the five bits digital control signal and apply thesmall DC input signal. This simulation is performed to check the output for themonotonicity, the step size and the gain range.



2.2 Analog-to-digital converter

The analog-to-digital converter (ADC) is a device, which is used to convert the continuestime analog signal into a digital signal. In this project, the analog-to-digital converter (ADC)is used to reproduce the digital signal transmitted over the channel by the transmitter. It ismain building block of the analog front end (AFE). The signal conditioned by the variablegain amplifier (VGA) is received by the analog-to-digital converter (ADC) and is convertedinto a digital signal in such a way, that each bit is taken at the middle of its symbol period.This signal is then send to the digital signal processor (DSP).

TrackAndHold

Encoder

Com

para

tor

Prea

mpl

ifier

Ar

ray

Analog to Digital Converter

Input conditioned signal from VGA

Digital output6363

Figure 2.9: Analog-to-digital converter (ADC) block diagram.

The analog-to-digital converter consists of the following main building blocks, also shown infigure 2.9:

• Track and Hold (TnH).

• Pre-amplifier Array.

• Comparator.

• Encoder.

Track and Hold is a circuit, which track the input continues time analog signal for specifictime period called tracking period and then hold its value after the tracking periodfor specified time period called hold period. The purpose of the track and hold inthe analog-to-digital converter is to eliminate the variations in the input analog signalwhich corrupt the conversion process.

Preamplifier Array is an amplifier array, which includes the averaging and the interpo-lation. It is used to reduce the offset. It increases, the difference between the inputsampled signal and the reference voltage, so that the comparator operation will notbe in the metastable state.

Comparator is a circuit, which compares two signals and switches its output to show thatwhich is greater. It receives the signal from the pre-amplifier array and produces onebit digital signal.

Encoder is a digital circuit, which converts one form of the code into another. It is usedin the analog-to-digital converter (ADC) for the space saving.

2.2. ANALOG-TO-DIGITAL CONVERTER

Chapter 3

Variable Gain AmplifierArchitectures

3.1 Introduction

There are two approaches, widely used to design the variable gain amplifier (VGA) [3].

• Translinear amplifiers.

• Exponential amplifiers.

Translinear amplifiers uses the diode equation, which gives the relationship between thejunction current and the base voltage in a bipolar device. This is an exponentialcurrent-voltage relationship which is called translinear.

Exponential amplifiers consists of a precision-matched R-xR ladder attenuator and aninterpolator, followed by a fixed gain amplifier. The relationship of the input and theoutput voltage is exponential.

3.2 Selected Architectures

Different research papers are studied and two differential amplifier architectures are selectedfor implementation on transistor level. These architectures are selected by observing differentparameters of the variable gain amplifier (VGA). These parameters include: bandwidth,linearity, gain range, gain step, noise, gain error, power consumption and area. Higherpriority is given to: bandwidth, linearity and gain range.The two selected architectures are:

1. Differential amplifier with diode connected load.

2. Differential amplifier with source degeneration.

The first architecture is a translinear amplifier and the second is an exponential amplifier.These architectures are discussed in the subsequent sections.

22

CHAPTER 3. VARIABLE GAIN AMPLIFIER ARCHITECTURES 23

3.3 Differential amplifier with diode connected load

First architecture designed is a differential amplifier with diode connected load. The differ-ential amplifier with diode connected is shown in figure 3.1.

Figure 3.1: Transistor level schematic of the differential amplifier with diode connected load.

The biasing current is produced by the external biasing circuit. This amplifier provides thevoltage gain, which is ideally independent of the temperature and the process variations [5].The small signal model of the differential amplifier is shown in figure 3.2.

Figure 3.2: Small signal model of the differential amplifier with diode connected load.

3.3. DIFFERENTIAL AMPLIFIER WITH DIODE CONNECTED LOAD


By the half circuit concept, above small signal model can be reduced to the followingsmall signal model, shown in figure 3.3.

Figure 3.3: Half circuit, small signal model of the differential amplifier with diode connectedload.

The voltage gain is determined by the small signal model, which is [5]:

Av =gm−input

gm−load=

√(W/L)input(W/L)load

IC1

IC2, (3.1)

where gm−input is the transconductance of the input transistors, gm−load is the transcon-ductance of the load transistors, IC1 is current in the input transistors and IC1 is current inthe diode connected load transistors. By above equation, it is noted that the voltage gain isideally independent of the process and the temperature variations, but still, it depends uponthe transistor size and the biasing currents. The transistor size and the current, changeswith the process or the temperature. Also, by the above equation, it is observed that to in-crease the voltage gain, the diode connected load should have smaller size and lower currentthen the input transistors.The linearity of the amplifier depends upon the current density. Linearity of this differentialamplifier is low at small gain values because of the small current densities of the input andthe load transistors.



The differential amplifier with diode connected load is implemented on transistor level.This architecture has a drawback that the common mode output voltage level varies in thecorner analysis. The gain variations are also increased by these changes of the commonmode output voltage level over the corners. To solve this problem, the common mode feed-back (CMFB) circuit is used with this architecture. This differential amplifier with commonmode feedback (CMFB) circuit is shown in figure 3.4.

Figure 3.4: Transistor level schematic of the differential amplifier with diode connected loadand CMFB circuit.

In the above figure 3.4, there is an ideal amplifier used in the CMFB circuit. This idealelement is used to check the behaviour of the amplifier with the CMFB circuit.The common mode feedback (CMFB) circuit utilizes a high gain amplifier, to keep the com-mon mode output voltage level within limit over all corners. The common mode feedback(CMFB) circuit amplifies the difference between the average of the differential output andthe reference voltage, which is “Vcm“ in this case [7], as shown in figure 3.4. The Vcm isthe common mode voltage at the output of the differential amplifier. For the averaging ofthe differential output voltage, a resistor divider is used. Any change in the common modeoutput voltage is compensated by changing the biasing voltage of the PMOS transistors. Inthis way, the variations in the common mode output voltage are reduced.



The simulation results of the differential amplifier with common mode feedback (CMFB)circuit in the corner analysis are given in the following table 3.1.

Table 3.1: Simulation results of the differential amplifier with diode connected load andCMFB circuit in the corner analysis.

Parameters Min Typ Max StddevPower consumption (W) 5.73 m 7.83 m 10.27 m 1.449 mOutput common mode voltage (V) 1.407 1.409 1.411 1.325 mTransient Gain (Linear) 2.679 4.64 6.023 1.196AC Gain (dB) 9.006 12.51 14.03 1.306Bandwidth (Hz) 2.231 G 3.064 G 3.809 G 465.4 MThird harmonic distortion (dBc) −45.76 −32.91 −25.98 7.586Input referred noise power (dBc) −150 −145.1 −140.4 2.952

The gain curves in the corner analysis are shown in the following figure 3.5

Wed Nov 9 17:24:05 2011

Transfer_Function

Name Corner Vsupply temperature cornerNr

Transfer_Function

Transfer_Function C10 1.9 -40 10

Transfer_Function C09 1.6 125 9









(dB)

-2.5

0.0

2.5

5.0

7.5

10.0

12.5

15.0

freq (Hz)10

010

110

210

310

410

510

610

710

810

910

10

Page 1 of 1

Figure 3.5: Gain curves of the differential amplifier with diode connected load and CMFBcircuit in the corner analysis.



The simulation results of the differential amplifier with common mode feedback (CMFB)circuit in the montecarlo analysis are given in the following table 3.2.

Table 3.2: Simulation results of the differential amplifier with diode connected load andCMFB circuit in the montecarlo analysis.

Parameters Min Mean Max SigmaPower consumption (W) 6.334 m 7.253 m 8.325 m 373.9 uOutput common mode voltage (V) 1.41 1.41 1.41 40.3 uOutput Offset (V) −31.09 m −1.124 m 25.75 m 12.89 mTransient Gain (Linear) 4.078 4.497 4.997 203.5AC Gain (dB) 12.81 13.05 13.23 82.2 mBandwidth (Hz) 2.556 G 2.725 G 2.963 G 78.47 MThird harmonic distortion (dBc) −31.51 −30.76 −30.21 241.5 mInput referred noise power (dBc) −149.7 −148.7 −148.8 349.2 m



3.4 Differential amplifier with source degeneration

Second architecture designed is the differential amplifier with source degeneration. The dif-ferential amplifier with source degeneration is shown in the following figure 3.6.

Figure 3.6: Schematic of the differential amplifier with source degeneration.

The source degeneration improves the linearity of the differential amplifier by reducing thegate to source voltage swing and making input/output characteristics more linear [2]. Thisdifferential amplifier with source degeneration have two tail current sources. One extra cur-rent source reduces the voltage headroom by the source resistor. It also increases the noisegenerated by the differential amplifier, which is a disadvantage of this architecture. Increasein the noise is due to the differential error produced by the two tail current sources.

3.4. DIFFERENTIAL AMPLIFIER WITH SOURCE DEGENERATION


The small signal model of the differential amplifier with source degeneration is shown infigure 3.7.

Figure 3.7: Small signal model of the differential amplifier with source degeneration.

Using the half circuit concept, above small signal model can be reduced into the followingsmall signal model, shown in figure 3.8.

Figure 3.8: Half circuit, small signal model of the differential amplifier with source degen-eration.



The voltage gain of the differential amplifier with source degeneration is derived fromabove small signal model, shown in figure 3.8. This voltage gain is given by the followingformula by neglecting ro of the input transistor:

Gm =gm

1 + gmRs. (3.2)

Av = GmRD =gmRD

1 + gmRs, (3.3)

where gm is the transconductance of the input transistor, Rs is the source degenerationresistance, RD is the drain resistance.The above gain equation shows that, if the value of the resistance Rs and RD is large enoughthen gain will depend only upon the ratio of RD/Rs. This makes the differential amplifierindependent of the process or the temperature changes. But in this thesis, Rs is not highenough to use this approximation. This differential amplifier with source degeneration isimplemented on transistor level.Simulation results of this architecture in the corner analysis are given in the following ta-ble 3.3.

Table 3.3: Simulation results of the differential amplifier with source degeneration in thecorner analysis.

Parameters Min Typ Max StddevPower consumption (W) 1.437 m 1.816 m 2.575 m 361.6 uOutput common mode voltage (V) 1.118 1.401 1.554 142.7 mTransient Gain (Linear) 2.582 3.672 4.593 753.4 mAC Gain (dB) 8.524 11.47 13.71 1.961Bandwidth (Hz) 5.635 G 6.943 G 9.185 G 1.131 GThird harmonic distortion (dBc) −62.17 −55.12 −48.98 4.444Input referred noise power (dBc) −146.1 −142.7 −137.7 3.13



The gain curves in the corner analysis are shown in the following figure 3.9.

Thu Nov 10 12:23:35 2011

Transfer_Function

Name Corner

Transfer_Function

Transfer_Function C01










5.0

10.0

15.0

(dB

)

-10.0

-5.0

0.0

101

102

103

104

1010

1011

105

106

107

108

109

freq (Hz)10

0

Page 1 of 1Figure 3.9: Gain curves of the differential amplifier with source degeneration in the corneranalysis.



Simulation results of this architecture in the montecarlo analysis are given in the followingtable 3.4.

Table 3.4: Simulation results of the differential amplifier with source degeneration in themontecarlo analysis.

Parameters Min Mean Max SigmaPower consumption (W) 1.587 m 1.822 m 2.097 m 101.7 uOutput common mode voltage (V) 1.341 1.4 1.452 22.33 mOutput Offset (V) -40.48 m -2.59 m 51.04 m 18.43 mTransient Gain (Linear) 2.861 3.72 4.781 365.4 mAC Gain (dB) 10.94 11.47 11.85 184.9 mBandwidth (Hz) 6.877 G 6.946 G 7.021 G 27.69 MThird harmonic distortion (dBc) −60.2 −25.36 −11.34 9.624Input referred noise power (dBc) −143 −142.7 −142.3 129.6 m



3.5 Comparison of differential amplifier with diode con-nected load and differential amplifier with sourcedegeneration

Following is the table for comparison of the two architectures, implemented on transistorlevel. In table 3.5, all values are for the worse case in the corner analysis, except the outputoffset which is the sigma value in the montecarlo analysis.

Table 3.5: Comparison of the simulation results of two differential amplifiers.

Parameters Architecture 1 Architecture 2Power consumption (W) 10.27 m 2.575 mOutput common mode voltage (V) 1.407 1.118Transient Gain (Linear) 2.679 2.582AC Gain (dB) 9.006 8.524Bandwidth (Hz) 2.231 G 5.635 GThird harmonic distortion (dBc) −25.98 −48.98Output offset (V) −31.09 m −40.48 m

Power Consumption is higher in the differential amplifier with diode connected load be-cause of an extra circuit for the common mode feedback (CMFB), as shown in fig-ure 3.4. Whereas, in the differential amplifier with source degeneration does not needthe common mode feedback (CMFB). Also, the diode connected load consumes powertoo, which is not in the case of the differential amplifier with source degeneration.Another reason for increase in the power consumption is that, to get higher band-width and linearity, the biasing current is increased, which results in higher powerconsumption.

Output common mode voltage is more stable in the differential amplifier with diodeconnected load as it uses the common mode feedback (CMFB) circuit, shown in fig-ure 3.4. It reduces the variations in the output common mode voltage. This could beobserved in the simulation results of table 3.1.

Transient Gain is higher in the differential amplifier with diode connected load as com-pared to the differential amplifier with source degeneration. It has high gain becauseof the PMOS at the drain terminal of the input transistor, as shown in figure 3.1.But the gain of the differential amplifier can be increased by reducing the bandwidth.Also, higher gain reduces the linearity.

Bandwidth is lower in the differential amplifier with diode connected load because of theloading at the output, by the diode connected transistors and the PMOS. Both reducesthe bandwidth by increasing the capacitance at the output terminal.

Third harmonic distortion is higher in the differential amplifier with source degener-ation because of the source resistor used in this architecture. This source resistorreduces the gate to source voltage swing and makes the input/output characteristicsmore linear [2]. The simulations showed that the linearity of the differential amplifierwith diode connected load could be improved by increasing the current density of theamplifier, which results in higher power consumption.

3.5. COMPARISON OF DIFFERENTIAL AMPLIFIER WITH DIODE CONNECTEDLOAD AND DIFFERENTIAL AMPLIFIER WITH SOURCE DEGENERATION


Output offset of the differential amplifier with diode connected load is small, as it havebigger transistors as compared to the differential amplifier with source degeneration.The increase in the size of the transistors, reduces the relative mismatch between thedifferential pair by increasing the averaging of the random variations.

3.6 Conclusion

The differential amplifier with source degeneration is preferred architecture because it haslower power consumption, higher gain bandwidth product and higher linearity. It is selectedfor the implementation of the variable gain amplifier (VGA) for the transceiver application.Although, output offset of this architecture is high as compared to the differential amplifierwith diode connected load. To compensate this drawback, the offset compensation circuitwill be used. It will reduce the offset by subtracting it at the input of the amplifier chain. Thecost have to be paid for selecting this architecture is: the common mode voltage variationsin the corner analysis and the noise generated by the tail current sources. Both of thesevalues are within limits, so no need for improvement.

3.6. CONCLUSION

Chapter 4

Three stage differential VGAwith resistive network andsource degeneration

4.1 Introduction

The three stage variable gain differential amplifier with output buffer is implemented in thismaster thesis. The block diagram of the three stage variable gain differential amplifier isshown in the following figure 4.1.

Offset Compensator

CoarseInterface Fine 1 Fine 2 Buffer

Gain Setting Decoder

Variable Gain Amplifier

4 7 7

Coeff_valid

Input Output

5Gain_control

OC_enable

Figure 4.1: Block diagram of the three stage differential amplifier with output buffer.

35

CHAPTER 4. THREE STAGE DIFFERENTIAL VGA WITH RESISTIVE NETWORKAND SOURCE DEGENERATION 36

It consists of a coarse amplifier stage followed by two fine amplifier stages, as shown inthe above figure 4.1. A buffer is also implemented to drive the output load of the sampleand hold circuit in the analog-to-digital converter (ADC). The coarse stage is a R-xR ladderattenuator with four gain setting bits. The fine stage is a source degenerative differentialamplifier which is discussed in the previous section 3.4. It has seven gain setting bits. Thebuffer is also a source degenerative differential amplifier with unity gain.The following circuits are also designed during this master thesis for the improvements ofthe variable gain amplifier (VGA).

• Constant gm biasing circuit.

• Offset compensation circuit.

• Gain setting decoder.

Constant gm biasing circuit is designed and implemented to bias the variable gain am-plifier (VGA), such that the gain variations over the corners are as small as possible.

Offset compensation circuit is designed and implemented to minimize the offset of thevariable gain amplifier (VGA).

Gain setting decoder is a verilogA code used to map five bits of the input digital controlsignal to the seven bit digital control signal, for each fine stage. It sets the gain insuch a way that it is monotonic and linear in dB.

4.1. INTRODUCTION


4.2 Coarse stage

This is a R-xR ladder based programmable attenuator. It reduces the input signal amplitudeand also provides the input impedance matching. It has four gain control bits, which areused to select different attenuations. Each bit gives approximately −3.3 dB of attenuation.Maximum attenuation given by the coarse stage is approximately −9.8 dB. The circuitdiagram of the coarse stage is shown in the following figure 4.2.

Figure 4.2: Schematic of the coarse stage.

The gain settings with corresponding bandwidth of the coarse stage are given in the followingtable 4.1

Table 4.1: Gain settings with corresponding bandwidth of the coarse stage.

Sr. No. Din Ac Gain (dB) Transient Gain (Linear) Bandwidth (Hz)1 1 −617.4 u 959 m 6.334 G2 2 −3.306 659 m 4.29 G3 3 −6.62 445.4 m 3.422 G4 4 −9.848 299.4 m 2.614 G

Note that, at gain setting 1, the attenuation is not zero. This is because of the transistorswitch in this path, as shown in figure 4.2.

4.2. COARSE STAGE


The simulation results in the corner analysis at worst case gain setting of Din = 8, aregiven in the following table 4.2.

Table 4.2: Simulation results of the coarse stage in the corner analysis.

Parameters Min Typ Max StddevAC Current (A) 10.04 m 11.25 m 12.75 m 936.7 uInput Impedance (Ohm) 39.22 44.43 49.82 1.87Output common mode voltage (V) 1.244 1.4 1.478 83.77 mTransient Gain (Linear) 283.7 m 299.4 m 307 m 7.635 mAC Gain (dB) −9.848 −9.848 −9.848 160.9 uBandwidth (Hz) 1.963 G 2.614 G 3.18 G 409.4 MLower cut-off frequency (Hz) 10.21 k 12.82 k 14.37 k 1.65 kOutput voltage amplitude (V) 227 m 239.5 m 245.6 m 6.093 mThird harmonic distortion (dBc) −51.71 −50.94 −47.03 1.647Input referred noise power (dBc) −150.5 −148.2 −145.7 2.017Common mode rejection ratio (dB) 28.55 48.09 48.83 NA

The AC current is flowing in the differential inputs of the coarse stage. It is observed for thecalculation of the input impedance. Also, note that there is a lower cut-off frequency. Thisis due to the external input coupling capacitance for interfacing the received signal from thechannel.The gain curves in the corner analysis at worst case gain setting of Din = 8, are shown inthe following figure 4.3.

Sat Nov 19 18:14:00 2011

Transfer_Function

Name Corner

Transfer_Function











(dB)

-100

-75.0

-50.0

-25.0

0.0

104

105

106

107

108

109

1010

1011

freq (Hz)10

010

110

210

3

Page 1 of 1

Figure 4.3: Gain curves of the coarse stage in the corner analysis.

4.2. COARSE STAGE


The simulation results in the montecarlo analysis at worst case gain setting of Din = 8,are given in the following table 4.3.

Table 4.3: Simulation results of the coarse stage in the montecarlo analysis.

Parameters Min Typ Max StddevAC Current (A) 11.24 m 11.25 m 11.26 m 4.182 uInput Impedance (Ohm) 44.39 44.43 44.49 16.52 mOutput common mode voltage (V) 1.4 1.4 1.4 0Input referred Offset (V) −743.9 a −29.71 a 743.4 a 348.4 aTransient Gain (Linear) 298.5 m 299.4 m 300.2 m 322.2 uAC Gain (dB) −9.876 −9.849 −9.823 9.562 mBandwidth (Hz) 2.601 G 2.614 G 2.625 G 4.156 MLower cut-off frequency (Hz) 11.16 k 12.39 k 13.67 k 561Output voltage amplitude (V) 238.8 m 239.5 m 240.2 m 257.8 uThird harmonic distortion (dBc) −70.07 −68.78 −67.85 423 mInput referred noise power (dBc) −148.2 −148.2 −148.2 11.03 m

4.2. COARSE STAGE


4.3 Fine stage

It is a differential amplifier with source degeneration. This architecture is discussed in theprevious section 3.4. Only addition in the previous architecture is the gain setting networkfor the different gain settings. This network is at the source terminal of the input transistor,as shown in the following figure 4.4. It makes the gain of the fine stage variable.Some parameters of the fine stage are improved. These parameters are:

• Minimize the variations of the gain in the corner analysis by the constant gm biasing.

• Lower the minimum gain.

The following three versions of the fine stage are designed progressively.

• Version 1: Fine stage with constant transconductance biasing.

• Version 2: Fine stage with high speed transistors.

• Version 3: Fine stage with resized switching transistors.

4.3. FINE STAGE


4.3.1 Fine stage version 1

This version of the fine stage improves the gain variations in the corner analysis. To reducethe gain variation, the Vgs over R biasing circuit is replaced by the constant transconduc-tance biasing circuit. This biasing circuit is discussed in the next subsection. The schematicof the fine stage version 1 is shown in the following figure 4.4.

Figure 4.4: Schematic of the fine stage with constant gm biasing.

Transistors in the gain setting network are used as switches to select different gain settingsby the digital signal processor (DSP). These resistors and transistors are sized according tothe power of two, as shown in the above figure 4.4. Every branch have transistor two timeswider than the previous branch and resistors two times smaller than the previous branch.

4.3. FINE STAGE


4.3.1.1 Constant (gm) biasing circuit

The gain variations with the process or the temperature could be decreased by using theconstant transconductance (gm) biasing circuit. The gain of the fine stage amplifier dependsupon the transconductance, as described by equation 3.3. The constant transconductancebiasing circuit tends to maintain the transconductance of the amplifier constant with theprocess or the temperature changes. This decreases the variations in the gain of the ampli-fier. The constant transconductance biasing circuit is shown in the following figure 4.5. Thetransistors Mload1 and Mload2 operates at the same source-bulk voltage to prevent the bodyeffect error.

Figure 4.5: Schematic of the constant transconductance biasing circuit.

The transconductance of the above circuit in figure 4.5 is given by the following formula [8].

gmmirror1=

2

RD

1− 1√W2

W1

, (4.1)

where W1 is the width of the mirror transistor Mmirror1, W2 is the width of the mirrortransistor Mmirror2, RD is the drain resistor and gmmirror1

is the transconductance of themirror transistor Mmirror1. In this project, ratio W2/W1 equal to 4 is used as it givesgmmirror1 = 1/RD. Note that in that case, the transconductance only depends upon the re-sistor value and the ratio of the width. This method gives satisfactory results, if the resistorvalue remains more stable than the transistor parameters [8].The amplifier used in the above circuit shown in figure 4.5, is utilized to make source volt-ages of Mload1 and Mload2 equal. This amplifier is a high gain amplifier. The schematic of

4.3. FINE STAGE


this amplifier is shown in figure 4.6.

Figure 4.6: Schematic of the amplifier used in the constant transconductance biasing circuit.

4.3. FINE STAGE


Complete transistor level schematic of the constant transconductance biasing circuit isshown in the following figure 4.7.

Figure 4.7: Schematic of the complete constant transconductance biasing circuit.

4.3. FINE STAGE


The above figure 4.7 of the constant transconductance biasing circuit consists of a selfbias amplifier, a constant transconductance biasing circuit, a start up circuit, and two cur-rent mirroring circuits. One current mirroring circuit is for the low speed transistor modeland other is for the high speed transistor model.Start up circuit, in the above figure 4.7, is used to avoid the unwanted state. In this state,zero current flows in the reference circuit [7]. The start up circuit should not affect thenormal operation of the biasing circuit.The simulation results in the corner analysis are given in the following table 4.4.

Table 4.4: Simulation results of the constant gm biasing circuit in the corner analysis.

Parameters Min Typ Max Stddevgm (S) 647.1 u 754.7 u 885.4 m 80.42 uIref (A) 34.41 u 52.02 u 92.38 u 20.41 u

The gm observed in the above table 4.4, is the observed transconductance of Mload1 in fig-ure 4.5. Comparison of the simulation results of the fine stage amplifier with and withoutthe constant transconductance biasing circuit in the corner simulation are given in the fol-lowing table 4.5.

Table 4.5: Comparison of simulation results of the fine stage with and without the constanttransconductance biasing circuit in the corner analysis.

Parameters Vgs over R biasing Constant gm biasingWorse Stddev Worse Stddev

Power consumption (W) 2.575 m 361.6 u 3.672 m 741.2 uOutput common mode voltage (V) 1.118 142.7 m 1.012 217.2 mTransient Gain (Linear) 2.582 753.4 m 2.719 349.4 mAC Gain (dB) 8.524 1.961 8.891 1.044Bandwidth (Hz) 5.635 G 1.131 G 5.66 G 1.188 GThird harmonic distortion (dBc) −48.98 4.444 −37.75 4.349Input referred noise power (dBc) −137.7 3.13 −138.7 2.39

The above table 4.5 shows that the gain variations are reduced by using the constanttransconductance biasing circuit. The cost is paid in terms of the bandwidth variations.

4.3. FINE STAGE


Comparison of the simulation results of the fine stage amplifier with and without theconstant transconductance biasing circuit in the montecarlo simulation are given in thefollowing table 4.6.

Table 4.6: Comparison of simulation results of the fine stage with and without the constanttransconductance biasing circuit in the montecarlo analysis.

Parameters Vgs over R biasing Constant gm biasingWorse Sigma Worse Sigma

Power consumption (W) 2.097 m 101.7 u 3.116 m 392 uOutput common mode voltage (V) 1.341 22.33 m 1.255 68.57 mOutput Offset (V) 51.04 m 18.43 m 11.74 m 3.897 mTransient Gain (Linear) 2.861 365.4 m 2.527 334.6 mAC Gain (dB) 10.94 184.9 m 7.551 732.3 mBandwidth (Hz) 6.877 G 27.69 M 7.303 G 88.21 MThird harmonic distortion (dBc) −11.34 9.624 −37.78 1.661Input referred noise power (dBc) −142.3 129.6 m −128.8 1.541

4.3. FINE STAGE


4.3.1.2 Simulation results of the fine stage version 1

The following are the simulation results of the fine stage version 1 in the corner and themontecarlo analysis. The simulation results in the corner analysis at worst case gain settingof Din = 127, are given in the following table 4.7.

Table 4.7: Simulation results of the fine stage with constant gm biasing in the corner analysis.

Parameters Min Typ Max StddevPower consumption (W) 1.434 m 2.178 m 3.672 m 741.2 uOutput common mode voltage (V) 1.012 1.419 1.615 217.2 mTransient Gain (Linear) 2.719 3.46 3.613 349.4 mAC Gain (dB) 8.891 10.93 11.61 1.044Bandwidth (Hz) 5.66 G 6.899 G 9.472 G 1.188 GOutput voltage amplitude (V) 228.9 m 285.4 m 306.1 m 29.43 mThird harmonic distortion (dBc) −49.58 −44.64 −37.75 4.349Input referred noise power (dBc) −144.9 −142.4 −138.7 2.39

The gain curves in the corner analysis at worst case gain setting of Din = 127, are shown inthe following figure 4.8. Thu Nov 24 19:16:04 2011

Transfer_Function

Name Corner

Transfer_Function











(dB)

-10.0

-5.0

0.0

5.0

10.0

15.0

103

104

105

106

107

108

109

1010

1011

freq (Hz)10

010

110

2

Page 1 of 1

Figure 4.8: Gain curves of the fine stage with constant gm biasing in the corner analysis.

4.3. FINE STAGE


The gain setting curves in the corner analysis are shown in the following figure 4.9.Sat Nov 26 16:46:37 2011

GainAC vs. Din

Name

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

5.85

11.8

4.37

8.8

7.32

Gain

AC

10.3

103.1-2.54 50.29 76.7123.88 129.5Din

Page 1 of 1Figure 4.9: Gain setting curves of the fine stage with constant gm biasing in the corneranalysis.

In the above figure 4.9, the gain is in dB and Din is the digital gain control bits. Note that,the AC gain shown in the above figure 4.9, always grows with increment of the input digitalgain control bits.The simulation results in the montecarlo analysis at worst case gain setting of Din = 127,are given in the following table 4.8.

Table 4.8: Simulation results of the fine stage with constant gm biasing in the montecarloanalysis.

Parameters Min Mean Max SigmaPower consumption (W) 1.053 m 2.2 m 3.116 m 392 uOutput common mode voltage (V) 1.255 1.415 1.615 68.57 mInput Referred Offset (V) −8.778 m 329.1 u 11.74 m 3.897 mTransient Gain (Linear) 2.527 3.438 4.078 334.6 mAC Gain (dB) 7.551 10.83 11.87 732.3 mBandwidth (Hz) 6.832 G 6.918 G 7.303 G 88.21 MOutput voltage amplitude (V) 213.7 m 284.5 m 338.4 m 27.75 mThird harmonic distortion (dBc) −46.03 −44.34 −37.78 1.661Input referred noise power (dBc) −142.9 −141.9 −128.8 1.541

4.3. FINE STAGE


The bandwidth is highest at the lowest gain and smallest at the highest gain. Thisrelation is because of additional capacitance introduced by the gain setting network. As thegain increases, more transistors are switched ON in this network. These transistor switchesadd capacitance at the output node, which results in decrease of the bandwidth. Bandwidthverses digital control bits curve is shown in the following figure 4.10.

Fri Nov 11 17:38:55 2011

AC_3dB_BW

Name

AC_3dB_BW

M20: 26.5252m 16.17686G

M21: 127.0 9.068839G

7.5

10.0

12.5

15.0

17.5

20.0

(G)

50.0

Din

125.0 150.0100.00.0 75.025.0

Page 1 of 1

Figure 4.10: Bandwidth curve of the fine stage with constant gm biasing in all gain settings.

4.3. FINE STAGE



The lowest possible AC gain of the fine stage is 5.9 dB, which should be lowered so that thegain range will increase. To improve the lowest possible gain, capacitance at the gain settingnetwork should be reduced. The capacitance at that node results in the gain curve peakingat high frequencies. This capacitance could be reduced by decreasing the size of the input,the biasing or the switching transistors and changing the type of the biasing transistors.Changing the type of the biasing transistors, also requires same type of transistor in thebiasing circuit.The lowest possible gain is lowered in the version 2 by two modifications in the version 1.First, the type of the biasing transistors in the amplifier and the mirroring transistor in thebiasing circuit is changed from low speed NMOS to high speed NMOS. Second, the sizes ofthe biasing transistors in the amplifier are reduced. The modified circuit with reduced sizenmos hs biasing transistor, is shown in the following figure 4.11.

Figure 4.11: Schematic of the fine stage with high speed biasing transistors.

4.3. FINE STAGE


The sizes of the input and the biasing transistors are decreased by using high speedNMOS, which reduces the capacitance at the node of the gain setting network. The reduc-tion in the capacitance at that node increases the bandwidth. It also eliminates the peakingin the gain curves, which decreases the lowest possible gain of the fine stage without peakingin the gain curve.The simulation results in the corner analysis at worst case gain setting of Din = 127, aregiven in the following table 4.9.

Table 4.9: Simulation results of the fine stage with high speed biasing transistors in thecorner analysis.

Parameters Fine stage version 1 Fine stage version 2Power consumption (W) 3.672 m 4.475 mOutput common mode voltage (V) 1.012 1.096Transient Gain (Linear) 2.719 2.241AC Gain (dB) 8.891 7.06Bandwidth (Hz) 5.66 G 7.215 GOutput voltage amplitude (V) 285.4 m 282.1 mThird harmonic distortion (dBc) −44.64 −42.15Input referred noise power (dBc) −138.7 −137

The lowest gain is lowered in the version 2 of the fine stage up to 3.4 dB. The above resultsin table 4.9, showed that the bandwidth is improved whereas the highest gain is reduced.Bandwidth improvement already discussed, is due to the reduction in the capacitance. Thehighest gain reduces because of the smaller lowest gain setting. Note that, it does not reduceas much as the lowest gain setting itself, which results in the increase of the gain range.

4.3. FINE STAGE


The gain curves in the corner analysis at worst case gain setting of Din = 127, are shownin the following figure 4.12.

Fri Nov 11 18:43:20 2011

Transfer_Function

Name Corner

Transfer_Function











0.0

(dB)

12.5

5.0

-5.0

10.0

2.5

7.5

-2.5

1010

102

104

101

108

1011

105

100

107

106

freq (Hz)10

310

9

Page 1 of 1

Figure 4.12: Gain curves of the fine stage with high speed biasing transistors in the corneranalysis.

The above figure 4.12 also shows the reduction in the highest gain.

4.3. FINE STAGE


The gain setting curves in the corner analysis are shown in the following figure 4.13.Sat Nov 12 11:58:16 2011

Gain vs. Din

Name

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

8.93

5.56

Gain

7.24

3.87

2.18

10.6

Din

76.71-2.54 129.550.29 103.123.88

Page 1 of 1

Figure 4.13: Gain setting curves of the fine stage with high speed biasing transistors in thecorner analysis.

The above figure 4.13 also shows that the highest gain is reduced.The simulation results in the montecarlo analysis at worst case gain setting of Din = 127,are given in the following table 4.10.

Table 4.10: Simulation results of the fine stage with high speed biasing transistors in themontecarlo analysis.

Parameters Fine stage version 1 Fine stage version 2Power consumption (W) 3.116 m 4.445 mOutput common mode voltage (V) 1.255 1.207Input Referred Offset (V) −8.778 m −14.89 mTransient Gain (Linear) 2.527 1.94AC Gain (dB) 7.551 6.302Bandwidth (Hz) 6.832 G 8.901 GOutput voltage amplitude (V) 284.5 m 291.6 mThird harmonic distortion (dBc) −44.34 −39.56Input referred noise power (dBc) −128.8 −138.5

4.3. FINE STAGE



The lowest possible AC gain of the fine stage with the nmos hs transistor is 3.4 dB, whichcould be lowered more by decreasing the size of the switching transistors. This reduction inthe size of the switching transistors reduces the capacitance of the gain setting network. Iteliminates the peaking in the gain curve at high frequencies and improves the lowest possiblegain without the peaking in the gain curve. The sizes of last three transistors are decreasedby power of 2. Also, both resistors connected with these switching transistors are decreasedto maintain same gain at these nodes. The schematic of the fine stage with resized switchingtransistors is shown in the following figure 4.14.

Figure 4.14: Schematic of the fine stage with resized switching transistors.

4.3. FINE STAGE


The gain curve is shown in the following figure 4.15. It shows the peaking in the curvedue to the capacitive impedance at high frequency in the gain setting network.

Fri Nov 11 19:15:54 2011

Transfer_Function

Name

Transfer_Function

M23: 7.1726949GHz 1.3051086dB

-2

-3

1

2

-4

0

-1

-5

(dB)

1010

1011

103

108

105

107

109

106

freq (Hz)10

410

210

010

1

Page 1 of 1

Figure 4.15: Gain curve without resized switching transistors.

The gain curve after reducing the capacitance at the gain setting network node is shown inthe following figure 4.16.

Sat Nov 12 12:16:55 2011

Transfer_Function

Name

Transfer_Function

M24: 397.0576kHz 1.070302dB

-4.0

-2.0

0.0

-6.0

(dB)

2.0

105102

freq (Hz)104 109100 108101 107106 1010103 1011

Page 1 of 1

Figure 4.16: Gain curve of the fine stage with resized switching transistors.

The above figure 4.16 shows the elimination of the peaking by reduction of the capacitanceand also the value of the lowest possible gain is reduced from 3.4 dB to 267.8 mdB. Theparameters of the fine stage version 3 at the corner and the montecarlo analysis are sameas the previous version 2 of the fine stage. The gain curves at the corner analysis are alsosame as the fine stage version 2.

4.3. FINE STAGE


The gain setting curves in the corner analysis are shown in the following figure 4.17.Sun Nov 20 18:01:20 2011

Gain vs. Din

Name

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

Gain

8.54703

.063875

2.18466

4.30545

10.6678

6.42624

76.7123.88 103.1-2.54 50.29 129.5Din

Page 1 of 1

Figure 4.17: Gain setting curves of the fine stage with resized switching transistors in thecorner analysis.

The AC gain range is 267.8 mdB to 10.46 dB. The total number of steps are 127. There areabrupt changes in the step size at gain setting of 16th, 32nd and 64th, as shown in the abovefigure 4.14. This is because of the change of transistor sizes at 5th, 6th, and 7th branch ofthe gain setting network. At these branches, there is no more power of two reduction, inthe transistor sizes, as in the 1st, 2nd, 3rd and 4th branch of the gain setting network. So,these transistors at the 5th, 6th and 7th branch, changes differently over the corners as thetransistors of the first four branches. This makes abrupt change in the gain step at 16th,32nd and 64th gain setting. With this change, the monotonic property of the gain settingsare lost. But it will be regained by the decoder discussed in section 4.6.1.The common mode rejection ratio of the fine stage version 3 in the corner analysis is givenin the following table 4.11.

Table 4.11: Simulation results of the fine stage with high speed biasing transistors in themontecarlo analysis.

Parameter Min Typ MaxCommon mode rejection ratio (dB) 47.934 48.955 49.43

4.3. FINE STAGE


4.4 Output buffer design

To drive the output load of the three stage variable gain differential amplifier a buffer isdesigned. This buffer has the capability to drive 200 fF load capacitance without degradingmuch performance of the three stage variable gain differential amplifier . The buffer is asource degenerative differential amplifier. The schematic of the output buffer is shown inthe following figure 4.18.

Figure 4.18: Schematic of the output buffer.

4.4. OUTPUT BUFFER DESIGN


The simulation results in the corner analysis are given in the following table 4.12.

Table 4.12: Simulation results of the output buffer in the corner analysis.

Parameters Min Typ Max StddevPower Consumption (W) 5.896 m 8.951 m 14.7 m 2.887 mOutput common mode voltage (V) 1.036 1.414 1.608 207.7 mTransient Gain (Linear) 870.6 m 1.005 1.102 85.16 mAC Gain (dB) −1.232 108.7 m 848.6 m 787.7 mBandwidth (Hz) 7.643 G 8.75 G 15.16 G 2.793 GOutput voltage amplitude (V) 210.5 m 243.5 m 268.1 m 20.92 mThird harmonic distortion (dBc) −59.69 −57.04 −47.27 4.313Input referred noise power (dBc) −144.6 −142.8 −140.5 1.239

The gain curves in the corner analysis are shown in the following figure 4.19.Sun Nov 20 14:22:24 2011

Transfer_Function

Name Corner

Transfer_Function











(dB)

-10

-7.5

-5.0

-2.5

0.0

2.5

freq (Hz)10

010

110

210

310

410

510

610

710

810

910

1010

11

Page 1 of 1

Figure 4.19: Gain curves of the output buffer in the corner analysis.



The simulation results in the montecarlo analysis are given in the following table 4.13.

Table 4.13: Simulation results of the output buffer in the montecarlo analysis.

Parameters Min Mean Max SigmaPower consumption (W) 4.513 m 8.811 m 14.24 m 1.796 mOutput common mode voltage (V) 1.179 1.419 1.593 75.02 mInput referred Offset (V) −11.05 m 556 u 13.3 m 4.719 mTransient Gain (Linear) 896.1 m 997.1 m 1.067 34.96 mAC Gain (dB) −705 m 28.97 m 378.5 m 233.7 mBandwidth (Hz) 7.493 G 8.641 G 9.742 G 413.3 MOutput voltage amplitude (V) 217.9 m 241.6 m 258.7 m 8.427 mThird harmonic distortion (dBc) −60.33 −55.79 −45.53 3.246Input referred noise power (dBc) −143.7 −142.6 −141.3 430 m



4.5 Gain setting decoder

The gain settings are changed by a digital control circuit. The output of the three stagevariable gain differential amplifier is observed and if there is a need to increase or decreasethe gain then that digital control circuit produces five bits output to set the gain. Thesefive bits output of the digital gain control circuit are mapped to seven digital control bitsfor each stage of the fine amplifier by the gain setting decoder. This decoder is implementedas a verilogA code in this thesis. The verilogA code can be studied in the appendix B. Thedecoder tends to minimize change in the step size during the gain setting. The gain stepdecreases with the increase of the digital control bits as shown in figure 4.20.

Figure 4.20: Gain setting curves of the three stage variable gain differential amplifier withoutgain setting decoder.

At higher gain settings, it becomes so small that the change in the gain with the digitalgain control bits is nearly zero. The decoder solves this problem by making the gain stepapproximately constant at all gain settings.The gain setting curves are shown in the following figure 4.21.

Figure 4.21: Gain setting curves of the three stage variable gain differential amplifier withgain setting decoder.

This makes the gain setting, linear and monotonic. This can be observed by comparingfigure 4.20 with the gain setting curve of the three stage variable gain differential amplifierwith output buffer shown in figure 4.21.

4.5. GAIN SETTING DECODER


4.6 Offset compensation

The offset is generated by mismatch between the differential pair which is discussed in section2.1.1.3. Major contribution to the DC offset generated in the variable gain amplifier (VGA)is by two fine stages. To compensate this DC offset a feedback methodology is used in thisthesis [9, 10]. This feedback circuit have a low pass filter and an amplifier. The feedbackcircuit amplifies the extracted offset at output of the variable gain amplifier (VGA) andsubtracts it with the input of the fine stage. The schematic of the offset compensationcircuit is shown in the following figure 4.22.

Figure 4.22: Schematic of the offset compensation circuit.

The input referred offset of the three stage variable gain differential amplifier without theoffset compensation circuit is -183.7 mV and with the offset compensation circuit is -2.54mV. The output of the three stage variable gain differential amplifier is filtered by the lowpass filter, as shown in the above figure 4.22. After filtering, this signal is amplified bythe two stage offset compensation amplifier. Two stages are used to get high amplification.Following is the discussion of these amplifiers.

4.6. OFFSET COMPENSATION


4.6.1 First stage offset compensation amplifier

This is a current source load differential amplifier with common mode feedback (CMFB)circuit. It needs the common mode feedback (CMFB) circuit to make the common modevoltage more stable on the corner analysis. The common mode feedback (CMFB) circuitis discussed previously in section 3.3. The schematic of the first stage offset compensationamplifier is shown in the following figure 4.23.

Figure 4.23: Schematic of the first stage offset compensation amplifier.




Table 4.14: Simulation results of the first stage offset compensation amplifier in the corneranalysis.

Parameters Min Typ Max StddevPower consumption (W) 113.3 u 174.4 u 289.7 u 58 uOutput common mode voltage (V) 1.014 1.407 1.608 217.2 mTransient Gain (Linear) 3.963 4.412 4.505 182.7 mAC Gain (dB) 12.25 13.45 13.78 537 mBandwidth (Hz) 860.7 M 1.026 G 1.302 G 149.2 MOutput voltage amplitude (V) 217.9 m 242.7 m 247.8 m 10.04 mThird harmonic distortion (dBc) −69.82 −67.84 −66.37 1.147Input referred noise power (dBc) −142.5 −140.2 −137 2.057


Transfer_Function

Name Corner

Transfer_Function











(dB)

5.0

10.0

-10.0

-20.0

15.0

-5.0

0.0

-15.0

102

1011

1010

106

103

108

100

104

109

105

freq (Hz)10

110

7

Page 1 of 1

Figure 4.24: Gain curves of the first stage offset compensation amplifier in the corner anal-ysis.




Table 4.15: Simulation results of the first stage offset compensation amplifier in the monte-carlo analysis.

Parameters Min Mean Max SigmaPower consumption (W) 101.8 u 178 u 256.5 u 35.86 uOutput common mode voltage (V) 1.223 1.399 1.572 80.63 mInput Referred Offset (V) −87.76 m −4.949 m 21.09 m 20.61 mTransient Gain (Linear) 1.739 4.388 8.374 1.167AC Gain (dB) 10.33 13.34 15.01 1.068Bandwidth (Hz) 974.6 M 1.027 G 1.074 G 21.4 MOutput voltage amplitude (V) 95.62 m 240.9 m 460.6 m 64.37 mThird harmonic distortion (dBc) −68.24 −67.88 −67.58 149 mInput referred noise power (dBc) −141 −136.5 −120.7 4.612



4.6.2 Second stage offset compensation amplifier

This is a resistive load differential amplifier. The amplifier is shown in figure 4.23 is usedto amplify the extracted output offset by the filter and delivered to the second stage. Theschematic of the second stage offset compensation amplifier is shown in the following fig-ure 4.25.

Figure 4.25: Schematic of the second stage offset compensation amplifier.




Table 4.16: Simulation results of the second stage offset compensation amplifier in the corneranalysis.

Parameters Min Typ Max StddevPower consumption (W) 4.538 m 6.827 m 11.35 m 2.231 mOutput common mode voltage (V) 1.006 1.404 1.587 197.7 mTransient Gain (Linear) 19.11 46.55 57.31 15.41AC Gain (dB) 25.74 33.86 36.09 4.098Bandwidth (Hz) 66.78 M 96.02 M 272.6 M 77.62 MOutput voltage amplitude (V) 95.42 m 230.2 m 286.5 m 76.33 mThird harmonic distortion (dBc) −48.41 −37.24 −31.28 7.035Input referred noise power (dBc) −156.6 −154.4 −152.9 1.033


Transfer_Function

Name Corner

Transfer_Function











0.0

20.0

-10.0

30.0

(dB

)

40.0

-20.0

10.0

106

108

100

104

101

103

1010

102

107

freq (Hz)10

1110

910

5

Page 1 of 1

Figure 4.26: Gain curves of the second stage offset compensation amplifier in the corneranalysis.




Table 4.17: Simulation results of the second stage offset compensation amplifier in themontecarlo analysis.

Parameters Min Mean Max SigmaPower consumption (W) 4.147 m 6.844 m 12.42 m 1.422 mOutput common mode voltage (V) 1.075 1.398 1.543 74.29 mInput Referred Offset (V) −224.7 m −3.044 m 1.863 m 22.53 mTransient Gain (Linear) 1.01 42.22 67.07 12.9AC Gain (dB) 25.06 33.31 34.18 969.2 mBandwidth (Hz) 72.95 M 102.8 M 392.2 M 34.39 MOutput voltage amplitude (V) 5.049 m 209.6 m 330.9 m 63.84 mThird harmonic distortion (dBc) −43.73 −37.3 −30.69 2.801Input referred noise power (dBc) −155.4 −153.2 −145.3 1.728



4.7 Three stage differential VGA with output buffer,gain setting decoder and offset compensation

The block diagram of this amplifier is shown in figure 4.1. It includes all the improvementcircuits which are: the output buffer, the offset compensation circuit and the gain settingdecoder. These circuits are discussed in sections 4.4, 4.5 and 4.6 respectively.The simulation results in the corner analysis at worst case gain setting of DinF = 127 andDinC = 8, are given in the following table 4.18.

Table 4.18: Simulation results of the three stage variable gain differential amplifier withimprovements in the corner analysis.

Parameters Min Typ Max StddevPower consumption (W) 14.46 m 21.91 m 34.17 m 6.269 mOutput common mode voltage (V) 1.066 1.414 1.604 197.2 mTransient Gain (Linear) 1.494 2.585 3.521 753.5 mAC Gain (dB) 3.672 8.659 11.74 3.068Bandwidth (Hz) 1.159 G 1.363 G 1.713 G 181.7 MLower cut-off frequency (Hz) 978.8 k 2.123 M 3.783 M 1.082 MOutput voltage amplitude (V) 134.4 m 232.6 m 316.9 m 67.81 mThird harmonic distortion (dBc) −54.55 −54.55 −39.86 4.555Input referred noise power (dBc) −124.5 −123.1 −120.9 1.25Common mode rejection ratio (dB) 42.184 43.272 43.83 NA


Transfer_Function

Name Corner

Transfer_Function











(dB)

-125.0

-100.0

-75.0

-50.0

-25.0

0.0

25.0

freq (Hz)10

010

110

210

310

410

510

610

710

810

910

10

Page 1 of 1

Figure 4.27: Gain curves of the three stage variable gain differential amplifier with improve-ments in the corner analysis.

4.7. THREE STAGE DIFFERENTIAL VGA WITH OUTPUT BUFFER, GAINSETTING DECODER AND OFFSET COMPENSATION



GainAc_dB vs. Din

Name

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

GainAc_dB

7.64

3.1

-1.43

-5.97

-10.5

12.2

Din13.7 28.9-1.46 44.1 59.3 74.5

Page 1 of 1

Figure 4.28: Gain setting curves of the three stage variable gain differential amplifier withimprovements in the corner analysis.

The above curves in figure 4.28 shows that the gain settings are linear and monotonic. TheAC gain range is −10.06 dB to 21.62 dB with step size of approximately 0.3 dB. The totalnumber of the gain steps are 78.The simulation results in the montecarlo analysis at worst case gain setting of DinF = 127and DinC = 8, are given in the following table 4.19.

Table 4.19: Simulation results of the three stage variable gain differential amplifier withimprovements in the montecarlo analysis.

Parameters Min Mean Max SigmaPower consumption (W) 13.12 m 21.97 m 29.8 m 3.831 mOutput common mode voltage (V) 1.27 1.413 1.566 68.05 mInput Referred Offset (V) −1.391 m 52.16 u 1.449 m 582.7 uTransient Gain (Linear) 1.488 2.552 3.248 402.9 mAC Gain (dB) 3.802 8.428 10.77 1.463Bandwidth (Hz) 1.325 G 1.382 G 1.474 G 34.07 MLower cut-off frequency (Hz) 596.8 k 2.004 M 3.323 M 669.8 kOutput voltage amplitude (V) 133.9 m 229.7 m 292.3 m 36.26 mThird harmonic distortion (dBc) −58.21 −54.01 −49.7 1.448Input referred noise power (dBc) −125.1 −123.1 −120.9 1.013



Bandwidth verses gain setting curve is shown in the following figure 4.29.Sun Nov 27 21:46:44 2011

AC_3dB_BW vs. Din

Name

C02

C03

C04

C05

C06

C07

C08

C09

C10

C01

AC_3dB_BW (G)

2.23

2.01

1.79

1.36

1.57

1.14

74.528.9-1.46 13.7 59.344.1Din

Page 1 of 1

Figure 4.29: Bandwidth curve of the three stage variable gain differential amplifier withimprovements.

The highest bandwidth is 3.206 GHz at lowest gain setting. The lowest bandwidth is 1.363GHz at the highest gain setting of the fine stage and the lowest gain setting of the coarsestage. In these gain settings, all transistor switches are in ON state and the capacitance ismaximum, which results in the lowest bandwidth.


Chapter 5

Layout design of the three stagevariable gain differentialamplifier with output buffer

The layout of the three stage variable gain differential amplifier is designed. There are fewthings to keep in mind during the designing of the high speed layout. First, the connectingwire thickness should be big enough to provide low impedance but at the same time smallenough to have low parasitic capacitance. The impedance of the connecting wire will affectthe gain and the capacitance will affect the bandwidth of the amplifier. Second, do notoverlap two signal wires long enough. It will increase the parasitic capacitance which willdecrease the bandwidth. Third, give enough space between long running parallel signal wiresto reduce parasitic capacitance. This improves the bandwidth.Following sections gives the layout design of each stage.

71

CHAPTER 5. LAYOUT DESIGN OF THE THREE STAGE VARIABLE GAINDIFFERENTIAL AMPLIFIER WITH OUTPUT BUFFER 72

5.1 Coarse stage

The layout of the coarse stage is shown in the following figure 5.1.

Figure 5.1: Layout of the coarse stage.

The RC extracted view of the layout is simulated in the corner and the montecarlo analysis.These results are given in the following tables. The simulation results in the corner analysisat worst case gain setting of Din = 8, are given in the following table 5.1.

Table 5.1: Comparison of simulation results of the coarse stage schematic and layout in thecorner analysis.

Parameters Schematic LayoutAC Current (A) 10.04 m 11.52 mInput Impedance (Ohm) 39.22 35.76Output common mode voltage (V) 1.244 1.244Transient Gain (Linear) 283.7 m 284.6 mAC Gain (dB) −9.848 −10.26Bandwidth (Hz) 1.963 G 1.685 GOutput voltage amplitude (V) 245.6 m 255.6 mThird harmonic distortion (dBc) −47.03 −47.83Input referred noise power (dBc) −145.7 −146.1

5.1. COARSE STAGE


The gain curves in the corner analysis at worst case gain setting of Din = 8, are shownin the following figure 5.2.

Sun Nov 27 15:28:52 2011

Transfer_Function

Name Corner

Transfer_Function











(dB)

-100

-75.0

-50.0

0.0

-25.0

109

106

107

108

1010

100

101

102

freq (Hz)10

310

1110

410

5

Page 1 of 1

Figure 5.2: Gain curves of the coarse stage layout in the corner analysis.

The simulation results in the montecarlo analysis at worst case gain setting of Din = 8, aregiven in the following table 5.2.

Table 5.2: Comparison of simulation results of the coarse stage schematic and layout in themontecarlo analysis.

Parameters Schematic LayoutAC Current (A) 11.24 m 12.61 mInput Impedance (Ohm) 44.39 39.62Output common mode voltage (V) 1.4 1.4Input referred Offset (V) −743.9 a −1.961 pTransient Gain (Linear) 298.5 m 277 mAC Gain (dB) −9.876 −10.3Bandwidth (Hz) 2.601 G 2.143 GOutput voltage amplitude (V) 240.2 m 249.1 mThird harmonic distortion (dBc) −67.85 −66.06Input referred noise power (dBc) −148.2 −148.9

• Note that the view extracted is RC.

• The increase in the maximum attenuation, as compared to the schematic, is due tothe addition of the wire and the contact resistance after the layout.

• The decrease in the bandwidth is due to the addition of the wire and the contactparasitic capacitance.

5.1. COARSE STAGE


5.2 Fine stage

The layout of the fine stage version 3 is designed, but the peaking appears again at highfrequency. The cause of that peaking is the parasitic capacitance of the layout. This phe-nomenon is previously discussed in section 4.3.2. This peaking is improved by decreasingthe gain resistance R0 in the gain setting network , shown in figure 4.4. The decrease inthis resistance increases the lowest gain of the fine stage. The lowest gain is increased from1.002 dB to 6.434 dB.The layout of the peaking improved the fine stage is shown in the following figure 5.3.

Figure 5.3: Layout of the fine stage.

5.2. FINE STAGE


The RC extracted view of the layout is simulated in the corner and the montecarlo anal-ysis. These results are given in the following tables.The simulation results in the corner analysis at worst case gain setting of Din = 127, aregiven in the following table 5.3.

Table 5.3: Comparison of simulation results of the fine stage schematic and layout in thecorner analysis.

Parameters Schematic LayoutPower consumption (W) 4.475 m 5.251 mOutput common mode voltage (V) 1.096 1.038Transient Gain (Linear) 3.432 3.801AC Gain (dB) 11.13 11.7Bandwidth (Hz) 7.212 G 5.148 GOutput voltage amplitude (V) 265.6 m 250.5 mThird harmonic distortion (dBc) −42.97 −50.51Input referred noise power (dBc) −136.9 −138.7Common mode rejection ratio (dB) 47.941 47.879

The gain curves in the corner analysis at worst case gain setting of Din = 127, are shown inthe following figure 5.4.

Sun Nov 27 16:44:44 2011

Transfer_Function

Name Corner

Transfer_Function











(dB)

-10.0

-5.0

0.0

5.0

10.0

15.0

freq (Hz)10

010

110

210

310

410

510

610

710

810

910

1010

11

Page 1 of 1

Figure 5.4: Gain curves of the fine stage layout in the corner analysis.

5.2. FINE STAGE


The simulation results in the montecarlo analysis at worst case gain setting of Din =127, are given in the following table 5.4.

Table 5.4: Comparison of simulation results of the fine stage schematic and layout in themontecarlo analysis.

Parameters Schematic LayoutPower consumption (W) 4.222 m 5.068 mOutput common mode voltage (V) 1.238 1.114Input referred Offset (V) −11.08 m −14.19 mTransient Gain (Linear) 3.345 3.385AC Gain (dB) 9.936 9.831Bandwidth (Hz) 8.87 G 6.274 GOutput voltage amplitude (V) 279.2 m 282.5 mThird harmonic distortion (dBc) −42.88 −46.98Input referred noise power (dBc) −138.3 −142.3



5.2. FINE STAGE


5.3 Output buffer

The layout of the output buffer is shown in the following figure 5.5.

Figure 5.5: Layout of the output buffer.

The RC extracted view of the layout is simulated in the corner and the montecarlo analysis.These results are given following.The simulation results in the corner analysis are given in the following table 5.5.

Table 5.5: Comparison of simulation results of the output buffer schematic and layout inthe corner analysis.

Parameters Schematic LayoutPower consumption (W) 14.7 m 12.93 mOutput common mode voltage (V) 1.036 1.186Transient Gain (Linear) 108.7 m 126.9 mAC Gain (dB) 1.005 1.009Bandwidth (Hz) 7.643 G 7.339 GOutput voltage amplitude (V) 268.1 m 260.6 mThird harmonic distortion (dBc) −47.27 −49.18Input referred noise power (dBc) −140.5 −140.4

5.3. OUTPUT BUFFER



Transfer_Function

Name Corner

Transfer_Function








-7.5

(dB)

-10

-5.0

-2.5

0.0

2.5

100

freq (Hz)10

810

110

210

910

310

510

1010

610

410

710

11

Page 1 of 1

Figure 5.6: Gain curves of the output buffer layout in the corner analysis.


Table 5.6: Comparison of simulation results of the output buffer schematic and layout inthe montecarlo analysis.

Parameters Schematic LayoutPower consumption (W) 14.24 m 13.96 mOutput common mode voltage (V) 1.179 1.183Input referred Offset (V) −11.95 m −15.84 mTransient Gain (Linear) 997.1 m 997 mAC Gain (dB) 28.97 m 63.16 mBandwidth (Hz) 7.493 G 7.224 GOutput voltage amplitude (V) 258.7 m 259.9 mThird harmonic distortion (dBc) −45.53 −45.72Input referred noise power (dBc) −141.3 −139.1



5.3. OUTPUT BUFFER


5.4 Three stage variable gain differential amplifier withoutput buffer, gain setting decoder and offset com-pensation

The layout of the three stage variable gain differential amplifier with output buffer is de-signed. The gain setting decoder is on the verilogA code and the offset compensation circuitis on the schematic level. The layout of the three stage variable gain differential amplifier isshown in the following figure 5.7. The area of this layout is 395 um× 140 um.

Figure 5.7: Layout of the three stage variable gain differential amplifier.

5.4. THREE STAGE VARIABLE GAIN DIFFERENTIAL AMPLIFIER WITHOUTPUT BUFFER, GAIN SETTING DECODER AND OFFSET COMPENSATION


The RC extracted view of the layout is simulated in the corner and the montecarlo anal-ysis. These results are given following.The simulation results in the corner analysis at worst case gain setting of DinF = 127 andDinC = 8, are given in the following table 5.7.

Table 5.7: Comparison of simulation results of the three stage variable gain differentialamplifier schematic and layout in the corner analysis.

Parameters Schematic LayoutPower consumption (W) 34.17 m 34.18 mOutput common mode voltage (V) 1.066 1.067Transient Gain (Linear) 1.645 1.623AC Gain (dB) 4.533 4.511Bandwidth (Hz) 1.142 G 953.3 MLower cut-off frequency (Hz) 4.137 M 4.124 MOutput voltage amplitude (V) 256.1 m 252.6 mThird harmonic distortion (dBc) −50.64 −51.72Input referred noise power (dBc) −123 −123.7Common mode rejection ratio (dB) 42.15 42.7

The gain curves in the corner analysis, are shown in the following figure 5.8.Sun Nov 27 14:30:23 2011

Transfer_Function

Name Corner

Transfer_Function











-25.0

25.0

-100.0

-125.0

(dB

)

0.0

-50.0

-75.0

104

109

freq (Hz)10

310

810

010

610

510

210

710

110

10

Page 1 of 1

Figure 5.8: Gain curves of the three stage variable gain differential amplifier layout in thecorner analysis.




GainAc_dB vs. Din

Name

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

GainAc_dB

10.1

-.804

12.8

7.39

1.93

4.66

Din59.3 74.544.1-1.46 28.913.7

Page 1 of 1

Figure 5.9: Gain setting curves of the three stage variable gain differential amplifier layoutin the corner analysis.

The AC gain range is −541.5 mdB to 22.46 dB with step size of approximately 0.3 dB. Thetotal number of steps are 78. The abrupt changes in the step size, as shown in figure 5.9,is due to the change of the transistors size in the gain setting network during the design ofthe fine stage version 3. This phenomenon is already discussed in section 4.3.3.



Bandwidth verses digital control bits curve is shown in figure 5.10.Sun Nov 27 14:33:34 2011

AC_3dB_BW vs. Din

Name

C01

C03

C04

C05

C06

C07

C08

C09

C10

1.38

1.09

.939

1.23

1.68

1.53

AC_3dB_BW (G)

13.7 44.128.9 59.3 74.5Din

-1.46

Page 1 of 1

Figure 5.10: Bandwidth curve of the three stage variable gain differential amplifier layoutin the corner analysis.

The bandwidth decreases as number of the transistors switched ON in the gain settingnetwork. The maximum bandwidth is 1.481 G with only one transistor switched ON in thecoarse stage. The minimum bandwidth is 953.3 MHz with all transistor switches are ON,in the coarse stage and the fine stages.



The simulation results in the montecarlo analysis at worst case gain setting of DinF =127 and DinC = 8, are given in the following table 5.8.

Table 5.8: Comparison of simulation results of the three stage variable gain differentialamplifier schematic and layout in the montecarlo analysis.

Parameters Schematic LayoutPower consumption (W) 35.27 m 33.44 mOutput common mode voltage (V) 1.205 1.206Input referred Offset (V) −2.543 m −1.947 mTransient Gain (Linear) 1.376 1.691AC Gain (dB) 3.196 5.077Bandwidth (Hz) 1.23 G 1.03 GLower cut-off frequency (Hz) 3.932 M 4.674 MOutput voltage amplitude (V) 329 m 352 mThird harmonic distortion (dBc) −46.73 −48.61Input referred noise power (dBc) −119.7 −119.6


• The increase in the maximum amplification as compared to the schematic is due tothe addition of the wire and the contact resistance after the layout.



Chapter 6

Future work

6.1 VGA

Following are the improvements in each stage, which could be implemented in the threestage variable gain differential amplifier.

6.2 Fine stage

1. Gain step size does not remain monotonic after the layout implementation. It couldbe made monotonic by redesigning the gain setting decoder for the fine stage version3. The changes in the step size could be compensated by selecting appropriate gainsetting of the fine stages.

2. Linearity of the gain setting curve will also improve by above method of the gainstep compensation.

3. Lowest gain is also increased after the layout, which could be decreased by reducingthe size of switching transistors in the gain setting network.

4. Bandwidth could be increased by decreasing the size of the input transistors. Theinput transistor in the fine stage acts as a load capacitance on the next stage. Bydecreasing the size of the input transistor, the load capacitance decreases and thebandwidth of complete chain of the amplifier increases.

6.3 Coarse stage

1. Input impedance of the coarse stage changes in the corner analysis from 39.22 ohmto 49.82 ohm. This change should be reduced by analysing the resistor type used inthe R-xR ladder network.

6.4 Offset compensation

1. Layout of the offset compensation circuit could not be designed due to lack of time.It should be designed in the future for complete implementation of the three stagevariable gain differential amplifier.

84

CHAPTER 6. FUTURE WORK 85

6.5 Constant transconductance biasing circuit

1. Layout of the constant transconductance biasing circuit could not be designed due tolack of time. It should be designed in the future for complete implementation of thethree stage variable gain differential amplifier.

6.6 Three stage variable gain differential amplifier withoutput buffer

1. Noise simulation could not be performed with PAM-8 noisy signal on the three stagevariable gain differential amplifier due to lack of time. It should be performed.

2. Offset of the inner amplifiers in the chain should be recorded. Also, the effect of thehigh offset on these amplifiers should be analysed.

6.5. CONSTANT TRANSCONDUCTANCE BIASING CIRCUIT

Appendix A

Simulation Plan

The testing of the variable gain amplifier (VGA) is planned in the initial phase of thisproject. In the test planning, the types of the test signal, the simulations to test thedifferent parameters and the formula for these parameters are finalized.Following are the simulations used to test the variable gain amplifier (VGA).

A.1 Normal Operation Simulation

The following simulations use sinusoidal test signal for normal operation of the variable gainamplifier (VGA).

1. DC SimulationThe following parameters will be checked by the DC simulation.

• Power consumption is measured by multiplying, the value of the DC supplyvoltage source with the current drawn from that source by the amplifier.The formula in the cadence design environment is:

V supply × IDC(”/Ixx/V DD”). (A.1)

• Output common mode voltage is measured by taking the average of thedifferential output voltage.The formula in the cadence design environment is:

V DC(”/V outP”) + V DC(”/V outN”)

2. (A.2)

• Output offset voltage is measured by taking the difference of the output DCvoltage.The formula in the cadence design environment is:

(V DC(”/V outP”)− V DC(”/V outN”)). (A.3)

• Operating regions of transistors is measured by the saved OP parameters,to check the correct overdrive and reserve voltages.The formula in the cadence design environment is:

(OP (”/Ixx/Mxx” ”vds”)−OP (”/Ixx/Mxx” ”vdsat”)), (A.4)

(OP (”/Ixx/Mxx” ”vgs”)−OP (”/Ixx/Mxx” ”vth”)). (A.5)

86

APPENDIX A. SIMULATION PLAN 87

2. Transient simulationThe following parameters will be checked by the transient simulation.

• Third harmonic distortion is measured by using the DFT on the output signalat the input sine with frequency of 500 MHz and amplitude of 10 mV. Determinethe magnitude of the third harmonic and subtract it from the fundamental.The formula in the cadence design environment is:

DFT = dft((V T (”/V outP”)−V T (”/V outN”)) 0 1e−07 512 ”Rectangular” 1 ”default”).(A.6)

By using above equation A.6,

value(dB20(DFT ) (3×V AR(”trfreq”)))−value(dB20(DFT ) V AR(”trfreq”)).(A.7)

• Output differential voltage is measured by taking the maximum difference ofthe output voltage.The formula in the cadence design environment is:

ymax((V T (”/V outP”)− V T (”/V outN”))). (A.8)

3. Transient and DC simulationThe following parameter requires the transient and the DC simulation during testing.

• Input referred offset voltage is measured by dividing the output offset voltageby the gain of the amplifier.The formula in the cadence design environment is:

V DC(”/V outP”)− V DC(”/V outN”)ymax(V T (”/V outP”)−V T (”/V outN”))ymax(V T (”/V inP”)−V T (”/V inN”))

. (A.9)

4. AC simulationThe following parameters will be checked by the AC simulation.

• Bandwidth is measured by the −3 dB crossing of the output signal at highfrequency.The formula in the cadence design environment is:

cross(dB20(V F (”/V outP”)− V F (”/V outN”)

ymax(abs(V F (”/V outP”)− V F (”/V outN”))))−3 1 ”falling” nil nil).

(A.10)

• Lower cut-off frequency is measured by the −3 dB crossing of the outputsignal at low frequency.The formula in the cadence design environment is:

cross(dB20(V F (”/V outP”)− V F (”/V outN”)

ymax(abs(V F (”/V outP”)− V F (”/V outN”))))−3 1 ”rising” nil nil).

(A.11)

• Transfer function is measured by the AC sweep from 0 to 10 GHz.The formula in the cadence design environment is:

dB20(V F (”/V outP”)− V F (”/V outN”)

V F (”/V inP”)− V F (”/V inN”)). (A.12)

A.1. NORMAL OPERATION SIMULATION

APPENDIX A. SIMULATION PLAN 88

• AC gain is measured by the sine input of amplitude 500 mV and frequency10 MHz.The formula in the cadence design environment is:

value(dB20(V F (”/V outP”)− V F (”/V outN”)

V F (”/V inP”)− V F (”/V inN”)) 1000000). (A.13)

5. Noise simulationThe following parameter will be checked by the noise simulation.

• Input referred noise power is measured by integrate the noise spectrum overthe normalized transfer function of the amplifier.The formula in the cadence design environment is:

dB20(integ((V N2()

V F (”/V outP”)−V F (”/V outN”)V F (”/V inP”)−V F (”/V inN”)

) 0 1e+ 09)). (A.14)

6. Parametric TransientThe following parameter will be checked by the parametric transient simulation.

• Transient gain is measured by applying the input sine wave at frequencies: 100,400 and 800 MHz with amplitudes: of 50, 350 and 600 mV.The formula in the cadence design environment is:

ymax(V T (”/V outP”)− V T (”/V outN”))

ymax(V T (”/V inP”)− V T (”/V inN”)). (A.15)

7. Parametric Transient and DCThe following parameter will be checked by the parametric, the transient and the DCsimulations.

• Output differential voltage is measured to check the waveform of the outputvoltage for the spikes.The formula in the cadence design environment is:

(V T (”/V outP”)− V T (”/V outN”)). (A.16)

• Gain is measured by changing the five bits digital control signal and apply thesmall DC input signal. This simulation is performed to check the output for themonotonicity, the step size and the gain range.

A.1. NORMAL OPERATION SIMULATION

Appendix B

Gain setting decoder verilogAcode

// −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

// Fraunhofer I IS − ICD Simulat ion Model

// −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

// Author ( s ) :// azmatrn//// Function :// Mapping o f ga in s e t t i n g f o r VGA to get incrementa l ga in// from VGA.

// −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

// L i t e r a t u r e :////// Dependencies :// Library ( s ) :// d i s c i p l i n e . h// constant . h//// Pin d e s c r i p t i o n :// d<0:6> : 7 b i t d i g i t a l input data// f1<0:6> : 7 b i t f i n e f i r s t s tage gain s e t t i n g// f2<0:6> : 7 b i t f i n e second s tage gain s e t t i n g//// Parameter d e s c r i p t i o n :// t r f = Ris ing and f a l l i n g t r a n s i t i o n time o f data stream [ Sec ]// vsupply = Voltage to output f o r Logic 1 [V]//

89

APPENDIX B. GAIN SETTING DECODER VERILOGA CODE 90

// Simulat ion ( s ) :// tran//

// Veri logA f o r azmat rn t e s t l i b , D e c o d e r g a i n s e t t i n g 7 B i t s ,// v e r i l o g a

‘ i n c lude ” cons tant s . vams”‘ i n c lude ” d i s c i p l i n e s . vams”

module D e c o d e r g a i n s e t t i n g 7 B i t s (d , f1 , f 2 ) ;input [ 0 : 6 ] d ;output [ 0 : 6 ] f1 , f 2 ;e l e c t r i c a l [ 0 : 6 ] d ;e l e c t r i c a l [ 0 : 6 ] f1 , f 2 ;

parameter r e a l t r f = 10p from [ 0 : 1 0 n ) ;parameter r e a l vsupply = 1 . 8 ;

i n t e g e r in [ 0 : 6 ] , inputdata ;i n t e g e r f ine1 , f i ne2 , f f 1 [ 0 : 6 ] , f f 2 [ 0 : 6 ] ;i n t e g e r count1 , count2 , i ;genvar i 1 ;

analog begin//Get input gain s e t t i n g f o r mapping from input pin

f o r ( i 1 =0; i1<=6; i 1=i 1 +1) begin

in [ i 1 ] = V(d [ i 1 ] ) / vsupply ;

endcount1 = 0 ;count2 = 0 ;inputdata = 0 ;

// Binary array to decimal s c a l a r conver s i on

f o r ( i =0; i<=6; i=i +1) begininputdata = in [ i ]∗pow(2 , i ) + inputdata ;

end

// $d i sp l ay (” Input Data i s =%d” , inputdata ) ;

//Map the input gain s e t t i n g to d e s i r e d gain s e t t i n g

f o r ( i =0; i<=inputdata ; i=i +1) begin

// F i r s t f i n e s tage gain s e t t i n g

i f ( i == 0) begin


f i n e 1 = 0 ;end e l s ei f ( ( i <=4) | |( i>=6 && i <=8) | |( i>=10 && i <=16)) begin

f i n e 1 = f i n e 1 + 1 ;end e l s ei f ( i==5 | | i==9 | | i==17 | | i ==33) begin

f i n e 1 = f i n e 1 ;end e l s ei f ( i>=18 && i<=32) begin

f i n e 1 = f i n e 1 +2;end e l s ei f ( i>=34 && i<=42) begin

f i n e 1 = f i n e 1 + 4 + count1 ;count1 = count1 + 1 ;

end e l s ei f ( i==43 | | i==50 | | i==56 | | i==63 | | i ==70) begin

f i n e 1 = 102 ;end e l s ei f ( ( i>=44 && i <=49) | |( i>=51 && i <=55) | |

( i>=57 && i <=62) | |( i>=64 && i <=69) | |( i ==71)) beginf i n e 1 = f i n e 1 + 4 ;

end e l s ei f ( i == 72) begin

f i n e 1 = 118 ;end e l s ei f ( i == 73) begin

f i n e 1 = 127 ;end

// Second f i n e s tage ge in s e t t i n g

i f ( i <= 4) beginf i n e 2 = 0 ;

end e l s ei f ( ( i>=6 && i <=8) | |( i>=10 && i <=16) | |

( i>=18 && i <=32) | |( i>=34 && i <=42)) beginf i n e 2 = f i n e 2 ;

end e l s ei f ( i==5 | | i==9 | | i==17 | | i ==33) begin

f i n e 2 = f i n e 2 + 1 ;end e l s ei f ( i == 43) begin

f i n e 2 = 7 ;end e l s ei f ( i>=44 && i<=49) begin


f i n e 2 = 18 ;end e l s ei f ( ( i>=51 && i <=55) | |( i>=57 && i <=62)) begin




f i n e 2 = 64 ;end e l s ei f ( i>=64 && i<=69) begin





f i n e 2 = 127 ;end

end

// $d i sp l ay (” Fine 1 gain s e t t i n g i s =%d” , f i n e 1 ) ;// $d i sp l ay (” Fine 2 gain s e t t i n g i s =%d” , f i n e 2 ) ;

// Decimal s c a l a r to binary array conver t i on

f o r ( i =0; i<=6; i=i +1) beginf f 1 [ i ] = f i n e 1 % 2 ;f i n e 1 = f i n e 1 / 2 ;f f 2 [ i ] = f i n e 2 % 2 ;f i n e 2 = f i n e 2 / 2 ;

end

// Generate mapped gain s e t t i n g on output p ins

f o r ( i 1 =0; i1<=6; i 1=i 1 +1) beginV( f1 [ i 1 ] ) <+ t r a n s i t i o n ( f f 1 [ i 1 ]∗ vsupply , 0 , t r f , t r f ) ;V( f2 [ i 1 ] ) <+ t r a n s i t i o n ( f f 2 [ i 1 ]∗ vsupply , 0 , t r f , t r f ) ;

endend

endmodule

Bibliography

[1] IEEE Std 802.3-2002, Section Three, Annex 40B.

[2] Behzad Razavi, ”Design of Analog CMOS Integrated Circuits,” ISBN 0-07-118839-8.

[3] Don Tuite, ”Design variable gain ampliifer,” Analog Devices.

[4] David M. Binkley, ”Tradeoffs and optimization in analog CMOS design,” ISBN 978-0-470-03136-0.

[5] Huy-Hieu Nguyen, Hoai-Nam Nguyen, Jeong-Seon Lee, and Sang-Gug Lee, “A binary-weighted switching and reconfiguration-based programmable gain amplifier,” IEEETransactions on Circuits and Systems-II: Express Briefs, vol. 56, no. 9, pp. 699-703SEPTEMBER 2009.

[6] Oscar E. Agazzi, Fellow, IEEE, Mario R. Hueda, Diego E. Crivelli, Hugo S. Carrer,Ali Nazemi, Germn Luna, Facundo Ramos, Ramiro Lpez, Carl Grace, Member, IEEE,Bilal Kobeissy, Cindra Abidin, Mohammad Kazemi, Mahyar Kargar, Csar Marquez,Sumant Ramprasad, Federico Bollo, Vladimir Posse, Stephen Wang, Georgios Asmanis,George Eaton, Member, IEEE, Norman Swenson, Tom Lindsay, and Paul Voois, “A90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic DispersionCompensation of Multimode Optical Fibers at 10 Gb/s,” IEEE Journal of Solid-StateCircuits, vol. 43, no. 12, pp. 2939-2957, DECEMBER 2008.

[7] R. Jacob Baker, ”CMOS Circuit Design, Layout, And Simulation,” Second Edition.

[8] Thomas H. Lee, ”Voltage References and Biasing,” 1993, rev. November 27, 2002.

[9] Hui Dong Lee, Student Member, IEEE, Kyung Ai Lee, and Songcheol Hong, Mem-ber, IEEE, ”A Wideband CMOS Variable Gain Amplifier With an Exponential GainControl,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 6, pp.1363-1373, JUNE 2007.

[10] Yanjie Wang, Bagher Afshar, Tuan-Yi Cheng, Vincent Gaudet and Ali M. NiknejadBerkeley Wireless Research Center, University of California, Berkeley, CA, USA, 947072 University of Alberta, Edmonton, Canada T6G 2V4, ”A 2.5mW Inductorless Wide-band VGA with Dual Feedback DC-Offset Correction in 90nm CMOS Technology,”IEEE Radio Frequency Integrated Circuits Symposium, pp. 91-94, 2008.

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