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Today’s topics

MemoryMemory byte ordering

BusesBuses Peripheral devicesPeripheral devices I/OI/O Intel IA-32 architectureIntel IA-32 architecture Intel IA-32 assembly languageIntel IA-32 assembly language

instruction formats addressing modes

Introduction to MASMIntroduction to MASM

Tying things together:the internal bus

Control Unit, ALU, Registers, Addressing Unit communicate via a bus.

Speed depends on Bus width: number of bits that can transfer

simultaneously Bus length

Synchronous vs asynchronous buses Synchronous means “tied to clock pulse”

Bus arbitration Multiple buses

MemoryMemory Cells with addressesCells with addresses

each cell contains (usually 8) ordered bitseach cell contains (usually 8) ordered bits most common definition of "byte"most common definition of "byte" n-bit byte can represent 2n-bit byte can represent 2nn different "codes" different "codes"

addresses are sequential bit patternsaddresses are sequential bit patterns m-bit address can specify 2m-bit address can specify 2mm cells cells e.g., a 32-bit address supports approx. 4Ge.g., a 32-bit address supports approx. 4G

Cells may be grouped into Cells may be grouped into wordswords word size (bits) = memory bus sizeword size (bits) = memory bus size

Some machines use "byte-addressable" Some machines use "byte-addressable" memory; others use "word-memory; others use "word-addressable"addressable"

Byte-orderingByte-ordering When it takes more than one byte to When it takes more than one byte to

represent a value …represent a value … Big-endianBig-endian

Bytes ordered left Bytes ordered left right (most significant to right (most significant to least significant) in each wordleast significant) in each word

Used in Motorola architectures (Mac) and othersUsed in Motorola architectures (Mac) and others Little-endianLittle-endian

Bytes ordered least significant to most significant Bytes ordered least significant to most significant in each wordin each word

Used in Intel architecturesUsed in Intel architectures In both schemes, bit values are stored left In both schemes, bit values are stored left

right within each byte (each character is one right within each byte (each character is one byte).byte).

In both schemes, strings are stored in byte In both schemes, strings are stored in byte order.order.

Problem:Problem: communicating between communicating between architectures.architectures.

Byte-orderingByte-ordering Example 32-bit integer: -1234Example 32-bit integer: -1234

11111111 11111111 11111011 0010111011111111 11111111 11111011 00101110Byte3 Byte2 Byte1 Byte0Byte3 Byte2 Byte1 Byte0

Big-endian Big-endian (big end first)(big end first)Memory addresses:Memory addresses:10041004 10051005 10061006 100710071111111111111111 1111111111111111 1111101111111011 0010111000101110Byte3Byte3 Byte2Byte2 Byte1Byte1 Byte0Byte0

Little-endian Little-endian (little end first)(little end first)Memory addresses:Memory addresses:10041004 10051005 10061006 100710070010111000101110 1111101111111011 1111111111111111 1111111111111111Byte0Byte0 Byte1Byte1 Byte2Byte2 Byte3Byte3

Byte Ordering (4 32-bit numbers)Byte Ordering (4 32-bit numbers)

(a) Big endian memory (a) Big endian memory (b) Little endian memory (b) Little endian memory

More tying things together:

the memory bus CPU - memory communicate via a bus.

Bus width Bus length

Synchronous / asynchronous Bus arbitration Multiple buses Pipelining

Interfacing

I/O devices Keyboard, mouse, etc Monitor, printer, etc. Network interface, modem, etc.

Secondary storage devices Disks Memory sticks Etc.

Types of magnetic disks and configurations

Tracks and sectors Floppy disk Hard disk

Integrated Drive Electronics (IDE, EIDE) Small Computer System Interface (SCSI,

ultra SCSI) Redundant Array of Inexpensive Disks

(RAID) Levels

Others

Magnetic Disk Fundamentals

Tracks and Sectors

Magnetic Disk Fundamentals Disk drives rotate at 3,600 to 12,000

RPM Transfer rate : speed of data

transfer between disk drive and computer Disk bandwidth is the (total number of

bytes transferred) / (total time from first request for service to completion of last transfer).

Access time : has two major components Seek time is the time for the disk to

move the heads to the cylinder containing the desired sector.

Rotational latency is the additional time waiting for the disk to rotate the desired sector to the disk head.

RAID Structure

RAID – multiple disk drives provides reliability via redundancy. Short for Redundant Array of Independent Disks

RAID (cont)

Techniques involve the use of multiple disks working cooperatively.

Disk striping uses a group of disks as one storage unit.

CDROM, CDR, CDRW, DVD

Compared to magnetic media, larger capacity, slower response

“Pits” and “lands” in continuous spiral Burned by high-power LASER Read by low-power LASER

Recordable (once) or rewritable DVD

Enhanced CD technology Several formats (sides and layers)

Memory Hierarchy

From bottom to top: speed increases capacity

decreases cost/bit increases

I/O Hardware

Variety of I/O devices Keyboard, mouse, game device,

monitor, printer, scanner, etc. Many specialized devices

Common concepts Port (internal/external, physical/logical) Bus (shared direct access / daisy chain ) Controller (host adapter)

I/O instructions control devices

Even more tying things together: the I/O bus

CPU / memory communicate with I/O unit via a bus. Bus width Bus length

Synchronous / asynchronous Bus arbitration Multiple buses

End of general architecture section (for now)

Begin analysis of a specific example architecture

Intel IA-32 Architecture CISC Multi-stage pipeline Modes of operation:

Protected Real-address

Intel IA-32 architecture Specific hardware implementations

registers memory addressing scheme

Specific instruction set and microprograms

Architecture-specific assembly languages MASM, NASM, TASM, etc,

Architecture-specific operating systems DOS, Windows, Linux, UNIX, etc.

Intel IA-32 architecture Byte is the smallest unit of data that

can be manipulated directly Operating system and instruction

decoder determine how bytes are interpreted integer character floating-point instruction address status bits

Intel IA-32 architecture Most instructions manipulate

registers, memory, and/or the ALU Some instruction check the status

register Other components are manipulated

by micro-programs

Intel Architecture: IA-32 Memory

Up to 4G Byte-addressable Little-endian

Registers High-speed temporary storage in CPU Some general-purpose, some special-

purpose Arithmetic/logic unit (ALU)

All arithmetic operations and comparisons are done here

Intel Architecture: IA-32 Two processors in one

integer unit floating-point unit

Can work in parallel (co-processors) Separate instruction sets Separate data registers

different configuration Separate ALUs

Integer Unit Registers8 x 32-bit “general” registers

EAX EBP

EBX ESP

ECX ESI

EDX EDI

2 x 32-bit special registers 6 x 16-bit segment registers

EFLAGS CS ES

EIP SS FS

DS GS

32-bit registers Can be addressed as 16-bit registers Some can be addressed as 8-bit registers Examples

AX refers to the least-significant 16-bits of EAX AL refers to the least-significant 8-bits of AX AH refers to the most-significant 8-bits of AX

A H A L 8-bit

A X 16-bit

E A X 32-bit

Integer unit registers

Operations are defined for individual registers (e.g., INC EAX) most pairings of registers (e.g., ADD EAX, EBX)

Specialized uses of general-purpose registers EAX and EDX are automatically used by integer

multiplication and division instructions ECX is automatically used as a counter for

some looping instructions Etc.

Floating-point Unit (FPU) Registers

80-bit registers

0

1

2

3

4

5

6

7

FPU Registers Used as a stack If more than 8 values are pushed, the

"bottom" of the stack will be lost Operations are defined for the "top"

one or two registers e.g., FPUSH 32.75 e.g., FADD ;pop top 2, add, and push result

may be referenced by name %st(x)

There’s only one set of registers for each unit!

Something like global variables Sometimes have to be saved and

restored.

Most register instructions (for now) reference EAX, EBX, ECX, and/or EDX

Assembly language

Assembly language provides:1. Set of mnemonics for machine

instructions• Opcodes and addressing modes

2. Mechanism for naming memory addresses and other constants.

• Note: a named memory address is usually called a "variable"

3. Other "pseudo-instructions"4. Other "conveniences" for developing

source code for a particular machine architecture

Assembler and assembly

Assembly language program (text)

source code

Assembler

Target machine code (binary)

object code

Why use assembly language?

Easier than machine code Access to all features of target

machine Performance (maybe) Using mixed languages Note that assembly language tends

to migrate toward a high-level language advanced features (“auto” loop control,

etc.) libraries

Assembly language directly controls …

Examples

registers mov eax, 10

memory mov myVar, 59

ALU add eax, myVarcmp eax, 100

program branching jle quitcall myProc

input/output int 21h

An assembly language is defined for one particular

architectureTechnically, each assembly language instruction corresponds to one machine instruction

Here’s the complete list of instructions for Intel IA-32

Lots of technical information here. For now just check the description, syntax, and examples. immed means a literal value mem means a memory reference reg means a general register (some specify size e.g., reg16 )

accum means the EAX register (or one of its sub-registers)

Questions?Questions?

Read IrvineRead Irvine Chapters 2, 3Chapters 2, 3