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Interfacing MEMORY and

I/O devices WITH 8085

Introduction – RAM,ROM,EPROM

• The programs and data which are executed by the

microprocessor have to be stored in ROM/EPROM and

RAM which are basically semiconductor memory chips.

• The programs and data which are stored in ROM/EPROM

are not erased even-though the power supply to the

ROM/EPROM chip is removed.

• Hence the ROM/EPROM are called non-volatile memory

and we can use them to store permanent programs such

as monitor program and data such as look up table,

which are needed in microprocessor based systems.

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Difference –

RAM,ROM,EPROM • The difference between ROM and EPROM is that

ROM chip is programmable only one timewhereas an EPROM chip can be programmedmany times after erasing the previously storedcontents in it, by passing UV rays for few minutesthrough the quartz window situated at the top ofthe EPROM chip.

• The programs and data which are stored in RAMare erased when the power supply to the RAMchip is removed and hence RAM is called volatilememory.

RAM - Introduction

• Program and data which are often changed such asprogram written during the development processof software for a microprocessor based system,program written during the learning of assemblylanguage programming and data entered whiletesting the above programs, are stored in RAM.

• RAM is also used to store data which are variablein nature such as parameters entered by the userfor a particular operating condition, in amicroprocessor based system.

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• Data can be only read from ROM or EPROMafter programming it whereas in RAM, datacan be read or written by themicroprocessor.

• In this chapter, the interfacing of EPROM andRAM chips with 8085 using address decodersconstructed using logic gates and decoder ICsuch as 74LS138 are discussed.

RAM - Introduction

Introduction

Logic Diagram for EPROM Logic Diagram for RAM

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Interfacing memory chips with 8085

• 8085 has 16 address lines namely (A15 to A0), amaximum of 64Kbytes (=216) memory can beinterfaced with 8085 and the memory address space of8085 (i.e. range of memory addresses that can begenerated by 8085) has the value from 0000H to FFFFHwhen represented in hexadecimal form.

• While executing a program stored in memory, the 8085microprocessor needs to access memory regularly toread the instructions and data stored in memory andalso to store the result to memory.

Interfacing memory chips with 8085

8085 Memory

Address Lines

Data Lines

Control Lines

Interface

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Interfacing memory chips

with 8085 contd..

• The 8085 initiates a set of signals and when it

wants to read from and write into memory

and the memory chip has certain signals such

as chip Enable or Chip Select, or Output

Enable or Read and or Write Enable or Write.

• The memory interfacing circuit must match

the above 8085’s signals with the memory

chip’s signals.

Generation of control signals for

memory

• Two control signals namely (Memory Read) and (Memory

Write) are generated for memory such that alone is at logic 0

during memory read operation from RAM or EPROM and

alone is at logic 0 during memory write operation into RAM.

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Generating Control Signals

MIO/

Memory

ReadMemory Write

IO Read

IO Write

RD=

0WR=

1

=01

1

0

0

1

1

0

0

13

Circuit used to generate and signals

MIO/

Memory

Read

IO Read

IO Write

RD=

1

=01

1

0

0

0

0

1

1

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Circuit used to generate and signals

MIO/

Memory

ReadMemory Write

IO Read

IO Write

=10

0

1

1

1

1

0

Circuit used to generate and signals

MIO/

Memory

Read

IO Read

IO Write

RD=

1

=10

0

1

1

0

0

1

1

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Relation between 8085’s control

signals and memory control signals

•When the signal is at logic high level, both memory

control signals are deactivated (i.e. at logic high)

independent of the status of and signals which is

shown in the third row.

Interfacing EPROM chip with 8085

Pin Diagram of IC 2764

• There are 8192 locations (8K=8x210 =8192)

in the IC 2764 and in each location, one

byte of information (instruction or data) is

stored.

• There are 13 address lines (Since 213 =8K)

namely A12 to A0 present in IC 2764 where

A0 is the least significant bit of the address

and A12 is the most significant bit of the

address.

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Steps to read content of Memory

Location

• In order to read the content of a memory locationin EPROM chip, the following steps are done

• The address of the memory location from wheredata has to be read is placed in the address linesof EPROM.

• CE signal is made logic low (i.e. 0)

• OE signal is made logic low(i.e. 0)

• Now the data in the selected memory locationwill be available in the data lines (D7-D0) ofEPROM.

Selection of memory location for various

values of address inputs in IC 2764

• 8085 has 16 address lines (A15-A0) and hence it can be interfaced

with maximum memory size of 64K bytes (= 216 bytes)

• The address range of the memory can vary from 0000H to FFFFH and

this is known as memory space of 8085

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Interfacing EPROM chip with

8085 using decoder IC• Whenever many number of same capacity

memory chips have to be interfaced with

8085, decoder IC with active low outputs

such as 74LS138 is very useful.

• By using a single 74LS138 IC, maximum of

eight memory chips (RAM and EPROM)

can be interfaced with 8085.

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Logic diagram of 74LS138

decoder IC

Truth table of 74LS138

decoder IC

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Introduction - 74LS138

decoder IC

• 74LS138 decoder IC has three select inputs namely A (LSB), B and C

(MSB) and three enable inputs namely G1,

• G2 represents the two active low enable signals of 74LS138 namely

and .

• Only when G1=1 and = = 0, 74LS138 functions as decoder and under

that condition depending upon the value in the select inputs, one of

the outputs will be low (i.e. 0) as shown in table 6.6.

• If either G1=0 or =1 or =1 then all of its outputs are 1, independent

of the value in the select inputs.

• In table 6.6, X represents don’t care condition which means the

input can be either 0 or 1.

G2A

74LS138 decoder IC

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Interfacing EPROM chips

using 74LS138 Decoder

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Truth table for the 6264 IC (8K x 8)

RAM chip

6264 IC (8K x 8) RAM chip

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6264 IC (8K x 8) RAM chip

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6264 IC (8K x 8) RAM chip

Partial address decoding:

• In the methods so far discussed, the entireaddress bus of 8085 (A15 to A0) is used tointerface memory chips with 8085 and thistechnique is called absolute address decoding.

• Using the absolute address decoding method,maximum of 64 Kbytes of memory can beinterfaced with 8085.

• There is another method known as partial addressdecoding which is used when the amount ofmemory needed in an 8085 based system is lessthan 64 Kbytes such as 8K or 16K or 32K.

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• In the partial address decoding method, all theaddress lines of 8085 are not used in interfacingwith memory.

• In the partial address decoding method, the lowerorder address lines of 8085 are connected to theaddress lines in memory chip same as in theabsolute address decoding method and some ofthe higher order address lines of 8085 are leftunconnected and only few higher order lines of8085 are connected to the chip enable signal ofmemory through address decoder.

• Hence the size of the address decoder getsreduced and sometimes the amount of hardware(number of gates) needed for interfacing isreduced in the partial address decoding method.

• At the same time for the same memory chip,different address ranges will get assigned in thepartial address decoding method and any one ofthe address ranges can be used to access thememory.

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I/O or Peripheral mapped I/O

• In this method, the I/O devices are treated separately frommemory.

• The control signals I/O read ( ) and I/O write ( ) which arederived from , and signals of 8085, are used to activateinput device and output device respectively.

• IN instruction and OUT instruction of 8085 are used toaccess the input device and output device respectively.

• Each I/O device is identified by a unique 8-bit addressassigned to it. Since 8-bit address is used for each I/Odevice, a maximum of 256 (=28) input devices and amaximum of 256 (=28) output devices can be interfacedwith 8085 since the control signal used to access inputdevices and output devices are different.

Generation of signals

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Status signals in 8085• Table shows the values in, and lines of

8085 during the I/O read and I/O write

operation and the corresponding values in

the signals and during the above

operations.

Memory mapped I/O

• In memory mapped I/O, each input device oroutput device is treated as if it is a memorylocation.

• The control signal is used to activate the inputdevice and the control signal and is used toactivate the output device.

• Each input or output device is identified by aunique 16-bit address same as 16-bit memoryaddress assigned to a memory location.

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• All the memory related instructions used to read datafrom memory such as LDA 2000H, LDAX B and MOV A,M, …etc. can be used to access input device and all thememory related instructions used to write data intomemory such as STA 3000H, STAX D and MOV M, A,…etc can be used to send data to output device.

• Since the I/O devices use some of the memory addressspace of 8085, the maximum memory capacity(EPROM & RAM capacity) will be less than 64K bytes inthis method.

Partial address decoding

• the entire address bus of 8085, (i.e. A7 to A0

in I/O mapped I/O scheme and A15 to A0 in

memory mapped I/O scheme) is used to

interface I/O devices with 8085 and this

technique is called absolute address decoding.

• Partial address decoding can also be used in

both the schemes

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• In this method, for a single I/O device there will

be more than one address and any one of them

can be used to access it.

• Here the address lines which are not used in the

interfacing are considered as don’t care condition

(i.e. either 0 or 1) and then depending on the way

the remaining address lines are connected to the

address decoder, the addresses assigned to the

I/O device are found out.