memory and programmable logic chapter 7. introduction ram: random access memory rom: read only...
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Memory and Programmable Logic
Chapter 7
Introduction
• RAM: Random Access Memory• ROM: Read Only Memory• Write operation: Storing info into memory• Read operation: Transferring info out of the memory• RAM can perform both Write and Read operations• ROM is a Programmable Logic Device (PLD) that can be
written once and can only be read afterwards• PLA: Programmable Logic Array• PAL: Programmable Array Logic• FPGA: Field Programmable Gate Array
Conventional and array logic diagrams
Random Access Memory
• Memory unit that can be written or read• Memory is composed of “words”• Word is a group of bits• Byte is a group of 8 bits (Denoted B)• Words can have one or more bytes: a word of
32 bits has 4 bytes• Memory size is normally measured in bytes,
e.g., 1024 bytes = 1KB
Random Access Memory
• When word size is known memory size can be given in words, e.g., 1 word = 64 bits = 8 bytes.
• 1K requires 10 bits address, i.e., 1024 = 210
• 1M = 220
• 1G = 230
• 4G = 232
• Each word has an id. number called an address (0 to 2k`-1, where k is the # of address lines)
Random Access Memory
Random Access Memory
Contents of a 1K x 16 memory
Write and read operations
• Read and write take the same time, regardless of location; contrast with magnetic tape; read may take different time from write operation
• Write: transfer-in operation
• Read: transfer-out operation
Write and read operations
• Steps to store a new word into memory1. Apply binary address of desired word to address
lines (k)2. Apply data bits that must be stored in memory
to data input lines (nin)
3. Activate the write input• Memory unit will take bits from input data
lines and store them in word specified by address lines
Write and read operations
• Steps to read a word out of memory1. Apply desired binary address of desired word to
address lines2. Activate the read input
• Memory unit will take bits from word specified by address lines and apply them to output data lines
Write and read operations
Control inputs in typical commercial memory chips
Timing waveforms
Cycle time: time required to finish a write operation
Timing waveforms
access time: time required to finish a read operation
Timing waveforms
CPUCLK
T = 1/fCLK
Cycle Time(i.e. Write Time)
ADDRESS ADDRESS VALID
MEMORY SELECT
DATA VALID FOR WRITEDATA VALID FOR READ
Types of memories
• Static RAM or SRAM: consists of internal latches that store binary information
• Dynamic RAM or DRAM: stores information in form of electric charge on capacitors provided by MOS transistors inside the chip, thus requires refresh every few ms
• Volatile memory lose stored information when powered off. Magnetic memory is nonvolatile. ROM is another type of nonvolatile memory
Types of memories
• DRAM refreshing requires cycling through words every few ms to restore decaying charge
• DRAM offers reduced power consumption and larger storage capacity in a single chip
• SRAM is easier to use
Bonus Assignment: find out what Flash Memories are and how they are used
Memory Decoding
Memory Decoding
Coincident decoding• Decoder with k
inputs and 2k outputs requires 2k AND gates
• A 1K memory requires a 10x1024 decoder
• Use instead a 2-D selection patter and 1K requires two 5x32 decoders!
• Word is selected by coincidence of one X and one Y line
MSB
LSB
Address multiplexing• SRAMs contain 6 transistors per cell• DRAMs contain one MOS transistor and one
capacitor per cell• DRAMs achieve higher storage capacity per unit
area – four times that of a SRAM - and lower power consumption
• DRAM typical word size = 1 bit• DRAM is preferred for large memories for PCs• DRAM available from 64K to 256M bits• To reduce number of pins, thus chip size, use
address multiplexing
Address multiplexing
• Capacity = 256x256 = 28x28 =64K
• RAS = Row Address Strobe
• CAS = Column Address Strobe
Error Detection and Correction
• Dynamic physical interaction of electrical signals may cause occasional errors
• Memories can use two types of codes:– Error detection codes, parity (chapter 3)– Error correction codes
Error Detection and Correction
• Hamming code– Error correction code– Uses several parity bits per word– Can detect and correct 1-bit errors
Hamming codeBit position
1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0
𝑃1=𝐸𝑋𝑂𝑅 (3,5,7,9,11)𝑃2=𝐸𝑋𝑂𝑅(3,6,7,10,11)𝑃4=𝐸𝑋𝑂𝑅 (5,6,7,12)𝑃8=𝐸𝑋𝑂𝑅(9,10,11,12)
Parity generation equations
Check bit equations (Syndrome)
𝐶1=𝐸𝑋𝑂𝑅(1,3,5,7,9,11)𝐶 2=𝐸𝑋𝑂𝑅(2,3,6,7,10,11)𝐶4=𝐸𝑋𝑂𝑅 (4,5,6,7,12)𝐶8=𝐸𝑋𝑂𝑅 (8,9,10,11,12)
Hamming code
Bit 1 2 3 4 5 6 7 8 9 10 11 12
No error 0 0 1 1 1 0 0 1 0 1 0 0
Bit 1 error 1 0 1 1 1 0 0 1 0 1 0 0
Bit 5 error 0 0 1 1 0 0 0 1 0 1 0 0
Hamming code
Position of error
C8 C4 C2 C1
No error 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 0 0 0
Syndrome
Single-error correction, double-error detection
Read-Only Memory
Read-Only Memory
Read-Only Memory
Read-Only Memory
ROM programming according to table 7.3
Combinational circuit implementation
• ROM uses a decoder for address and decoder gives minterms
• Outputs use OR gates thus ROM can be seen as:– A storage device– Combinational circuit implementing Boolean
functions
Combinational circuit implementationExample
Example 7.1: ROM-based circuit that accepts a three-bit number and produces a binary number equal to the square of the input number.
Combinational circuit implementationExample
Types of ROM
• Mask programming: done by semicondutor company during last fabrication process of unit
• PROM (Programmable ROM): Programming by blowing fuses by applying a high voltage; blown fuse outputs a 0
• EPROM (Erasable PROM): Erase using special ultraviolet light
• EEPROM or E2PROM (Electrically Erasable PROM)
Combinational PLDs
Programmable Logic ArrayExercise: Obtain the equations for this PLA. What role do the EXOR gates play?
Programmable Logic Array
Example 7.2
Implement the following two Boolean functions with a PLA:
𝐹 1 ( 𝐴 ,𝐵 ,𝐶 )=∑ (0,1,2,4 )𝐹 2 ( 𝐴 ,𝐵 ,𝐶 )=∑ (0,5,6,7 )
What do we have to do?
Obtain minimum number of terms as sum of products
𝐹 1 ( 𝐴 ,𝐵 ,𝐶 )=𝐴′ 𝐵 ′+𝐴 ′𝐶 ′+𝐵 ′𝐶 ′
𝐹 2 ( 𝐴 ,𝐵 ,𝐶 )=𝐴𝐵+ 𝐴𝐶+𝐴 ′ 𝐵 ′𝐶 ′
Programmable Array Logic
Example of PAL Programming
Example of PAL Programming
Sequential Programmable Devices
Sequential Programmable Devices
• SPLD: Sequential Programmable Logic Device
• CPLD: Complex Programmable Logic Device
Sequential Programmable Devices
Basic macrocell logic
Sequential Programmable Devices
CPLD
Sequential Programmable DevicesArchitecture of Xilinx Spartan FPGA (Field Programmable Gate Array
Sequential Programmable DevicesConfigurable Logic Block (CLB)
Sequential Programmable Devices
RAM cell controlling a PIP transmission gate
Exercises
• 7.1• 7.2• 7.3• 7.4• 7.6• 7.7• 7.8• 7.9
• 7.10• 7.14• 7.15• 7.18• 7.19• 7.20• 7.23• 7.24
P7.26
Sequential Programmable Devices
IOB of XC4000 Series