Lecture 9• Strained-Si Technology I: Device Physics

– Background– Planar MOSFETs– FinFETsReading: • Y. Sun, S. Thompson, T. Nishida, “Strain Effects in

Semiconductors,” Springer, 2010.• multiple research articles (reference list at the end of

this lecture)

Strain Analysis in Daily Life

Mechanical Stress/Strain Analysis

10/29/2013 2Nuo Xu EE 290D, Fall 2013

Stress Tensor

Fn

Fs

Stress = lim

L ∆L

Strain = lim

Stress:results from the repulsiveelectromagnetic force betweenionic cores when the latticeatoms deviate from theirequilibrium positions.

Stress Types

Extensional Shear

Tensile

Compressive

Strain-Stress Relationship

10/29/2013 3Nuo Xu EE 290D, Fall 2013

Elasticity Tensor:• assuming strain has linear

response to stress (Hooke’s Law)

• can be simplified into 3 independent variables, for cubic lattices (e.g. Si)

Extensional Strain/Stress

Shear Strain/Stress

OR for a certain direction:If x, y, z along main crystal axis:

Impact of Strain on Semiconductors

10/29/2013 4Nuo Xu EE 290D, Fall 2013

• Energy Band Splitting • E vs. k curvature change

Unstrained1GPa <110>Compressive

Si

Ge

GaAs

Y. Sun, JAP (2007)

w/o s w/ hs w/ usCB

VB

2

4

HHLH

Transport m*

Reduction

Strain Impact on Si Bandstructure: Planar N-MOSFET

10/29/2013 5Nuo Xu EE 290D, Fall 2013

Electrons

Δ2 Electron

Gate

Source Drain

Gate

Source Drain

Gate

Source Drain

Unstrained Longitudinal Vertical

Energy Splitting

[110]

E-k Curvature Change

applying strain

Lower DOS available for Scattering

Reduced (Inter-valley) Scattering Rates

Sub-band reoccupation

Lowered average m*

K. Uchida, IEDM (2008)

Strain Impact on Si Bandstructure:Planar P-MOSFET

10/29/2013 6Nuo Xu EE 290D, Fall 2013

Holes

Heavy HoleLight HoleSplit-off Hole

Gate

Source Drain

Gate

Source Drain

Gate

Source Drain

Unstrained Longitudinal Vertical

[110]

Transport m* Reduction

Energy Splitting E-k Curvature Change

applying strain

Lower DOS available for Scattering

Reduced (Inter-sub-band) Scattering Rates

Sub-band reoccupation

Lowered average m*

Strain Enhancement on Si MOSFET Carrier Mobility

D. Esseni, JCE (2009) F. Conzati, SSE (2009)

Electron Hole[110]

10/29/2013 7Nuo Xu EE 290D, Fall 2013

• For N-MOSFET, electron mobility enhancement saturates at ~1.5 GPa <110>-uniaxial tensile stress .

• For P-MOSFET, hole mobility enhancement saturates at very high <110>-uniaxial compressive stress.

Impact of Quantum Confinement

10/29/2013 8Nuo Xu EE 290D, Fall 2013

• N-MOSFET: e% degrades at higher Eeff, due to the quantum confinement counters the strain-induced sub-band splitting.

• P-MOSFET: h% maintains vs. Eeff due to the dominant m*

reduction.

Holes under Uniaxial Comp. Stress

E. X. Wang, TED (2006)

Electrons under Biaxial Tensile Stress

O. Weber, IEDM (2007)

Analytical Modeling for Carrier Mobility Enhancement due to Strain

10/29/2013 9Nuo Xu EE 290D, Fall 2013

• Piezoresistance (PR) Model

• Sub-band Reoccupation Model

Too simple Limited predictive ability

(by ignoring Eeff, Strain-dependence…)

Analytically models the energy-band top and m*

change vs. strain Trade-off between

computing loads and accuracy

J.-S. Lim, EDL (2004)

Numerical Approach: Self-Consistent Poisson-Schrödinger Simulation

10/29/2013 10Nuo Xu EE 290D, Fall 2013

0 22

30 22

30 22

0 22

32 2 022

32 2 02 2

LP Q L M M

L P Q M Q L

M P Q L L Q

LM L P Q M

L Q L M P

LM L Q P

22 2 2

10

( )2 x y zP k k km

22 2 2

20

( 2 )2 x y zQ k k km

2

30

3 ( )x y zL k ik km

22 2

2 30

3[ ( ) 2 )2 x y x yM k k i k km

2 2

* 2 ( ) ( ) ( )2 n n n

z

d e z z E zm dz

2

2( ) ( ) ( , )2

nn nk

k

gn z dk f E k z

( ) ( )nn

n z n z

( )( ) ( ) ( )D Ad d zz e N N p z n zdz dz

Schrödinger equation

Poisson equation

6x6 Luttinger-Kohn Hamiltonian for HolesscPS Approach

Impacts of strain on energy-band top as well as curvature change will be completely included into the Hamiltonian.

Computationally intensive.

Impact of Si Body Thickness Scaling

10/29/2013 11Nuo Xu EE 290D, Fall 2013

4 6 8 10 12 14

280

300

320

340

360

380

400

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

Ninv=1.0e13cm-2

Silicon Film Thickness (nm)

Elec

tron

Mob

ility

(cm

2 /V.s

)

1GPa Longitudinal Tensile 1GPa Vertical Compressive Unstrained

(100)/<110>

Electron Mobility C

hange (

e e )

40

60

80

100

120

140

160

4 6 8 10 12 14

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Hole M

obility Change (

h h )

Hol

e M

obili

ty (

cm2 /V

.s)

1GPa Longi. Comp. 1GPa Verti. Tens. 1GPa Trans. Tens. Unstrained

Silicon Film Thickness (nm)

Pinv=1.0e13cm-2(100)/<110>

N-Channel (Electron) P-Channel (Hole)

• Stress enhancement diminishes for electrons as tSOI scaledbelow 5nm, but not for holes.

[110]scPS simulations, N. Xu, VLSI-T (2011)

N-Channel (Electron) P-Channel (Hole)

Impact of tSi Scaling on Piezoresistive Coefficients

Open symbols Simulated Closed Symbols Measured

10/29/2013 12Nuo Xu EE 290D, Fall 2013

N. Xu, SOI Conf. (2012)

[110]

2 4 6 8 10 12-50

-40

-30

-20

-10

0

10

20 zz

xx

yy

Piez

o-C

oeffi

cien

t (10

-11 Pa

-1) Vertical zz

Transverse yy

Longitudinal xx

Uchida, IEDM 04,08Xu, VLSI 11

Silicon Body Thickness (nm)2 4 6 8 10 12

-60

-40

-20

0

20

40

60

80

Silicon Body Thickness (nm)

Piez

o-C

oeffi

cien

t (10

-11 Pa

-1)

xx

yy

zz

Longitudinal xx

Transverse yy

Vertical zz

Uchida, IEDM 08Xu, VLSI 11

• As tSi decreases, Πxx decreases due to diminished sub-band reoccupation and inter-valley scattering reduction.

Strain Enhancement on FinFET Carrier Mobility: Electrons

∆2,1st

∆4, 2nd

∆4, 1st

Unstrained Strained

10/29/2013 13Nuo Xu EE 290D, Fall 2013N. Serra, TED (2010)

[110]

(110)-sidewall N-FinFET(100)-sidewall N-FinFET

(110)-sidewall N-FinFET

Strain Enhancement on FinFET Carrier Mobility: Holes

10/29/2013 14Nuo Xu EE 290D, Fall 2013

Equi-energy contours from the 1st HH

[110]

[110]

Planar MOSFET(100)/<110>

FinFET(110)/<110>

unstrained σx = -1 GPa

Courtesy of L. Smith (Synopsys)

(100) Surface

(110) Surface

6 9 12 15 18 21 24-60

-40

-20

0

20

40

60

80

xx

yy

Saitoh, VLSI 08 Shin, EDL 06 Suthram, EDL 08

Piez

o-C

oeffi

cien

t (10

-11 P

a-1)

Silicon Fin Width (nm)

Xu, EDL 12 Serra, TED 10

zz

• No substantial degradation in piezo-resistance is seen with decreasing fin width.

N-Channel (Electron) P-Channel (Hole)

6 9 12 15 18 21 24

-40

-20

0

20

40

60

80

Silicon Fin Width (nm)

Piez

o-C

oeffi

cien

t (10

-11 P

a-1)

Xu, EDL 12 Saitoh, VLSI 08 Suthram, EDL 08Krishinamohan, IEDM 08

xx

yy

zz

Impact of Fin Width Scaling on Piezoresistive Coefficients

Open symbols Simulated Closed Symbols Measured

10/29/2013 15Nuo Xu EE 290D, Fall 2013

[110]

N. Xu, SOI Conf. (2012)

Impact of Fin Aspect-Ratio

0 200 400 600 800 1000 1200 1400100

200

300

400

Elec

tron

Mob

ility

(cm

2 /Vs)

Stress (MPa)

<100> CESL <100> Biaxial Tensile <110> CESL <110> Biaxial Tensile

Open: HSi= 58nm, WSi= 20nmFilled: HSi= 20nm, WSi= 58nm

Ninv = 9x1012cm-2

N-Channel (Electron) P-Channel (Hole)

• μn is highest for <100> uniaxial-strained Tri-Gate, μp is highest for <110> uniaxial-strained Tri-Gate at high level stress.

0 200 400 600 800 1000 1200 1400100

200

300

400

500Open: HSi= 58nm, WSi= 20nmFilled: HSi= 20nm, WSi= 58nm

Hol

e M

obili

ty (c

m2 /V

s)

Stress (MPa)

CESL Biaxial Compressive Biaxial Tensile

<110> Fin

Pinv=1x1013cm-2

(Uniaxial)

(Uniaxial)

(Uniaxial)

10/29/2013 16Nuo Xu EE 290D, Fall 2013

scPS simulations, N. Xu, IEDM (2010)

Strain Enhancement on Short-Channel MOSFET Performance

10/29/2013 17Nuo Xu EE 290D, Fall 2013

• Enhancement in apparent mobility is maintained vs. Lgscaling.

• ~50% of Δµ/µ can be transferred to ΔION/ION.

0 2 4 6 8 10 12 14 16 18 200

2

4

6

8

10

12

Id,lin Increase @ |Vds|=10mV (%)

I on In

crea

se @

|Vds

|=1V

(%)

Forward Back BiasVback= -0.5 ~ -1.0V

p-channel FDSOILg = 30nm ~ 80nm

Pinv=7.0e12cm-2

S = 0.54

Wafer Bending Sxx= -70 ~ -170MPa

S = 0.59

30 40 50 60 70 80 90 100

4

6

8

10

12

14

short channel % Id,lin %

Long Channel +12%

Gate Length (nm)

Stre

ss-in

duce

d En

hanc

emen

t (%

)

300K Pinv=9.5e12cm-2

Mobility vs. Gate Length ΔION/ION vs. Δidlin/Idlin under strainExpt. results, N. Xu, VLSI-T (2011,2012)

References1. Y. Sun et al., “Physics of Strain Effects in Semiconductors and metal-oxide-semiconductor field-

effect transistors,” Journal of Applied Physics, 101, 104503, 2007.2. F. Conzati et al., ”Drain Current Improvements in Uniaxially Strained P-MOSFETs: A Multi-Subband

Monte Carlo Study,” Solid-State Electronics, vol.53, pp.706-711, 2009.3. D. Esseni et al.,”Semi-Classical Transport Modeling of CMOS Transistors with Arbitrary Crystal

Orientations and Strain Engineering,” Journal of Computational Electronics, vol.8, pp.209-224,2009.

4. N. Xu et al., “Stress-induced Performance Enhancement in Ultra-Thin-Body Fully Depleted SOIMOSFETs: Impacts of Scaling,” Symposium on VLSI Technology Dig., p.162-163, 2011.

5. K. Uchida et al., “Physical Mechanisms of Electron Mobility Enhancement in Uniaxial StressedMOSFETs and Impacts of Uniaxial Stress Engineering in Ballistic Regime,” IEEE InternationalElectron Device Meeting, Tech. Dig., p.229-232, 2004.

6. K. Uchida et al., “Carrier Transport and Stress Engineering in Advanced Nanoscale TransistorsFrom (100) and (110) Transistors To Carbon Nanotube FETs and Beyond,” IEEE InternationalElectron Device Meeting, Tech. Dig., p.569-572, 2008.

7. N. Serra et al., ”Mobility Enhancement in Strained n-FinFETs: Basic Insight and StressEngineering,” IEEE Transactions on Electron Devices, vol.57, p.482-490, 2010.

8. T. Krishnamohan et al., “Comparison of (001), (110) and (111) Uniaxial- and Biaxial- Strained-Geand Strained-Si PMOS DGFETs for All Channel Orientations: Mobility Enhancement, Drive Current,Delay and Off-State Leakage,” IEEE International Electron Device Meeting, Tech. Dig., p.899-902,2008.

9. M. Saitoh et al., ”Three-Dimensional Stress Engineering in FinFETs for Mobility/On-CurrentEnhancement and Gate Current Reduction,” Symposium on VLSI Technology Dig., p.18-19, 2008.

10. K. Shin et al., “Study of Bending-Induced Strain Effects on MuGFET Performance,” IEEE ElectronDevice Letters, vol.27, p.671-673, 2006.

10/29/2013 18Nuo Xu EE 290D, Fall 2013

References11. S. Suthram et al., “Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress

Induced Performance Enhancement on Double-Gate FinFETs,” IEEE Electron Device Letters,vol.29, p.480-482, 2008.

12. J.-S. Lim et al., “Comparison of Threshold Voltage Shifts for Uniaxial and Biaxial Tensile-Stressedn-MOSFETs,” IEEE Electron Device Letters, vol.25, no.11, pp.731-733, 2004.

13. E. X. Wang et al., “Physics of Hole Transport in Strained Si MOSFET Inversion Layers,” IEEETransactions on Electron Devices, vol.53, no.8, pp.1840-1851, 2006.

14. O. Weber et al., “Examination of Additive Mobility Enhancement for Uniaxial Stress Combined withBiaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs,” IEEE InternationalElectron Device Meeting, Tech. Dig., p.719-722, 2007.

15. N. Xu et al., “MuGFET Carrier Mobility and Velocity: Impacts of Fin Aspect Ratio, Orientation andStress,” IEEE International Electron Device Meeting, Tech. Dig., p.194-197, 2010.

16. N. Xu et al., “Impact of Back Biasing on Carrier Transport in Ultra-Thin Body and BOX (UTBB) FullyDepleted SOI MOSFETs,” Symposium on VLSI Technology Dig., p.113-114, 2012.

10/29/2013 19Nuo Xu EE 290D, Fall 2013